CN103498196A - Method for fabricating silicon wafer - Google Patents
Method for fabricating silicon wafer Download PDFInfo
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- CN103498196A CN103498196A CN201310361966.3A CN201310361966A CN103498196A CN 103498196 A CN103498196 A CN 103498196A CN 201310361966 A CN201310361966 A CN 201310361966A CN 103498196 A CN103498196 A CN 103498196A
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- 238000000034 method Methods 0.000 title claims abstract description 379
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 250
- 239000010703 silicon Substances 0.000 title claims abstract description 250
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 248
- 230000008569 process Effects 0.000 claims abstract description 278
- 238000000137 annealing Methods 0.000 claims abstract description 167
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 83
- 239000001301 oxygen Substances 0.000 claims abstract description 83
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 83
- 238000010438 heat treatment Methods 0.000 claims abstract description 50
- 239000002244 precipitate Substances 0.000 claims abstract description 47
- 238000011068 loading method Methods 0.000 claims abstract description 25
- 210000000746 body region Anatomy 0.000 claims description 67
- 230000007547 defect Effects 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 36
- 239000007789 gas Substances 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000007669 thermal treatment Methods 0.000 claims description 6
- 229910021529 ammonia Inorganic materials 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000013589 supplement Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000003754 machining Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 185
- 230000001590 oxidative effect Effects 0.000 description 22
- 230000000052 comparative effect Effects 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 238000005247 gettering Methods 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000004458 analytical method Methods 0.000 description 4
- 238000003556 assay Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000002045 lasting effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02469—Group 12/16 materials
- H01L21/02472—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Abstract
The present invention provides a method for fabricating a silicon wafer, comprising: performing heat treatment to the silicon wafer to form a denuded zone and a bulk area in the silicon wafer; loading the heated silicon wafer to a heating device at a loading temperature; performing a first annealing process on the silicon wafer at a first temperature to supplementarily generate oxygen precipitate nuclei and oxygen precipitates in the bulk area; and performing a second annealing process on the silicon wafer at a second temperature higher than the first temperature to enlarge the oxygen precipitates in the bulk area, wherein the heat treatment to the silicon wafer is performed before the loading of the heated silicon wafer.
Description
The present invention is dividing an application of the denomination of invention submitted on September 28th, 2009 Chinese patent application 200910174525.6 that is " silicon wafer and manufacture method thereof ".
Related application
The present invention requires the right of priority of No. 10-2008-0095462nd, the korean patent application submitted to Korea S Department of Intellectual Property on September 29th, 2008 and on January 16th, 2009 and No. 10-2009-0003697, by reference it is incorporated to this paper.
Technical field
The present invention relates to semiconductor fabrication, more specifically relate to silicon wafer and manufacture method thereof.
Background technology
In such as nmos pass transistor and the transistorized most of high voltage devices of PMOS, usually trap forms from the about degree of depth of 5 microns to 10 microns of substrate surface.The dopant profiles of the trap that only uses ion implantation technology to be difficult to realize that the degree of depth is 5 microns to 10 microns.For this reason, should implement dopant diffusion processes by high-temperature heat treatment after ion implantation technology.
Yet, due to high-temperature heat treatment, in silicon body (bulk), can not realize oxygen precipitate fully.This cause for shallow trench isolation from the lattice defect such as the ring-type dislocation occurring at silicon substrate after the etch process of (STI).
In addition, these lattice defects make good article rate reduce, and the electrical parameter characteristic of the leakage current homogeneity during the ready mode of the deteriorated threshold voltage such as high voltage device and static RAM (SRAM) also.In addition, during manufacturing the essential foreign impurity matters test process of implementing of semiconducter device institute, these lattice defects increase for checking and analyze the time of a large amount of defects, thereby cause manufacturing the increase of the overall process time of semiconducter device.
Summary of the invention
One embodiment of the invention relate to a kind of silicon wafer, and it prevents the generation of the lattice defect that causes due to heat budget that follow-up high-temperature heat treatment process causes by increasing fully the gettering site.
Another embodiment of the invention relates to a kind of silicon wafer, and it has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of method of manufacturing silicon wafer, and it prevents the generation of the lattice defect that causes due to heat budget that follow-up high-temperature heat treatment process causes by increasing fully the gettering site.
Another embodiment of the invention relates to a kind of method of manufacturing silicon wafer, and described silicon wafer has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of by using the semiconducter device of above-mentioned silicon wafer manufacturing.
Another embodiment of the invention relates to a kind of by manufacture the method for semiconducter device by the above-mentioned method for the manufacture of silicon wafer.
According to an aspect of the present invention, provide a kind of silicon wafer, it comprises: the first denuded zone (denuded zone), and it forms the predetermined depth had from the silicon wafer end face; And body regions, it is formed between the back side of the first denuded zone and silicon wafer, wherein the first denuded zone form have from end face approximately 20 microns to the about degree of depth of 80 microns, and wherein in body regions the variation in 10% in whole body regions of the concentration of oxygen be uniformly distributed.
According to a further aspect in the invention, provide a kind of method of manufacturing silicon wafer, it comprises: the silicon wafer with denuded zone and body regions is provided; At the first temperature, this silicon wafer is implemented to the first annealing process, to supplement, produce oxygen precipitate core and oxygen precipitate in body regions; And at the second temperature higher than the first temperature, silicon wafer is implemented to the second annealing process, to increase the oxygen precipitate in body regions.
According to another aspect of the invention, provide a kind of method of manufacturing silicon wafer, it comprises: silicon wafer is provided; Silicon wafer is loaded into to heating unit inside under loading temperature; Enforcement loads by silicon wafer the first heating process that temperature is heated to the first temperature certainly; At the first temperature, implement to make the first annealing process of this silicon wafer annealing to produce oxygen precipitate; Enforcement is heated above silicon wafer the second heating process of the second temperature of the first temperature from the first temperature; The second annealing process of implementing to make silicon wafer annealing at the second temperature is to increase oxygen precipitate with for increasing its density; Enforcement is cooled to silicon wafer the process for cooling of unloading temperature from the second temperature; And the silicon wafer self-heating apparatus is offloaded to outside.
Other purpose of the present invention and advantage can be understood by following description, and become apparent with reference to embodiment of the present invention.And it will be apparent to one skilled in the art that: objects and advantages of the present invention can realize by means and the combination thereof of claim.
The accompanying drawing explanation
Fig. 1 is the cross-sectional view according to the silicon wafer of one embodiment of the invention;
Fig. 2 manufactures the cross-sectional view of the method for silicon wafer according to first embodiment of the invention for explanation;
Fig. 3 manufactures the cross-sectional view of the method for silicon wafer according to second embodiment of the invention for explanation;
Fig. 4 manufactures the cross-sectional view of the method for silicon wafer according to third embodiment of the invention for explanation;
Fig. 5 manufactures the cross-sectional view of the method for silicon wafer according to four embodiment of the invention for explanation;
Fig. 6 is the figure of explanation two step annealing process according to an embodiment of the invention;
Fig. 7 illustrates the figure of bmd density under various conditions;
Fig. 8 illustrates the figure of the degree of depth of denuded zone under various conditions;
Fig. 9 to Figure 12 for explanation under various conditions according to the figure of the degree of depth of the bmd density of oxygen concn and denuded zone;
Figure 13 is the cross-sectional view according to the silicon wafer of Comparative Examples manufacture;
Figure 14 is the cross-sectional view according to the silicon wafer of one embodiment of the invention manufacture;
The lattice defect figure of body regions in the silicon wafer that Figure 15 explanation is manufactured according to Comparative Examples;
Figure 16 illustrates the lattice defect figure of body regions in the silicon wafer that use two step annealing processs according to an embodiment of the invention manufacture;
Figure 17 A to Figure 17 D is for illustrating the method for manufacturing according to an embodiment of the invention semiconducter device;
The assay of the lattice defect in silicon wafer prepared according to Comparative Examples by Figure 18 explanation;
Scanning electronic microscope (SEM) photo of silicon wafer prepared for the oxidizing process by Comparative Examples by Figure 19;
The plane picture of silicon wafer prepared for the oxidizing process by Comparative Examples by Figure 20;
The micro image that silicon wafer prepared the oxidizing process by Comparative Examples for demonstration by Figure 21 carries out the bmd density analysis;
The assay of the lattice defect of Figure 22 explanation silicon wafer according to an embodiment of the invention;
The plane picture that Figure 23 is silicon wafer according to an embodiment of the invention;
Figure 24 is for showing the Photomicrograph that silicon wafer is according to an embodiment of the invention carried out to the bmd density analysis;
Figure 25 is the comparative result figure of explanation leakage current during static RAM (SRAM) ready mode; And
Figure 26 is the comparative result figure of explanation good article rate.
Embodiment
By reference to the following description of the embodiment of described accompanying drawing afterwards, advantage of the present invention, feature and aspect can become apparent.
In the accompanying drawings, in order to clearly demonstrate, the size in layer and zone is amplified.Also should be understood that when one deck (or film) is called as at another layer or substrate ' on ', can, directly on another layer or substrate, also can there be middle layer in it.In addition, should be understood that when one deck is called as at another layer ' under ', can, directly under another layer, also can there be one or more interposed layer in it.In addition, also should be understood that and be called as when two-layer ' between ' when one deck,, also can there be one or more interposed layer in the sole layer that it can be between two-layer.
The present invention can be by realizing high in body regions and uniform bmd density to wafer silicon with two step annealing processs.As a result, the present invention can prevent by increasing fully gettering site (gettering site) generation of the lattice defect that causes due to heat budget that follow-up high-temperature heat treatment process causes.
Fig. 1 is the cross-sectional view according to the silicon wafer of one embodiment of the invention.
As shown in Figure 1, silicon wafer 100 comprises: the first denuded zone DZ1, and the first denuded zone DZ1 forms the predetermined depth had from silicon wafer end face 101; And body regions BK, this body regions BK is formed between the first denuded zone DZ1 and the back side 102.Silicon wafer 100 also comprises the second denuded zone DZ2, and the second denuded zone DZ2 forms the predetermined depth with 102 directions towards this end face 101 from this back side.
The first denuded zone DZ1 that formation has from the predetermined depth of end face 101 direction of 102 towards the back side is area free from defect (DFZ), and there is not the lattice defect such as room and dislocation in it.Preferably, the first denuded zone DZ1 form have from end face 101 direction of 102 towards the back side approximately 20 microns to the about degree of depth of 80 microns.
The second denuded zone DZ2 is also for DFZ and form and have 102 directions towards end face 101 degree of depth identical with the first denuded zone DZI degree of depth from the back side, or, according to the glossing to the back side 102, the second denuded zone DZ2 forms the degree of depth with the degree of depth that is less than the first denuded zone DZ1.That is, when when the end face 101 to silicon wafer 100 and the back side 102, both indistinguishably carry out mirror polish, the first denuded zone DZI and the second denuded zone DZ2 form has same depth.On the contrary, while when end face 101 is carried out to mirror polish, mirror polish not being carried out in the back side 102, the second denuded zone DZ2 forms has the degree of depth that is less than the first denuded zone DZI degree of depth, and this is because form oxygen precipitate according to the roughness at the back side 102 near the back side 102.
The body regions BK formed between the first denuded zone DZI and the second denuded zone DZ2 comprises this bulky micro defect (BMD) 103.It is even that BMD103 keeps in whole body regions.BMD103 comprises throw out and body stacking fault (bulk stacking fault).In addition, can control BMD103 in body regions BK to have sufficient density, gettering is via follow-up high-temperature heat treatment process or thermal process and the metal pollutant spread on the surface of silicon wafer by this.BMD103 in body regions BK can keep density to be preferably approximately 1 * 10
5ea/cm
2to approximately 1 * 10
7ea/cm
2, more preferably approximately 1 * 10
6ea/cm
2to 1 * 10
7ea/cm
2.The concentration of oxygen in body regions BK (hereinafter referred to as ' oxygen concn ') and oxygen precipitate are closely related, preferably oxygen concn change profile in 10% and remain approximately 10.5～about 13PPMA (atom PPM) in whole body regions BK.
Fig. 2 manufactures the cross-sectional view of the method for silicon wafer according to first embodiment of the invention for explanation.
With reference to figure 2, prepare silicon wafer 200.Now, silicon wafer 200 can be naked wafer.Can form silicon wafer 200 according to following steps.At first, after growing single-crystal silicon, silicon single crystal is cut into to wafer shape.Implement etch process with etching through the surface of cut crystal or make after the sphering of the side of cut crystal, mirror polish is carried out in end face 201 and the back side 202 of silicon wafer 200.Now, use crystal growth vertical pulling method (Czochralski, CZ) to carry out growing single-crystal silicon.In addition, can after subsequent thermal technique, implement the mirror-polishing process to silicon wafer 200.
First thermal process of enforcement to silicon wafer 200, make the end face 201 of silicon wafer 200 and the oxide elements 203 between the back side 202 to internal divergence.As a result, form the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.The first thermal process can be RTP (rapid hot technics) or uses the annealing process of furnace apparatus.Preferably, the first thermal process comprises RTP.
For the end face 201 of rapid diffusion silicon wafer 200 and the oxide elements 203 in the back side 202, use argon (Ar) gas, nitrogen (N
2) gas, ammonia (NH
3) gas or its combination at high temperature implements the first thermal process.When the first thermal process is RTP, is 1050 ℃ in scope and lasts approximately 10 seconds to approximately 30 seconds to implementing the first thermal process at the about temperature of 1150 ℃.When the first thermal process is annealing process, is 1050 ℃ in scope and lasts approximately 100 minutes to approximately 300 minutes to implementing the first thermal process at the about temperature of 1150 ℃.
Then, implement the second thermal process to silicon wafer 200, make oxide elements 203 combinations in body regions BK.As a result, produce oxygen precipitate core 204.Similar with the first thermal process, the second thermal process can be RTP or uses the annealing process of furnace apparatus.The second thermal process preferably includes RTP.
For being easy to form oxygen precipitate core 204, use argon (Ar) gas, nitrogen (N
2) gas, ammonia (NH
3) gas or its be combined in lower than implementing the second thermal process at the temperature of the temperature of the first thermal process.When the second thermal process is RTP, scope be approximately 950 ℃ last approximately 10 seconds to approximately 30 seconds to implementing the second thermal process at the about temperature of 1000 ℃.When the second thermal process is annealing process, scope be approximately 950 ℃ last approximately 100 minutes to approximately 200 minutes to implementing the second thermal process at the about temperature of 1000 ℃.
Subsequently, after completing the second thermal process, silicon wafer 200 is implemented to the first annealing process.Use furnace apparatus to implement the first annealing process.By heating silicon wafer 200 under the preset temperature of the temperature lower than the second thermal process, supplement the oxygen precipitate core 204 produced in body regions BK, simultaneously, produce oxygen precipitate 205A.Preferably, scope be approximately 750 ℃ last approximately 100 minutes to approximately 180 minutes to implementing the first annealing process at the about temperature of 800 ℃.In addition, at oxygen (O
2) atmosphere encloses lower enforcement the first annealing process.
After completing the first annealing process, silicon wafer 200 is implemented to the second annealing process.Also use furnace apparatus to implement the second annealing process.By heating silicon wafer 200 under the preset temperature of the temperature higher than the first annealing process, increase oxygen precipitate 205A.As a result, produce the oxygen precipitate 205B through increasing.Preferably, scope be approximately 1000 ℃ last approximately 100 minutes to approximately 180 minutes to implementing the second annealing process at the about temperature of 1150 ℃.In addition, at oxygen (O
2) atmosphere encloses lower enforcement the second annealing process.
Hereinafter, describe the first annealing process and the second annealing process in detail.Hereinafter, the first annealing process and the second annealing process are called to two step annealing processs.
Fig. 6 is the graphic representation of explanation according to two step annealing processs of an embodiment of the present invention.
Referring to Fig. 6, use the annealing process of furnace apparatus to comprise use oxygen (O
2) gas makes first annealing process (II) of silicon wafer 200 annealing and implement to make second annealing process (IV) of silicon wafer 200 annealing at the second temperature higher than the first temperature at the first temperature.Implement the first annealing process (II) and the second annealing process (IV) and all last approximately 100 minutes to approximately 180 minutes.The scope of the first temperature of the first annealing process (II) is approximately 750 ℃ to approximately 800 ℃, and the scope of the second temperature of the second annealing process (IV) is approximately 1000 ℃ to approximately 1150 ℃.
Effect for improvement oxidizing process and thermal treatment process, front at the first annealing process (II), can further comprise that according to the two step annealing processs of embodiment of the present invention that silicon wafer 200 is loaded into to furnace apparatus is inner and then silicon wafer 200 is retained to the loading process (L) that loading temperature lasts a predetermined lasting time.And, after the second annealing process (IV), according to the two step annealing processs of embodiment of the present invention, can further be included in before silicon wafer 200 is offloaded to the furnace apparatus outside silicon wafer 200 is retained to the uninstall process (UL) that unloading temperature lasts a predetermined lasting time.
The loading temperature of loading process (L) is lower than the first temperature.Preferably, the scope of loading temperature is approximately 600 ℃ to approximately 700 ℃.During loading process (L) not by oxygen supply to furnace apparatus.As a result, during loading process (L), silicon wafer 200 is not subject to oxidation.The unloading temperature of uninstall process (UL) equals the first temperature substantially.Preferably, the scope of unloading temperature is approximately 750 ℃ to approximately 800 ℃.During uninstall process (UL), not supply oxygen and the supply of nitrogen only.The scope of the flow rate of nitrogen is that about 9slm is to about 11slm.
In addition, according to the two step annealing processs of embodiment of the present invention can further be included between loading process (L) and the first annealing process (II) for the first heating process (I) of loading temperature being heated to the first temperature and between the first annealing process (II) and the second annealing process (IV) for the first temperature being heated to second heating process (III) of the second temperature.When during the first heating process (I) and the second heating process (III), the per minute temperature rise rate is too high, chip architecture may be out of shape.Therefore, the temperature rise rate in the first heating process (I) and the second heating process (III) can be set as approximately to 5 ℃/minute to the about scope of 8 ℃/minute.
And, according to the two step annealing processs of embodiment of the present invention can further be included between the second annealing process (IV) and uninstall process (UL) for the second temperature being cooled to the process for cooling (V) of unloading temperature.The scope of the rate of temperature fall of process for cooling (V) can be approximately 2 ℃/minute to approximately 4 ℃/minute.
In the two step annealing processs according to embodiment of the present invention, the annealing of silicon wafer 200 mainly realizes substantially during the first annealing process and the second annealing process (II, IV), because supply oxygen during these techniques only.The scope of the flow rate of the oxygen of supplying during the first annealing process and the second annealing process (II, IV) can be about 50sccm to about 120sccm.Can implement the first annealing process and the second annealing process (II, IV) and all last approximately 100 minutes to approximately 180 minutes.
The following embodiment according to the present invention that can be applicable to show in Fig. 3 to Fig. 5 as the two step annealing processs of describing in Fig. 6 is for the manufacture of the first annealing process and second annealing process of the method for silicon wafer.
Fig. 3 is the cross-sectional view of explanation according to the method for the manufacture of silicon wafer of the second embodiment of the present invention.
Referring to Fig. 3, implement the thermal process to silicon wafer 300, make the end face 301 of silicon wafer 300 and the oxide elements 303 between the back side 302 to internal divergence.As a result, form the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.Thermal process can be RTP or uses the annealing process of furnace apparatus.Preferably, the first thermal process comprises RTP.
For the end face 301 of rapid diffusion silicon wafer 300 and the oxide elements 303 at the back side 302, at high temperature implement thermal process.When thermal process is RTP, is 1050 ℃ in scope and lasts approximately 10 seconds to approximately 30 seconds to implementing thermal process at the about temperature of 1150 ℃.When thermal process is annealing process, is 1050 ℃ in scope and lasts approximately 100 minutes to approximately 200 minutes to implementing thermal process at the about temperature of 1150 ℃.
Subsequently, silicon wafer 300 is implemented to the first annealing process, make oxide elements 203 combinations in body regions BK.As a result, form oxygen precipitate core 304.Under the preset temperature of the temperature lower than thermal process, use furnace apparatus to implement the first annealing process.Preferably, scope be approximately 750 ℃ last approximately 100 minutes to approximately 180 minutes to implementing the first annealing process at the about temperature of 800 ℃.In addition, at oxygen (O
2) atmosphere encloses lower enforcement the first annealing process.
Fig. 4 is the cross-sectional view of explanation according to the method for the manufacture of silicon wafer of the 3rd embodiment of the present invention.
In Fig. 4, the thermal process be implemented in the first annealing process at the temperature of the thermal process temperature lower than Fig. 3 before.
With reference to figure 4, at the temperature of the thermal process temperature lower than Fig. 3, silicon wafer 400 is implemented to thermal process.Therefore, produce oxygen precipitate core 404.Because thermal process is implemented at low temperatures, so form oxygen precipitate core 404 in the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.Thermal process can be RTP or annealing process.Preferably, the first thermal process comprises RTP.When thermal process is RTP, approximately 950 ℃ to approximately at the temperature of 1000 ℃, implementing thermal process approximately 10 seconds to approximately 30 seconds.When thermal process is annealing process, approximately 950 ℃ to approximately at the temperature of 1000 ℃, implementing thermal process approximately 100 minutes to approximately 200 minutes.
Subsequently, silicon wafer 400 is implemented to the first annealing process and the second annealing process successively, make and produce oxygen precipitate core 404 and oxygen precipitate 405A.Implement the first annealing process and the second annealing process under identical condition in those conditions of the first annealing process with Fig. 3 and the second annealing process.
Fig. 5 manufactures the cross-sectional view of the method for silicon wafer according to four embodiment of the invention for explanation.
With reference to figure 5, different from the annealing process shown in Fig. 2 to Fig. 4, according to the annealing process of four embodiment of the invention without the extra heat technique before the first annealing process and the second annealing process.That is, be provided as the silicon wafer 500 of naked wafer, and silicon wafer 500 is implemented to the first annealing process and the second annealing process successively, make and form the first denuded zone DZI and the second denuded zone DZ2 and body regions BK.Implement the first annealing process and the second annealing process under identical condition in those conditions of the first annealing process with shown in Fig. 2 to Fig. 4 and the second annealing process.
In Fig. 5, Reference numeral ' 501 ' means end face, and ' 502 ' means the back side, and ' 503 ' means oxide elements, and ' 504 ' means oxygen precipitate core, and ' 505A ' means oxygen precipitate, and ' 505B ' means the oxygen precipitate increased.
The method of silicon wafer constructed in accordance is described referring to figs. 2 to Fig. 5 as mentioned above.As previously mentioned, at first shown in Fig. 2 to Fig. 4 to the 3rd embodiment, RTP preferably before the first annealing process and the second annealing process for thermal process.
The subsurface defect of the oxygen precipitate in silicon wafer or void defects can be controlled during monocrystalline silicon growing, or by thermal process, control after monocrystalline silicon growing.As described above, thermal process can comprise the RTP that uses halogen lamp and the annealing process that uses furnace apparatus.
At argon (Ar) gas or hydrogen (H
2) atmosphere is greater than approximately 100 minutes long-time at the annealing process higher than implementing to use furnace apparatus under the about high temperature of 1000 ℃ under enclosing.Diffusion by oxide elements in the silicon wafer that annealing process causes thus and silicon are reset, and in the part of the end face of silicon wafer, form device ideal area (that is, nondefective zone (DFZ)).Yet, along with silicon wafer sizes increases, this annealing process is because high-temperature heat treatment is difficult to control pollution or the slip dislocation of silicon wafer.
Therefore, RTP obtains the silicon wafer characteristic that is better than annealing process.Yet, when the silicon wafer that uses various defect detecting methods assessments to be manufactured by RTP, control oxygen precipitate only from end face approximately 3 microns to the about degree of depth of 10 microns.In addition, when when only implementing RTP and manufacture silicon wafer once or twice, exist realizing the restriction of high bmd density in body regions.More specifically, when by enforcement RTP, once manufacturing silicon wafer, bmd density is through being defined as 1 * 10
6ea/cm
2to 3 * 10
6ea/cm
2, and be difficult to make bmd density to exceed this scope.
In embodiments of the invention, as shown in Figures 2 to 4, implement two step annealing processs after thermal process, remove thus void defects and oxygen precipitate near the silicon wafer end face.As a result, the present invention can guarantee nondefective zone (DFz) and increase the stacking defect of body comprise in body regions and the bmd density of oxygen precipitate, improve the gettering effect by the gettering site increased in body regions thus.
Hereinafter, reference table 1 and table 2 are described the characteristic of the silicon wafer of being manufactured by embodiment of the present invention in detail.
[table 1]
[table 2]
In table 1, use argon (Ar) gas, nitrogen (N
2) gas, ammonia (NH
3) gas or its combination, implement ' high temperature RTP ' and ' low temperature RTP ' approximately 10 seconds to approximately 30 seconds under rapid thermal process.Use oxygen (O
2) gas implements ' low temperature annealing process ' and ' high-temperature annealing process ' approximately 100 minutes to approximately 180 minutes.
In table 1 and table 2, ' the first embodiment shown in condition 1 ' presentation graphs 2, ' the second embodiment shown in condition 2 ' presentation graphs 3, ' the 3rd embodiment shown in condition 3 ' presentation graphs 4, ' the 4th embodiment shown in condition 4 ' presentation graphs 5.Table 2 shows bmd density and denuded zone (DZ) degree of depth according to the oxygen concn in each condition (oi).
The figure of the parameter that Fig. 7 to Figure 12 is indicator gauge 1 and table 2.Particularly, Fig. 7 is the figure of explanation for the bmd density of each condition.Fig. 8 is the figure of explanation for the DZ degree of depth of each condition.Fig. 9 to Figure 12 is the figure of explanation for oxygen concn in the body regions of each condition.
Reference table 2 and Fig. 7, all obtain and be greater than 1 * 10 under all conditions
5ea/cm
2bmd density.Particularly, regardless of oxygen concn, in condition, all obtain and be greater than 1 * 10 for 1 time
6ea/cm
2bmd density.Although do not show that measurable this bmd density is compared significantly lower with the bmd density under above condition for the data of the bmd density by only implementing the silicon wafer that RTP manufactures once or twice.
As previously mentioned, control metal pollutant by gettering BMD.Yet, because bmd density tends to reduce during high-temperature technology, during manufacturing silicon wafer, need to guarantee high bmd density.Generally speaking, the high voltage device that semiconducter device need to operate under high voltage environment.For manufacturing this high voltage device, essential severe ion implantation technology and the high-temperature annealing process implemented, this is because need to have the tie region (that is, doped region) of dark distribution.When bmd density reduces during high-temperature annealing process, not only due to defect estimation but also due to low gettering ability, so occur the ring-type dislocation at follow-up shallow trench isolation after (STI).
As the result of measuring bmd density, when bmd density is approximately 2.5 * 10
5ea/cm
2the time part ring-type dislocation appears, but when bmd density be approximately 4.4 * 10
5ea/cm
2the time ring-type dislocation do not appear.Therefore, need to control bmd density and be greater than at least 1 * 10
5ea/cm
2.In the present embodiment, during manufacturing silicon wafer, regardless of conventional thermal process, for the initial process of manufacturing semiconducter device, all to implement in addition two step annealing processs.Initial process is included in the ion implantation oxidizing process of implementing before that forms trap.Oxidizing process is corresponding to be used to form the technique of screen oxide layer during forming ion implantation (hereinafter, be called trap ion implantation) of trap.
Reference table 2 and Fig. 8, show the DZ degree of depth according to each condition.The DZ degree of depth and bmd density and oxygen concn are closely related.Along with bmd density and oxygen concn increase, the DZ degree of depth reduces.When oxygen concn, under each condition all for example, when identical (, being 11.6 in table 2), the bmd density under condition 1 and condition 2 is higher than the bmd density under condition 3 and condition 4, but the DZ degree of depth under condition 1 and condition 2 is lower than the DZ degree of depth under condition 3 and condition 4.Therefore, the DZ degree of depth can be the tolerance of bmd density.
Reference table 2 and Fig. 9 to Figure 12, show under each condition bmd density and the DZ degree of depth according to oxygen concn.Along with oxygen concn (Oi) increases, bmd density increases and the DZ degree of depth reduces.Therefore, oxygen concn (Oi) is also the tolerance of bmd density.That is, can calculate the bmd density in body regions by measuring the DZ degree of depth and oxygen concn (Oi).
The cross-sectional view that Figure 13 and Figure 14 are silicon wafer.
Particularly, Figure 13 shows by implementing RTP only the cross-sectional view with the silicon wafer manufactured without two step annealing processs, and Figure 14 shows the cross-sectional view by the silicon wafer implementing two step annealing processs and manufacture according to one embodiment of the invention.
As shown in the figure, a plurality of silicon dislocations occur in the silicon wafer of Figure 13, but do not have the silicon dislocation in the silicon wafer of Figure 14.In addition, when by the use epitaxy, forming epitaxial film, the lattice defect in the body regions of silicon wafer (wherein forming epitaxial film) is significantly reduced.
Figure 15 and Figure 16 illustrate the lattice defect figure of body regions in silicon wafer (wherein forming epitaxial film).The verifying attachment that use is manufactured by KLA company is implemented this check.
As shown in Figure 15, when implementing not have the oxidizing process of two step annealing processs, a large amount of lattice defects are distributed in figure.At this, oxidizing process forms screen oxide layer during trap is ion implantation.On the contrary, as shown in Figure 16, when implementing to have the oxidizing process of two step annealing processs of the present invention, lattice defect significantly reduces.
Hereinafter, describe the method for manufacturing for the semiconducter device with trap of high voltage device in detail with reference to Figure 17 A to Figure 17 D, the method comprises two step annealing processs according to an embodiment of the invention.
Figure 17 A to Figure 17 D is for illustrating the method for manufacturing according to an embodiment of the invention semiconducter device.
With reference to figure 17A, use the two step annealing processs that show in Fig. 6 to form screen oxide layer 601 on silicon wafer 600.Silicon wafer 600 can be the enforcement RTP wafer once or twice described in Fig. 2 to Fig. 4, or is the naked wafer of not implementing RTP as shown in Figure 5.Screen oxide layer 601 can be silicon oxide layer, and forms approximately
extremely approximately
thickness.
With reference to figure 17B, form trap 602 to one predetermined depths in silicon wafer 600.Trap 602 can be p-type or N-shaped conduction type according to the conduction type of high voltage device.
Referring to Figure 17 C, pad nitride layer (not shown) as hard mask is formed on screen oxide layer 601, or pad nitride layer is formed on the buffer layer (not shown), this buffer layer is by forming removing the rear enforcement excess oxygen of screen oxide layer 601 metallization processes.The reason that removes screen oxide layer 601 is that screen oxide layer 601 is not suitable for buffer layer, and this is because screen oxide layer 601 is damaged during ion implantation technology.Then be formed for forming the photoetching agent pattern 604 of sti trench groove on pad nitride layer.
Pad nitride layer can be passed through low-pressure chemical vapor deposition (LPCVD) technique and form, by being minimized in during depositing operation the stress that is applied to silicon wafer 600, to prevent that silicon wafer 600 is impaired.Pad nitride layer can be formed by silicon nitride.Pad nitride layer can form approximately
extremely approximately
thickness.
Use photoetching agent pattern 604 as etching mask, partly etching pad nitride layer, screen oxide layer 601 and silicon wafer 600, form pad nitride pattern 603, screen oxide pattern 601A, silicon wafer 600A and trap 602A thus successively.As a result, form the groove 605 with predetermined depth and slope in silicon wafer 600A.
Referring to Figure 17 D, form the device isolation structure 606 of filling groove 605, remove subsequently pad nitride pattern 603 and screen oxide pattern 601A.Device isolation structure 606 can be formed by the high density plasma with excellent gap-filling properties (HDP) layer.
In method more of the present invention and Comparative Examples, the beneficial effect of above embodiment of the present invention hereinafter will be described.Method of the present invention comprises that the oxidizing process by using two step annealing processs forms screen oxide layer, and Comparative Examples comprises that the oxidizing process by using a step annealing technique forms screen oxide layer.In the oxidizing process of this Comparative Examples, use wet oxidation process silicon wafer at the single temperature of 800 ℃ to 850 ℃.
Defect in silicon wafer prepared by Figure 18 to Figure 21 explanation oxidizing process by Comparative Examples.
Specifically, after forming groove via STI technique in silicon wafer prepared in the oxidizing process by Comparative Examples by Figure 18 explanation, the diagram data of the lattice defect of being checked by the verifying attachment of KLA company manufacturing.As shown in figure 18, can be observed in most of defect chips and have the lattice defect such as ring-type silicon dislocation.
Silicon wafer scanning electronic microscope (SEM) photo that Figure 19 and Figure 20 obtain for the verifying attachment by the manufacturing of KLA company.
Particularly, Figure 19 is for showing the SEM image in silicon wafer cross section, and Figure 20 is plane inclination STM image.As shown in FIG. 19 and 20, can be observed and have lattice defect and dislocation.
Figure 21 is for showing the Photomicrograph that the silicon wafer with ring-type defect is carried out to this bulky micro defect (BMD) density analysis.
As shown in Figure 21, can be observed the end face formation of most of BMD near silicon wafer, and only have minority BMD to be formed in the middle body of silicon wafer, that is, be formed in body regions.That is, the bmd density of body regions is significantly lower than the bmd density of the end face of silicon wafer.
Figure 22 to Figure 24 is the assay by lattice defect in the use silicon wafer that according to embodiments of the present invention prepared by the oxidizing process of two step annealing processs.This check is used the verifying attachment of being manufactured by KLA company to implement.
Specifically, the assay of the lattice defect of silicon wafer after Figure 22 explanation forms groove via STI technique in silicon wafer prepared by the oxidizing process of the two step annealing processs of the application of the invention.As shown in figure 22, can be observed that lattice defect is removed and some particulates or dust only detected.
The plane inclination STM image that Figure 23 is the silicon wafer that obtained by the verifying attachment of KLA company manufacturing.Similar with the result of Figure 22, can be observed and some particles only detected.
The Photomicrograph that silicon wafer prepared for the oxidizing process shown the application of the invention two step annealing processs by Figure 24 carries out the bmd density analysis.As shown in figure 24, can be observed and evenly form BMD in whole silicon wafer.
Figure 25 is the comparative result figure of explanation leakage current during static RAM (SRAM) ready mode.In Figure 25, the figure on the left side shows the sample of high voltage device prepared by the oxidizing process of the application of the invention two step annealing processs, the sample of the high voltage device of the figure display comparison example on the right.As shown in figure 25, the sample prepared with oxidizing process by Comparative Examples is compared, and can be observed the sample prepared by oxidizing process of the present invention and shows even leakage current characteristic.
Figure 26 is the comparative result figure of explanation good article rate.In Figure 26, the figure on the left side shows the sample of high voltage device prepared by the oxidizing process of the application of the invention two step annealing processs, the sample of the high voltage device of the figure display comparison example on the right.As shown in figure 26, with the sample of Comparative Examples, compare the high about 5%-9% of the good article rate of the sample prepared by oxidizing process of the present invention.
According to the present invention, at first, can produce fully the gettering site in silicon wafer by under differing temps, implementing two step annealing processs.This makes the generation that can prevent the lattice defect that causes due to heat budget that follow-up high-temperature heat treatment process causes.
Secondly, the present invention can be by the silicon wafer that enforcement two step annealing processs have height and Uniform B MD density in being provided at body regions under differing temps.
The 3rd, according to the present invention, after under differing temps, silicon wafer being implemented to two step annealing processs, use epitaxy to form epitaxial film on silicon wafer.As a result, the present invention can provide the semiconducter device that forms the epitaxial film with excellent specific property.
The 4th, according to the present invention, by under differing temps, silicon wafer being implemented to two step annealing processs with form screen oxide layer on silicon wafer after, by using screen oxide layer, as the ion mask, implement ion implantation technology to form trap in silicon wafer.As a result, the present invention can produce fully the gettering site in silicon wafer, with the generation of the lattice defect that heat budget was caused that prevents from thus causing due to follow-up high-temperature heat treatment process.
Although for particular, described the present invention, those skilled in the art obviously can make various changes and modification in the situation that do not depart from the spirit of the present invention and the category that are limited by following claim.
Remarks
1. 1 kinds of silicon wafers of remarks, it comprises: the first denuded zone, it forms the predetermined depth had from the end face of described silicon wafer; And body regions, it is formed between the back side of described the first denuded zone and described silicon wafer, wherein said the first denuded zone form have from described end face approximately 20 microns to the about degree of depth of 80 microns, and the variation in 10% in whole described body regions of the oxygen concn in wherein said body regions is uniformly distributed.
Remarks 5. is as the silicon wafer of remarks 1, and it also comprises the second denuded zone, and described the second denuded zone is formed at described body regions below and has the predetermined depth towards the direction of described end face from the described back side.
Remarks 6. is as the silicon wafer of remarks 5, and wherein said the second denuded zone forms has from the described back side approximately 20 microns to the about degree of depth of 80 microns.
7. 1 kinds of methods for the manufacture of silicon wafer of remarks, it comprises: the silicon wafer with denuded zone and body regions is provided; At the first temperature, described silicon wafer is implemented to the first annealing process and produce oxygen precipitate core and oxygen precipitate to supplement in described body regions; With at the second temperature higher than described the first temperature, described silicon wafer is implemented to the second annealing process with the described oxygen precipitate in increasing described body regions.
Remarks 11. is as the method for remarks 10, and wherein said the first thermal process and described the second thermal process are implemented by rapid hot technics (RTP) or annealing process.
Remarks 12. is as the method for remarks 10, wherein said the first thermal process approximately 1050 ℃ to approximately implementing at the temperature of 1150 ℃, described the second thermal process approximately 950 ℃ to approximately implementing at the temperature of 1000 ℃.
Remarks 13. is as the method for remarks 10, and wherein said the first thermal process and described the second thermal process are used argon (Ar) gas, nitrogen (N
2) gas, ammonia (NH
3) gas or its combination.
Remarks 14. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: described silicon wafer is implemented to thermal process to form described denuded zone and described body regions being equal to or less than at the 3rd temperature of described the second temperature.
Remarks 15. is as the method for remarks 14, wherein said thermal process approximately 1050 ℃ to approximately implementing at the temperature of 1150 ℃.
Remarks 16. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: higher than described the first temperature, at lower than the 3rd temperature of described the second temperature, described silicon wafer is being implemented to thermal process to form described denuded zone and described body regions.
Remarks 17. is as the method for remarks 16, wherein said thermal process approximately 950 ℃ to approximately implementing at the temperature of 1000 ℃.
Remarks 18. is as the method for remarks 7, and wherein said the first annealing process and described the second annealing process are at oxygen (O
2) atmosphere encloses lower enforcement.
Remarks 19. is as the method for remarks 7, and the two all implements wherein said the first annealing process and described the second annealing process approximately 100 minutes to approximately 180 minutes.
Remarks 21. is as the method for remarks 7, and wherein after implementing described the second annealing process, described body regions comprises that the density of this bulky micro defect (BMD) of described oxygen precipitate controls as approximately 1 * 10
5ea/cm
2to approximately 1 * 10
7ea/cm
2.
Remarks 22. is as the method for remarks 7, and wherein after implementing described the second annealing process, the oxygen concn in described body regions is controlled and is uniformly distributed for the variation in 10% in whole described body regions.
Remarks 23. is as the method for remarks 7, and wherein after implementing described the second annealing process, the oxygen concn in described body regions is controlled as approximately 10.5 to about 13PPMA.
Remarks 24. is as the method for remarks 7, and it also comprises: remove the oxide skin formed on the end face at described silicon wafer during described the second annealing process; With form epitaxial film by epitaxy, described epitaxial film is formed on the end face of described silicon wafer.
Remarks 25. is as the method for remarks 7, and it also comprises: form trap as buffer layer by using oxide skin in described silicon wafer, wherein said oxide skin is formed on the end face of described silicon wafer during described the second annealing process.
Remarks 26. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: growing single-crystal silicon; The silicon single crystal of described growth is cut into to wafer shape; With implement etch process with the surface of the silicon wafer of the described cutting of etching or make the side sphering of the silicon wafer of described cutting.
27. 1 kinds of methods of manufacturing silicon wafer of remarks, it comprises: silicon wafer is provided; Under loading temperature, described silicon wafer is loaded into to heating unit inside; Enforcement is heated to described silicon wafer the first heating process of the first temperature from described loading temperature; At described the first temperature, implement to make the first annealing process of described silicon wafer annealing to produce oxygen precipitate; Enforcement is heated above described silicon wafer the second heating process of the second temperature of described the first temperature from described the first temperature; The second annealing process of implementing to make described silicon wafer annealing at described the second temperature to be to increase described oxygen precipitate, thereby increases its density; Enforcement is cooled to described silicon wafer the process for cooling of unloading temperature from described the second temperature; With described silicon wafer is offloaded to outside from described heating unit.
Remarks 28. is as the method for remarks 27, and providing of wherein said silicon wafer comprises: by described silicon wafer being implemented to thermal process to form denuded zone and body regions in described silicon wafer.
Remarks 29. is as the method for remarks 27, and wherein said loading temperature is approximately 600 ℃ to approximately 700 ℃.
Remarks 31. is as the method for remarks 27, and wherein said the first temperature is approximately 750 ℃ to approximately 800 ℃.
Remarks 32. is as the method for remarks 27, and the temperature rise rate of wherein said the second heating process is approximately 5 ℃/minute to approximately 8 ℃/minute.
Remarks 33. is as the method for remarks 27, wherein said the second temperature be approximately 1000 ℃ to about 11S0 ℃.
Remarks 34. is as the method for remarks 27, and the rate of temperature fall of wherein said process for cooling is approximately 2 ℃/minute to approximately 4 ℃/minute.
Remarks 35. is as the method for remarks 27, and wherein said unloading temperature is approximately 750 ℃ to approximately 800 ℃.
Remarks 36. is as the method for remarks 27, and nitrogen (N is used in wherein said silicon wafer unloading
2) gas enforcement.
Remarks 37. is as the method for remarks 27, and wherein said the first annealing process and described the second annealing process are used oxygen (O
2) gas enforcement.
Claims (34)
1. the method for the manufacture of silicon wafer, it comprises:
Described silicon wafer is heat-treated to form denuded zone and body regions in described silicon wafer;
Will be in heat treated described silicon wafer be loaded into heating unit under loading temperature;
At the first temperature, described silicon wafer is implemented to the first annealing process and produce oxygen precipitate core and oxygen precipitate to supplement in described body regions; With
At the second temperature higher than described the first temperature, described silicon wafer is implemented to the second annealing process with the described oxygen precipitate in increasing described body regions;
The described thermal treatment of wherein said silicon wafer was carried out before the described loading through heat treated described silicon wafer.
2. method as claimed in claim 1, wherein said the first annealing process is implemented at the temperature of 750 ℃ to 800 ℃.
3. method as claimed in claim 1, wherein said the second annealing process is implemented at the temperature of 1000 ℃ to 1150 ℃.
4. method as claimed in claim 1, the described thermal treatment of wherein said silicon wafer comprises:
Described silicon wafer is implemented to the first thermal process to form described denuded zone and described body regions being equal to or less than at the 3rd temperature of described the second temperature; With
At lower than the 4th temperature of described the 3rd temperature, described silicon wafer is being implemented to the second thermal process to form described oxygen precipitate core in described body regions higher than described the first temperature.
5. method as claimed in claim 4, wherein said the first thermal process and described the second thermal process are implemented by rapid hot technics (RTP) or annealing process.
6. method as claimed in claim 4, wherein said the first thermal process is implemented at the temperature of 1050 ℃ to 1150 ℃, and described the second thermal process is implemented at the temperature of 950 ℃ to 1000 ℃.
7. method as claimed in claim 4, wherein said the first thermal process and described the second thermal process are used argon (Ar) gas, nitrogen (N
2) gas, ammonia (NH
3) gas or its combination.
8. method as claimed in claim 1, the described thermal treatment of wherein said silicon wafer comprises:
Described silicon wafer is implemented to thermal process to form described denuded zone and described body regions being equal to or less than at the 3rd temperature of described the second temperature.
9. method as claimed in claim 8, wherein said thermal process is implemented at the temperature of 1050 ℃ to 1150 ℃.
10. method as claimed in claim 1, the described thermal treatment of wherein said silicon wafer comprises:
At lower than the 3rd temperature of described the second temperature, described silicon wafer is being implemented to thermal process to form described denuded zone and described body regions higher than described the first temperature.
11., as the method for claim 10, wherein said thermal process is implemented at the temperature of 950 ℃ to 1000 ℃.
12. method as claimed in claim 1, wherein said the first annealing process and described the second annealing process are at oxygen (O
2) atmosphere encloses lower enforcement.
13. method as claimed in claim 1, the two all implements wherein said the first annealing process and described the second annealing process 100 minutes to 180 minutes.
14. method as claimed in claim 1, wherein said denuded zone forms the degree of depth had from 20 microns to 80 microns of the end faces of described silicon wafer.
15. method as claimed in claim 1, wherein after implementing described the second annealing process, described body regions comprises that the density of this bulky micro defect (BMD) of described oxygen precipitate controls as being greater than 5 * 10
6ea/cm
2and be less than or equal to 1 * 10
7ea/cm
2.
16. method as claimed in claim 1, wherein after implementing described the second annealing process, the oxygen concn in described body regions is controlled and is uniformly distributed for the variation in 10% in whole described body regions.
17. method as claimed in claim 1, wherein after implementing described the second annealing process, it is 10.5 to 13PPMA that the oxygen concn in described body regions is controlled.
18. method as claimed in claim 1, it also comprises:
Remove the oxide skin formed on the end face at described silicon wafer during described the second annealing process; With
Form epitaxial film by epitaxy, described epitaxial film is formed on the end face of described silicon wafer.
19. method as claimed in claim 1, it also comprises:
By using oxide skin to form trap as buffer layer in described silicon wafer, wherein said oxide skin is formed on the end face of described silicon wafer during described the second annealing process.
20. method as claimed in claim 1, providing of wherein said silicon wafer comprises:
Growing single-crystal silicon;
The silicon single crystal of described growth is cut into to wafer shape; With
Implement etch process with the surface of the silicon wafer of the described cutting of etching or make the side sphering of the silicon wafer of described cutting.
21. a method of manufacturing silicon wafer, it comprises:
Silicon wafer is heat-treated to form denuded zone and body regions in described silicon wafer;
To be loaded into heating unit inside through heat treated described silicon wafer under loading temperature;
Enforcement is heated to loaded silicon wafer the first heating process of the first temperature from described loading temperature;
At described the first temperature, implement to make first annealing process of annealing through the described silicon wafer of the first heating described, in the described silicon wafer of the first heating, to produce oxygen precipitate;
Enforcement will be heated to the second heating process of the second temperature through the described silicon wafer of the first annealing from described the first temperature, described the second temperature is higher than described the first temperature;
At described the second temperature, implement to make second annealing process of annealing through the described silicon wafer of the second heating to increase described oxygen precipitate, thereby increase described density in the described silicon wafer of the first heating;
Enforcement will be cooled to the process for cooling of unloading temperature through the described silicon wafer of the second annealing from described the second temperature; With
To be offloaded to outside from described heating unit through cooling described silicon wafer.
22., as the method for claim 21, wherein said loading temperature is 600 ℃ to 700 ℃.
23., as the method for claim 21, the temperature rise rate of wherein said the first heating process is 5 ℃/minute to 8 ℃/minute.
24., as the method for claim 21, wherein said the first temperature is 750 ℃ to 800 ℃.
25., as the method for claim 21, the temperature rise rate of wherein said the second heating process is 5 ℃/minute to 8 ℃/minute.
26., as the method for claim 21, wherein said the second temperature is 1000 ℃ to 1150 ℃.
27., as the method for claim 21, the rate of temperature fall of wherein said process for cooling is 2 ℃/minute to 4 ℃/minute.
28., as the method for claim 21, wherein said unloading temperature is 750 ℃ to 800 ℃.
29., as the method for claim 21, nitrogen (N is used in wherein said silicon wafer unloading
2) gas enforcement.
30., as the method for claim 21, wherein said the first annealing process and described the second annealing process are used oxygen (O
2) gas enforcement.
31., as the method for claim 21, wherein said silicon wafer comprises unadulterated silicon wafer.
32., as the method for claim 21, the described thermal treatment of wherein said silicon wafer was carried out before the described loading through heat treated described silicon wafer.
33. the method for a semiconductor machining comprises:
In under loading temperature, unadulterated silicon wafer being loaded into to heating unit;
Loaded described unadulterated silicon wafer is carried out to first from described loading temperature and be heated to the first temperature;
At described the first temperature, the described unadulterated silicon wafer through the first heating is carried out to the first annealing in the described silicon wafer through the first heating, to produce oxygen precipitate;
To directly from described the first temperature, carry out second through the described unadulterated described silicon wafer of the first annealing and be heated to the second temperature, described the second temperature is higher than described the first temperature;
At described the second temperature, the described silicon wafer through the second heating is carried out to second and anneal to increase described described oxygen precipitate in the described silicon wafer of the second heating and the density that increases described described oxygen precipitate in the described silicon wafer of the second heating;
To be cooled to unloading temperature from described the second temperature through the described silicon wafer of the second annealing; With under unloading temperature from the unloading of described heating unit through cooling described silicon wafer.
34. as the method for claim 33, before also being included in the described loading of described unadulterated silicon wafer:
Described unadulterated silicon wafer is heat-treated to form denuded zone and body regions in described silicon wafer.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20080095462 | 2008-09-29 | ||
| KR10-2008-0095462 | 2008-09-29 | ||
| KR1020090003697A KR20100036155A (en) | 2008-09-29 | 2009-01-16 | Silicon wafer and fabrication method thereof |
| KR10-2009-0003697 | 2009-01-16 | ||
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- 2009-09-09 TW TW098130435A patent/TWI395844B/en active
- 2009-09-28 CN CN201310361966.3A patent/CN103498196B/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2010087512A (en) | 2010-04-15 |
| TWI395844B (en) | 2013-05-11 |
| JP5940238B2 (en) | 2016-06-29 |
| KR20110049764A (en) | 2011-05-12 |
| CN103498196B (en) | 2015-07-01 |
| CN101713098A (en) | 2010-05-26 |
| KR20100036155A (en) | 2010-04-07 |
| CN101713098B (en) | 2013-09-18 |
| KR101423367B1 (en) | 2014-08-04 |
| TW201026914A (en) | 2010-07-16 |
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