TWI395844B - Silicon wafer and fabrication method thereof - Google Patents

Description

Silicon wafer and its manufacturing method

The present invention relates to semiconductor fabrication techniques and, more particularly, to germanium wafers and methods of fabricating the same.

The present invention claims priority to Korean Patent Application No. 10-2008-0095462 and No. 10-2009-0003697, filed on Sep. 29, 2008, and Jan. 16, 2009, to the Korean Intellectual Property Office. This is incorporated herein by reference.

In most high voltage devices, such as NMOS transistors and PMOS transistors, a well is typically formed from the surface of one of the substrates to a depth of approximately 5 microns to 10 microns. It is difficult to achieve a doping profile of a well having a depth of 5 microns to 10 microns using only an ion implantation process. For this reason, it is necessary to perform a dopant diffusion process using a high temperature heat treatment after the ion implantation process.

However, due to the high temperature heat treatment, oxygen evolution cannot be completely achieved in the crucible body. This causes crystal defects such as ring dislocations to occur in the germanium substrate after the etching process for shallow trench isolation (STI).

In addition, such crystal defects reduce production yield and also deteriorate electrical parameter characteristics such as the threshold voltage of the high voltage device and the leakage current uniformity during the standby mode of the static random access memory (SRAM). Moreover, such crystal defects increase the time to inspect and analyze a large number of defects during the impurity inspection process, which is a process that must be performed to fabricate a semiconductor device, resulting in an increase in the total processing time for fabricating the semiconductor device.

Embodiments of the present invention are directed to a germanium wafer for preventing crystal defects from being caused by a thermal budget caused by a subsequent high temperature heat treatment process by substantially increasing the gettering sites.

Another embodiment of the present invention is directed to a germanium wafer having a high and uniform bulk microscopic defect (BMD) density in the body region.

Another embodiment of the present invention is directed to a method for fabricating a tantalum wafer that is produced by substantially increasing the gettering sites to prevent crystal defects from being attributed to thermal budgets caused by subsequent high temperature heat treatment processes.

Another embodiment of the present invention is directed to a method for fabricating a tantalum wafer having a high and uniform bulk microscopic defect (BMD) density in a body region.

Another embodiment of the present invention is directed to a semiconductor device fabricated by using the germanium wafer described above.

Another embodiment of the present invention is directed to a method for fabricating a semiconductor device by using the method described above for fabricating a germanium wafer.

According to an aspect of the present invention, a germanium wafer is provided, comprising: a first ablation region formed to have a predetermined depth starting from a top surface of the germanium wafer; and a body region formed on Between the first ablation region and a back surface of the germanium wafer, wherein the first ablation region is formed to have a depth ranging from approximately 20 micrometers to approximately 80 micrometers from the top surface, and wherein oxygen is present in the body region The concentration is evenly distributed throughout the body region within 10% of the change.

According to still another aspect of the present invention, a method for fabricating a germanium wafer is provided, comprising: providing a germanium wafer having a denuded region and a body region; performing the germanium wafer at a first temperature a first annealing process to supplement an oxygen precipitate core and an oxygen precipitate in the body region; and performing a second annealing process on the germanium wafer at a second temperature higher than the first temperature to increase oxygen deposition in the body region Things.

According to still another aspect of the present invention, a method for fabricating a germanium wafer is provided, comprising: providing the germanium wafer; loading the germanium wafer into the interior of the heating device at a loading temperature; performing a twinning a first heating process for heating the temperature from the loading temperature to the first temperature; performing a first annealing process for annealing the germanium wafer to generate oxygen precipitates at the first temperature; performing a silicon wafer from the first Heating a temperature to a second heating process that is higher than a second temperature of the first temperature; performing a second annealing process for annealing the germanium wafer to increase oxygen precipitates for use in the second temperature Density; performing a cooling process for cooling the germanium wafer from the second temperature to an unloading temperature; and unloading the germanium wafer from the heating device to the outside.

The other objects and advantages of the invention will be apparent from the description and appended claims. Further, the objects and advantages of the invention will be apparent to those skilled in the <RTIgt;

The advantages, features, and aspects of the invention will be apparent from the description of the embodiments described herein.

In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer (or film) is referred to as "on another layer or substrate", it can be directly on the other layer or substrate, or an intervening layer can also be present. In addition, it should be understood that when a layer is referred to as "below another layer", it may be directly below the other layer, and one or more intervening layers may also be present. In addition, it should also be understood that when a layer is referred to as "between two layers," it may be a single layer between two layers, or one or more intervening layers may be present.

The present invention achieves a high and uniform BMD density in the body region by using a two-step annealing process for the wafer crucible. As a result, the present invention can prevent crystal defects from being generated due to a thermal budget caused by a subsequent high-temperature heat treatment process by sufficiently increasing a gettering site.

1 is a cross-sectional view of a tantalum wafer in accordance with an embodiment of the present invention.

As shown in FIG. 1, the germanium wafer 100 includes: a first ablation region DZ1 formed to have a predetermined depth starting from a top surface 101 of the germanium wafer; and a body region block The body region BK is formed between the first ablation region DZ1 and a back surface 102. The germanium wafer 100 further includes a second ablated region DZ2 that is formed to have a predetermined depth from the back surface 102 toward the top surface 101.

The first ablation region DZ1 formed to have a predetermined depth from the top surface 101 toward the back surface 102 is a defect-free region (DFZ) which does not have crystal defects such as vacancies and dislocations. Preferably, the first ablation zone DZ1 is formed to have a depth ranging from about 20 micrometers to about 80 micrometers from the direction of the top surface 101 toward the back surface 102.

The second ablation zone DZ2 is also DFZ and formed to have the same depth as the depth of the first ablation zone DZ1 from the back surface 102 toward the top surface 101, or according to the polishing process for the back surface 102, the second ablation zone DZ2 is formed. It has a depth smaller than the depth of the first ablation zone DZ1. That is, when the top surface 101 and the back surface 102 of the wafer 100 are mirror-polished without difference, the first ablation region DZ1 and the second ablation region DZ2 having the same depth are formed at the same depth. In contrast, when the top surface 101 is mirror-polished and the back surface 102 is not mirror-polished, a second ablation region DZ2 having a depth smaller than the depth of the first ablation region DZ1 is formed because the roughness of the back surface 102 is formed next to the back surface 102. Oxygen precipitates.

The body region BK formed between the first ablation region DZ1 and the second ablation region DZ2 includes a bulk microscopic defect (BMD) 103. The BMD 103 remains uniform throughout the body area. BMD 103 includes precipitates and bulk stacks. In addition, the BMD 103 in the body region BK can be controlled to have a sufficient density to draw metal contaminants to be diffused on the surface of the germanium wafer via a subsequent high temperature heat treatment process or thermal process. The BMD 103 in the body region BK preferably maintains a density of from about 1 x 10 ⁵ ea/cm ² to about 1 × 10 ⁷ ea/cm ² , and more preferably from about 1 × 10 ⁶ ea/cm ² to 1 ×. 10 ⁷ ea/cm ² . The concentration of oxygen in the body region BK (hereinafter referred to as "oxygen concentration") is closely related to the oxygen precipitate, and the oxygen concentration is preferably distributed throughout the body region BK within 10% and is maintained from approximately 10.5 to approximately 13 PPMA (atoms Ten thousand points).

2 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a first embodiment of the present invention.

Referring to Figure 2, a germanium wafer 200 is prepared. At this time, the germanium wafer 200 may be a bare wafer. The germanium wafer 200 can be formed in the following steps. First, after the single crystal germanium is grown, the single crystal germanium is cut into a wafer shape. After performing an etching process to etch the surface of the diced wafer or rounding the sides of the diced wafer, the top surface 201 and the back surface 202 of the ruthenium wafer 200 are mirror polished. At this time, a single crystal crucible was grown using a Czochralski (CZ) crystal growth method. In addition, the mirror polishing process for the germanium wafer 200 can be performed after the subsequent thermal process.

The first thermal process of the wafer 200 is performed such that the oxide element 203 between the top surface 201 and the back surface 202 of the germanium wafer 200 diffuses internally. As a result, the first ablation zone DZ1 and the second ablation zone DZ2 and the body region BK are formed. The first thermal process can be an RTP (rapid thermal process) or an annealing process using a furnace apparatus. Preferably, the first thermal process comprises RTP.

To rapidly diffuse the oxide element 203 in the top surface 201 and the back surface 202 of the germanium wafer 200, the first step is performed at a high temperature using argon (Ar) gas, nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas, or a combination thereof. Hot process. When the first thermal process is RTP, the first thermal process is performed for a period of from about 10 seconds to about 30 seconds at a temperature ranging from 1050 ° C to approximately 1150 ° C. When the first thermal process is an annealing process, the first thermal process is performed for a period of from about 100 minutes to about 300 minutes at a temperature ranging from 1050 ° C to about 1150 ° C.

Next, a second thermal process for the germanium wafer 200 is performed such that the oxide elements 203 in the body region BK are bonded. As a result, an oxygen precipitate core 204 is produced. Similar to the first thermal process, the second thermal process can be an RTP or an annealing process using a furnace apparatus. The second thermal process preferably includes RTP.

To facilitate the formation of the oxygen precipitate core 204, a second thermal process is performed at a temperature lower than the temperature of the first thermal process using argon (Ar) gas, nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas, or a combination thereof. When the second thermal process is RTP, the second thermal process is performed for a period of time from about 10 seconds to about 30 seconds at a temperature ranging from about 950 ° C to about 1000 ° C. When the second thermal process is an annealing process, the second thermal process is performed for a period of from about 100 minutes to about 200 minutes at a temperature ranging from about 950 ° C to about 1000 ° C.

Subsequently, a first annealing process is performed on the germanium wafer 200 after the second thermal process is completed. The first annealing process is performed using a furnace device. The oxygen precipitates core 204 in the body region BK is replenished by heating the tantalum wafer 200 at a predetermined temperature lower than the temperature of the second heat process, and at the same time, the oxygen precipitates 205A are generated. Preferably, the first annealing process is performed for a period of from about 100 minutes to about 180 minutes at a temperature ranging from about 750 ° C to about 800 ° C. Further, the first annealing process is performed under an oxygen (O ₂ ) gas atmosphere.

A second annealing process is performed on the germanium wafer 200 after the first annealing process is completed. A second annealing process is also performed using the furnace apparatus. The oxygen precipitate 205A is enlarged by heating the tantalum wafer 200 at a predetermined temperature higher than the temperature of the first annealing process. As a result, an enlarged oxygen precipitate 205B is produced. Preferably, the second annealing process is performed at a temperature ranging from approximately 1000 ° C to approximately 1150 ° C for a period of from about 100 minutes to about 180 minutes. Further, a second annealing process is performed under an oxygen (O ₂ ) gas atmosphere.

Hereinafter, the first annealing process and the second annealing process are described in detail. Hereinafter, the first annealing process and the second annealing process are referred to as a two-step annealing process.

6 is a graph illustrating a two-step annealing process in accordance with an embodiment of the present invention.

Referring to FIG. 6, the annealing process using the furnace apparatus includes performing a first annealing process (II) for annealing the tantalum wafer 200 at a first temperature using oxygen (O ₂ ) gas and performing a second temperature higher than the first temperature. A second annealing process (IV) for annealing the tantalum wafer 200. Each of the first annealing process (II) and the second annealing process (IV) is performed for approximately 100 minutes to approximately 180 minutes. The first temperature of the first annealing process (II) ranges from approximately 750 ° C to approximately 800 ° C, and the second temperature of the second annealing process (IV) ranges from approximately 1000 ° C to approximately 1150 ° C.

To improve the effects of the oxidation process and the heat treatment process, prior to the first annealing process (II), the two-step annealing process according to an embodiment of the present invention may further include loading the germanium wafer 200 into the furnace device and then transferring the germanium wafer 200 is maintained until the loading temperature (L) for a predetermined duration. Moreover, after the second annealing process (IV), the two-step annealing process according to an embodiment of the present invention may further include maintaining the germanium wafer 200 to the unloading temperature for a predetermined time before unloading the germanium wafer 200 to the outside of the furnace device. The duration of the uninstall process (UL).

The loading temperature of the loading process (L) is lower than the first temperature. Preferably, the loading temperature ranges from approximately 600 ° C to approximately 700 ° C. No oxygen is supplied to the furnace unit during the loading process (L). As a result, the wafer 200 is not oxidized during the loading process (L). The unloading temperature of the unloading process (UL) is substantially equal to the first temperature. Preferably, the unloading temperature ranges from approximately 750 ° C to approximately 800 ° C. During the unloading process (UL), no oxygen is supplied and only nitrogen is supplied. The flow rate of nitrogen ranges from approximately 9 slm to approximately 11 slm.

Further, the two-step annealing process according to an embodiment of the present invention may further include a first heating process for heating the loading temperature to the first temperature between the loading process (L) and the first annealing process (II) (I And a second heating process (III) for heating the first temperature to the second temperature between the first annealing process (II) and the second annealing process (IV). When the rate of temperature increase per minute during the first heating process (I) and the second heating process (III) is too high, the wafer structure may be deformed. Therefore, the rate of temperature rise in the first heating process (I) and the second heating process (III) can be set to a range of approximately 5 ° C / min to approximately 8 ° C / min.

Further, the two-step annealing process according to an embodiment of the present invention may further include a cooling process (V) for cooling the second temperature to the unloading temperature between the second annealing process (IV) and the unloading process (UL). The cooling rate of the cooling process (V) can range from approximately 2 ° C/min to approximately 4 ° C/min.

In the two-step annealing process according to an embodiment of the present invention, the annealing of the germanium wafer 200 is substantially achieved primarily during the first annealing process and the second annealing process (II, IV) because oxygen is supplied only during such processes. . The flow rate of oxygen supplied during the first annealing process and the second annealing process (II, IV) may range from approximately 50 sccm to approximately 120 sccm. Each of the first annealing process and the second annealing process (II, IV) may be performed for approximately 100 minutes to approximately 180 minutes.

The two-step annealing process as described in FIG. 6 can be applied to the first annealing process and the second annealing process of the method for fabricating a germanium wafer according to the following embodiments of the present invention shown in FIGS. 3 through 5.

3 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a second embodiment of the present invention.

Referring to FIG. 3, a thermal process for the germanium wafer 300 is performed such that the oxide element 303 between the top surface 301 and the back surface 302 of the germanium wafer 300 is diffused internally. As a result, the first ablation zone DZ1 and the second ablation zone DZ2 and the body region BK are formed. The thermal process can be RTP or an annealing process using a furnace unit. Preferably, the first thermal process comprises RTP.

In order to rapidly diffuse the oxide element 303 of the top surface 301 and the back surface 302 of the tantalum wafer 300, a thermal process is performed at a high temperature. When the thermal process is RTP, the thermal process is performed for a period of approximately 10 seconds to approximately 30 seconds at a temperature ranging from 1050 ° C to approximately 1150 ° C. When the thermal process is an annealing process, the thermal process is performed at a temperature ranging from 1050 ° C to approximately 1150 ° C for approximately 100 minutes to approximately 200 minutes.

Subsequently, a first annealing process is performed on the germanium wafer 300 such that the oxide elements 203 in the body region BK are bonded. As a result, an oxygen precipitate core 304 is formed. The first annealing process is performed using a furnace apparatus at a predetermined temperature lower than the temperature of the hot process. Preferably, the first annealing process is performed for a period of from about 100 minutes to about 180 minutes at a temperature ranging from about 750 ° C to about 800 ° C. Further, the first annealing process is performed under an oxygen (O ₂ ) gas atmosphere.

A second annealing process is performed on the germanium wafer 300. A second annealing process is also performed using the furnace apparatus. The oxygen precipitates 305 are produced by heating the tantalum wafer 300 at a predetermined temperature higher than the temperature of the first annealing process. Preferably, the second annealing process is performed at a temperature ranging from approximately 1000 ° C to approximately 1150 ° C for a period of from about 100 minutes to about 180 minutes. Further, a second annealing process is performed under an oxygen (O ₂ ) gas atmosphere.

4 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a third embodiment of the present invention.

In FIG. 4, the thermal process prior to the first annealing process is performed at a temperature lower than the temperature of the thermal process of FIG.

Referring to FIG. 4, a thermal process for the germanium wafer 400 is performed at a temperature lower than the temperature of the thermal process of FIG. Thus, an oxygen precipitate core 404 is produced. Since the thermal process is performed at a low temperature, the oxygen precipitate core 404 is formed in the first ablation zone DZ1 and the second ablation zone DZ2 and the body region BK. The thermal process can be an RTP or an annealing process. Preferably, the first thermal process comprises RTP. When the thermal process is RTP, the thermal process is performed for a period of approximately 10 seconds to approximately 30 seconds at a temperature ranging from approximately 950 ° C to approximately 1000 ° C. When the thermal process is an annealing process, the thermal process is performed at a temperature ranging from approximately 950 ° C to approximately 1000 ° C for approximately 100 minutes to approximately 200 minutes.

Subsequently, the first annealing process and the second annealing process are sequentially performed on the germanium wafer 400 such that the oxygen precipitate core 404 and the oxygen precipitate 405A are generated. The first annealing process and the second annealing process are performed under the same conditions as those of the first annealing process and the second annealing process of FIG.

Figure 5 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a fourth embodiment of the present invention.

Referring to FIG. 5, unlike the annealing process shown in FIGS. 2 through 4, the annealing process according to the fourth embodiment of the present invention does not require an additional annealing process and an additional thermal process prior to the second annealing process. That is, the germanium wafer 500 is provided as a bare wafer, and the first annealing process and the second annealing process are sequentially performed on the germanium wafer 500, so that the first ablation zone DZ1 and the second ablation zone DZ2 and the body region BK are formed. . The first annealing process and the second annealing process are performed under the same conditions as those of the first annealing process and the second annealing process shown in FIGS. 2 to 4.

In Fig. 5, reference numeral "501" indicates the top surface, "502" indicates the back surface, "503" indicates the oxide element, "504" indicates the oxygen precipitate core, "505A" indicates the oxygen precipitate, and "505B" indicates the Increased oxygen precipitates.

As described above, a method for fabricating a germanium wafer in accordance with the present invention is described with reference to FIGS. 2 through 5. As described previously, in the first to third embodiments shown in FIGS. 2 to 4, the RTP prefers to use a thermal process before the first annealing process and the second annealing process.

The internal defects of the oxygen precipitates or void defects in the germanium wafer can be controlled during the growth of the single crystal germanium or by the thermal process after the growth of the single crystal germanium. As described above, the thermal process can include an RTP using a halogen lamp and an annealing process using a furnace device.

The annealing process using the furnace apparatus is performed for more than about 100 minutes at an elevated temperature of approximately 1000 ° C under an argon (Ar) gas or hydrogen (H ₂ ) atmosphere. The diffusion of the oxide elements in the germanium wafer and the rearrangement of the germanium caused by the annealing process form an ideal region of the device (i.e., a defect free region (DFZ)) in a portion of the top surface of the germanium wafer. However, as the size of the germanium wafer increases, it is difficult to control the contamination or sliding dislocations of the germanium wafer due to the high temperature heat treatment.

Therefore, RTP achieves the characteristics of germanium wafers superior to the annealing process. However, when various defect detection methods are used to evaluate tantalum wafers fabricated by RTP, only oxygen precipitates are controlled to be within a depth of from about 3 microns to about 10 microns from the top surface. Furthermore, when a germanium wafer is fabricated by performing RTP only once or twice, there is a limit to achieving high BMD density in the body region. More specifically, when a germanium wafer is manufactured by performing RTP once, the BMD density is determined to be in the range of from 1 × 10 ⁶ ea/cm ² to 3 × 10 ⁶ ea/cm ² , and it is difficult to make the BMD density. Beyond this range.

In an embodiment of the present invention, as shown in FIGS. 2 through 4, a two-step annealing process is performed after the thermal process, thereby removing void defects and oxygen precipitates near the top surface of the germanium wafer. As a result, the present invention can ensure a defect-free zone (DFZ) and increase the BMD density (including bulk stack defects and oxygen precipitates in the body region), thereby improving the suction effect by increasing the suction sites in the body region.

Hereinafter, the characteristics of the germanium wafer manufactured by the embodiment of the present invention will be described in detail with reference to Tables 1 and 2.

In Table 1, "high temperature RTP" and "low temperature RTP" are performed under rapid thermal processing using argon (Ar) gas, nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas or a combination thereof for approximately 10 seconds to approximately 30 seconds. . The "low temperature annealing process" and the "high temperature annealing process" are performed using oxygen (O ₂ ) gas for approximately 100 minutes to approximately 180 minutes.

In Tables 1 and 2, "Condition 1" indicates the first embodiment shown in Figure 2, "Condition 2" indicates the second embodiment shown in Figure 3, and "Condition 3" indicates the third shown in Figure 4. The embodiment and "Condition 4" represent the fourth embodiment shown in FIG. Table 2 shows the BMD density and the ablation zone (DZ) depth according to the oxygen concentration (Oi) in each condition.

7 to 12 are graphs showing the parameters of Tables 1 and 2. In detail, Figure 7 is a graph illustrating the BMD density for each condition. Figure 8 is a graph illustrating the DZ depth for each condition. 9 to 12 are graphs illustrating the oxygen concentration in the body region for each condition.

Referring to Table 2 and Figure 7, a BMD density greater than 1 x 10 ⁵ ea/cm ² was obtained under all conditions. Specifically, a BMD density (regardless of oxygen concentration) of more than 1 × 10 ⁶ ea/cm ² was obtained under Condition 1. Although no data is presented regarding the BMD density of tantalum wafers fabricated by performing RTP only once or twice, it is predicted that the BMD density will be significantly lower than the BMD density under the above conditions.

Metal contaminants are controlled by pipetting BMD as previously described. However, since the BMD density tends to decrease during the high temperature process, it is necessary to ensure a high BMD density during the fabrication of the germanium wafer. In general, semiconductor devices require high voltage devices that operate in a high voltage environment. In order to manufacture such a high voltage device, it is necessary to perform a heavy ion implantation process and a high temperature annealing process because a junction region having a deep distribution (i.e., a doped region) is required. When the BMD density decreases during the high temperature annealing process, not only due to defect evaluation but also due to low suction capability, annular dislocations occur after subsequent shallow trench isolation (STI).

As a result of measuring the BMD density, a circular dislocation occurs partially when the BMD density is approximately 2.5 × 10 ⁵ ea/cm ² , but no annular dislocation occurs when the BMD density is approximately 4.4 × 10 ⁵ ea/cm ² . . Therefore, it is necessary to control the BMD density to be greater than at least 1 x 10 ⁵ ea/cm ² . In this embodiment, a two-step annealing process is additionally performed for the initial process of fabricating a semiconductor device, regardless of the conventional thermal process during the fabrication of the germanium wafer. The initial process includes an oxidation process performed prior to ion implantation for forming a well. The oxidation process corresponds to a process for forming a masking oxide layer during ion implantation for forming a well (hereinafter, referred to as well ion implantation).

Referring to Table 2 and Figure 8, the DZ depth is shown for each condition. DZ depth is closely related to BMD density and oxygen concentration. As the BMD density and oxygen concentration increase, the DZ depth becomes smaller. When the oxygen concentration is the same under each condition (for example, 11.6 in Table 2), the BMD density under conditions 1 and 2 is higher than the BMD density under conditions 3 and 4, but the DZ under conditions 1 and 2. The depth is lower than the DZ depth under Condition 3 and Condition 4. Therefore, the DZ depth can be measured by the BMD density.

Referring to Table 2 and Figures 9 through 12, the BMD density and DZ depth according to oxygen concentration under each condition are shown. As the oxygen concentration (Oi) increases, the BMD density increases but the DZ depth becomes smaller. Therefore, the oxygen concentration (Oi) is also a measure of the BMD density. That is, the BMD density in the body region can be calculated by measuring the DZ depth and the oxygen concentration (Oi).

13 and 14 are cross-sectional views of a germanium wafer.

In detail, FIG. 13 shows a cross-sectional view of a germanium wafer fabricated by performing only RTP but without a two-step annealing process, and FIG. 14 shows fabrication by performing a two-step annealing process in accordance with an embodiment of the present invention. A cross-sectional view of the wafer.

As shown, a plurality of erroneous dislocations occur in the wafer of FIG. 13, but there are no erroneous dislocations in the wafer of FIG. Further, when an epitaxial layer is formed by using epitaxial growth, crystal defects in the body region of the germanium wafer in which the epitaxial layer is formed are remarkably reduced.

15 and 16 illustrate crystal defect diagrams of a body region (in which an epitaxial layer is formed) in a germanium wafer. This test was performed using an inspection device manufactured by KLA Corporation.

As shown in Figure 15, a large number of crystal defects are distributed in the figure when performing an oxidation process without a two-step annealing process. Herein, the oxidation process forms a masking oxide layer during well ion implantation. In contrast, as shown in FIG. 16, crystal defects are significantly reduced when performing an oxidation process having the two-step annealing process of the present invention.

Hereinafter, a method for fabricating a semiconductor device having a well for a high voltage device will be described in detail with reference to FIGS. 17A through 17D, which includes a two-step annealing process according to an embodiment of the present invention.

17A through 17D are diagrams illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.

Referring to Figure 17A, a mask oxide layer 601 is formed over the germanium wafer 600 using the two-step annealing process illustrated in FIG. The germanium wafer 600 may be a wafer to which RTP is applied once or twice as described in FIGS. 2 to 4, or a bare wafer to which RTP is not applied as described in FIG. 5. The masking oxide layer 601 may be a hafnium oxide layer and formed to a range of approximately 100 To roughly 140 The thickness.

Referring to Figure 17B, well 602 is formed in tantalum wafer 600 to a predetermined depth. Well 602 may have a p-type or n-type conductivity type depending on the conductivity type of the high voltage device.

Well 602 is formed via an ion implantation process and a diffusion process. It is difficult to form a well for a high voltage device using only an ion implantation process. Therefore, the diffusion process and the ion implantation process should be additionally performed after the ion implantation process is completed to form the well 602 having the doping profile of FIG. 17B. The diffusion process is performed for a long time via an annealing process using a high temperature heating device such as a furnace. Preferably, the diffusion process is performed using a nitrogen (N ₂ ) gas at a temperature ranging from approximately 1100 ° C to approximately 1250 ° C for a period of from about 6 hours to about 10 hours.

Referring to FIG. 17C, a pad nitride layer (not shown) serving as a hard mask is formed on the mask oxide layer 601, or a pad nitride layer is formed on a buffer layer (not shown). It is formed by performing an additional oxidation process after removing the mask oxide layer 601. The reason for removing the masking oxide layer 601 is that the masking oxide layer 601 is not suitable for the buffer layer because the masking oxide layer 601 is damaged during the ion implantation process. A photoresist pattern 604 for forming an STI trench is then formed over the pad nitride layer.

The pad nitride layer can be formed via a low pressure chemical vapor deposition (LPCVD) process to prevent damage to the germanium wafer 600 during the deposition process by minimizing stress applied to the germanium wafer 600. The pad nitride layer may be formed of tantalum nitride. A pad nitride layer can be formed to a range of approximately 1400 To roughly 2000 The thickness.

The pad nitride layer, the mask oxide layer 601, and the germanium wafer 600 are partially etched in order using the photoresist pattern 604 as an etch mask, thereby forming the pad nitride pattern 603, the mask oxide pattern 601A, and the twin crystal Round 600A and well 602A. As a result, a trench 605 having a predetermined depth and inclination is formed in the germanium wafer 600A.

Referring to FIG. 17D, a device isolation structure 606 filling the trench 605 is formed, and then the pad nitride pattern 603 and the mask oxide pattern 601A are removed. Device isolation structure 606 may be formed from a high density plasma (HDP) layer having excellent gap fill properties.

While comparing the method of the present invention with the comparative examples, the advantageous effects of the above embodiments of the present invention will be described below. The method of the present invention includes forming a masking oxide layer via an oxidation process using a two-step annealing process, and a comparative example includes forming a masking oxide layer via an oxidation process using a one-step annealing process. In the oxidation process of this comparative example, a tantalum wafer was oxidized using a wet oxidation process at a single temperature ranging from 800 °C to 850 °C.

18 to 21 illustrate defects in a germanium wafer prepared by the oxidation process of the comparative example.

In particular, FIG. 18 illustrates a graph of crystal defects examined by an inspection apparatus manufactured by KLA Corporation after forming a trench through a STI process in a germanium wafer prepared by a comparative example oxidation process. As shown in Figure 18, the presence of crystal defects such as annular germanium dislocations in most defective wafers can be observed.

19 and 20 are scanning electron microscope microscopic (SEM) images of a germanium wafer obtained by an inspection apparatus manufactured by KLA Corporation.

Specifically, FIG. 19 is an SEM image showing a cross section of a germanium wafer, and FIG. 20 is a planar tilted STM image. As shown in Figures 19 and 20, the presence of crystal defects and dislocations was observed.

Figure 21 is a photomicrograph showing the bulk microscopic defect (BMD) density analysis of a germanium wafer with a ring defect.

As shown in Figure 21, it can be observed that most of the BMD is formed immediately adjacent to the top surface of the wafer, but a small number of BMDs are formed in the central portion of the germanium wafer, i.e., formed in the body region. That is, the BMD density of the body region is significantly lower than the BMD density of the top surface of the germanium wafer.

22 to 24 are test results of crystal defects in a germanium wafer prepared by an oxidation process using a two-step annealing process according to an embodiment of the present invention. This test was performed using an inspection device manufactured by KLA Corporation.

In detail, FIG. 22 illustrates the inspection results of the crystal defects of the germanium wafer after the trench is formed by the STI process in the germanium wafer prepared by the oxidation process using the two-step annealing process of the present invention. As shown in Figure 22, it was observed that the crystal defects were removed and only some particles or dust were detected.

Figure 23 is a plan view of a tilted STM of a germanium wafer obtained by an inspection apparatus manufactured by KLA Corporation. Similar to the results of Figure 22, it was observed that only some of the particles were detected.

Figure 24 is a photomicrograph showing the BMD density analysis of a tantalum wafer prepared by an oxidation process using the two-step annealing process of the present invention. As shown in Figure 24, it is observed that the BMD is uniformly formed throughout the germanium wafer.

Figure 25 is a graph illustrating the comparison of leakage currents during a standby mode of a static random access memory (SRAM). In Fig. 25, a left side view shows a sample of a high voltage device prepared by an oxidation process using the two-step annealing process of the present invention, and a right side view shows a sample of a high voltage device of a comparative example. As shown in Figure 25, it was observed that the samples prepared by the oxidation process of the present invention exhibited uniform leakage current characteristics as compared to the samples prepared by the oxidation process of the comparative example.

Fig. 26 is a graph showing the comparison result of the production yield. In Fig. 26, a left side view shows a sample of a high voltage device prepared by an oxidation process using the two-step annealing process of the present invention, and a right side view shows a sample of a high voltage device of a comparative example. As shown in Fig. 26, the production yield of the sample prepared by the oxidation process of the present invention was as high as about 5% to 9% as compared with the sample of the comparative example.

According to the present invention, first, a suction site can be sufficiently produced in a germanium wafer by performing a two-step annealing process at different temperatures. This makes it possible to prevent crystal defects from being attributed to the thermal budget caused by the subsequent high temperature heat treatment process.

Second, the present invention can provide a germanium wafer having a high and uniform BMD density in the body region by performing a two-step annealing process at different temperatures.

Third, according to the present invention, after performing a two-step annealing process on the germanium wafer at different temperatures, an epitaxial layer is formed on the germanium wafer using epitaxial growth. As a result, the present invention can provide a semiconductor device in which an epitaxial layer having excellent characteristics is formed.

Fourth, according to the present invention, after the shadow oxide layer is formed on the germanium wafer by performing a two-step annealing process on the germanium wafer at different temperatures, ion implantation is performed by using the mask oxide layer as an ion mask. The process is entered to form a well in the germanium wafer. As a result, the present invention can sufficiently generate the gettering sites in the germanium wafer to thereby prevent crystal defects from being generated due to the thermal budget caused by the subsequent high temperature heat treatment process.

While the invention has been described with respect to the specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the following claims.

100. . . Silicon wafer

101. . . Top surface

102. . . back

103. . . Ontology micro defect (BMD)

200. . . Silicon wafer

201. . . Top surface

202. . . back

203. . . Oxide element

204. . . Oxygen precipitate core

205A. . . Oxygen precipitate

205B. . . Increased oxygen precipitate

300. . . Silicon wafer

301. . . Top surface

302. . . back

303. . . Oxide element

304. . . Oxygen precipitate core

305. . . Oxygen precipitate

400. . . Silicon wafer

401. . . Top surface

402. . . back

403. . . Oxide element

404. . . Oxygen precipitate core

405A. . . Oxygen precipitate

405B. . . Increased oxygen precipitate

500. . . Silicon wafer

501. . . Top surface

502. . . back

503. . . Oxide element

504. . . Oxygen precipitate core

505A. . . Oxygen precipitate

505B. . . Increased oxygen precipitate

600. . . Silicon wafer

600A. . . Silicon wafer

601. . . Masking oxide layer

601A. . . Masking oxide pattern

602. . . well

602A. . . well

603. . . Pad nitride pattern

604. . . Resistive pattern

605. . . trench

606. . . Device isolation structure

BK. . . Body area

DZ1. . . First ablation zone

DZ2. . . Second ablation zone

1 is a cross-sectional view of a germanium wafer in accordance with an embodiment of the present invention;

2 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a first embodiment of the present invention;

3 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a second embodiment of the present invention;

4 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a third embodiment of the present invention;

5 is a cross-sectional view illustrating a method for fabricating a tantalum wafer in accordance with a fourth embodiment of the present invention;

6 is a graph illustrating a two-step annealing process in accordance with an embodiment of the present invention;

Figure 7 is a graph illustrating BMD density under various conditions;

Figure 8 is a graph illustrating the depth of the ablation zone under various conditions;

9 to 12 are graphs illustrating the BMD density and the depth of the ablation zone according to the oxygen concentration under various conditions;

Figure 13 is a cross-sectional view of a germanium wafer fabricated in accordance with a comparative example;

Figure 14 is a cross-sectional view of a germanium wafer fabricated in accordance with an embodiment of the present invention;

Figure 15 illustrates a crystal defect map of a body region in a germanium wafer fabricated according to a comparative example;

16 illustrates a crystal defect diagram of a body region in a germanium wafer fabricated using a two-step annealing process in accordance with an embodiment of the present invention;

17A-17D are diagrams illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention;

Figure 18 illustrates test results of crystal defects in a germanium wafer prepared according to a comparative example;

Figure 19 is a scanning electron microscope (SEM) image of a germanium wafer prepared by an oxidation process of a comparative example;

20 is a plan view of a germanium wafer prepared by an oxidation process of a comparative example;

21 is a microscopic image showing BMD density analysis of a germanium wafer prepared by an oxidation process of a comparative example;

22 illustrates test results of crystal defects of a germanium wafer in accordance with an embodiment of the present invention;

23 is a plan view of a germanium wafer in accordance with an embodiment of the present invention;

24 is a photomicrograph showing BMD density analysis of a germanium wafer in accordance with an embodiment of the present invention;

25 is a graph illustrating a comparison result of leakage currents during a standby mode of a static random access memory (SRAM); and

Fig. 26 is a graph showing the comparison result of the production yield.

100. . . Silicon wafer

101. . . Top surface

102. . . back

103. . . Ontology micro defect (BMD)

BK. . . Body area

DZ1. . . First ablation zone

DZ2. . . Second ablation zone

Claims (36)

A germanium wafer comprising: a first ablation region formed to have a predetermined depth starting from a top surface of the germanium wafer; and a body region formed in the first ablation region and the twin Between one of the back sides of the circle, wherein the first ablation zone is formed to have a depth ranging from approximately 20 microns to approximately 80 microns from the top surface, and wherein a concentration of oxygen in the body region is throughout the body region One of the changes within 10% is evenly distributed. The wafer of claim 1 wherein the density of one of the bulk microscopic defects (BMD) in the body region ranges from approximately 1 x 10 ⁵ ea/cm ² to approximately 1 x 10 ⁷ ea/cm ² . As claimed in claim 1, the concentration of one of the oxygen in the body region ranges from approximately 10.5 PPMA to approximately 13 PPMA (atomic parts per million). The wafer of claim 1, further comprising an epitaxial layer formed on the top surface of the germanium wafer by epitaxial growth. The wafer of claim 1, further comprising a second ablation zone formed under the body region and having a predetermined depth from the back surface toward the top surface. The wafer of claim 5, wherein the second ablation zone is formed to have a depth ranging from about 20 microns to about 80 microns starting from the back side. A semiconductor processing method comprising: heat treating a wafer to form an ablation region and a book in the germanium wafer a body region; the heat-treated tantalum wafer is loaded on a heating device at a loading temperature; and a first annealing process is performed on the silicon wafer at a first temperature to replenish oxygen precipitates in the body region a core and an oxygen precipitate; and performing a second annealing process on the silicon wafer at a second temperature higher than the first temperature to increase the oxygen precipitates in the body region, wherein the germanium wafer This heat treatment occurs prior to the loading of the heat treated tantalum wafer. The method of claim 7, wherein the first annealing process is performed at a temperature ranging from approximately 750 ° C to approximately 800 ° C. The method of claim 7, wherein the second annealing process is performed at a temperature ranging from approximately 1000 ° C to approximately 1150 ° C. The method of claim 7, wherein the heat-treated tantalum wafer comprises: performing a first thermal process on the tantalum wafer at a third temperature equal to or lower than the second temperature to form the ablated region and a body region; and performing a second thermal process on the silicon wafer at a temperature above the first temperature and below the third temperature to form the oxygen precipitate cores in the body region. The method of claim 10, wherein the first thermal process and the second thermal process are performed by a rapid thermal process (RTP) or an annealing process. The method of claim 10, wherein the first thermal process is performed at a temperature ranging from approximately 1050 ° C to approximately 1150 ° C, and the second thermal process is at a temperature ranging from approximately 950 ° C to approximately 1000 ° C. Execute. The method of claim 10, wherein the first thermal process and the second thermal process use argon (Ar) gas, nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas, or a combination thereof. The method of claim 7, wherein the heat-treated tantalum wafer comprises: performing a thermal process on the tantalum wafer at a third temperature equal to or lower than the second temperature to form the ablated region and the body region . The method of claim 14, wherein the thermal process is performed at a temperature ranging from approximately 1050 ° C to approximately 1150 ° C. The method of claim 7, wherein the heat-treated tantalum wafer comprises: performing a thermal process on the tantalum wafer at a third temperature higher than the first temperature and lower than the second temperature to form the ablation Zone and the body area. The method of claim 16, wherein the thermal process is performed at a temperature ranging from approximately 950 ° C to approximately 1000 ° C. The method of claim 7, wherein the first annealing process and the second annealing process are performed under an oxygen (O ₂ ) gas atmosphere. The method of claim 7, wherein each of the first annealing process and the second annealing process is performed for a period of from about 100 minutes to about 180 minutes. The method of claim 7, wherein the ablated region is formed to have a depth ranging from substantially 20 microns to substantially 80 microns from a top surface of the one of the germanium wafers. The method of claim 7, wherein after performing the second annealing process, a density of one of the bulk microscopic defects (BMD) including the one of the oxygen precipitates in the body region is controlled to approximately 1×10 ⁵ ea/cm ² It is approximately 1×10 ⁷ ea/cm ² . The method of claim 7, wherein after performing the second annealing process, a concentration of oxygen in the body region is controlled to be uniformly distributed throughout the body region by one of 10%. The method of claim 7, wherein after performing the second annealing process, a concentration of oxygen in the body region is controlled to a range of approximately 10.5 to approximately 13 PPMA. The method of claim 7, further comprising: removing one of the oxide layers formed on one of the top surfaces of the germanium wafer during the second annealing process; and forming an epitaxial layer via epitaxial growth, An epitaxial layer is formed on the top surface of the germanium wafer. The method of claim 7, further comprising: forming a well in the germanium wafer by using an oxide layer as a buffer layer, wherein the oxide layer is formed in the twin crystal during the second annealing process On one of the tops of the circle. The method of claim 7, wherein the heat-treated tantalum wafer comprises: growing a single crystal germanium; cutting the grown single crystal germanium into a wafer shape; and performing an etching process to etch the cut wafer The surface of the wafer or the sides of the diced wafer are rounded. A semiconductor processing method includes: heat treating a wafer to form an ablation region and a body region in the germanium wafer; and loading the heat treated tantalum wafer on a heating temperature at a loading temperature In the apparatus, performing the first heating on the loaded wafer to heat from the loading temperature to a first temperature; and performing the first heating on the first wafer at the first temperature Sub-annealing to generate oxygen precipitates in the germanium wafer that has been heated for the first time; directly heating the germanium wafer that has been subjected to the first annealing for a second heating to heat from the first temperature to one a second temperature, wherein the second temperature is greater than the first temperature; and the second wafer having been subjected to the second heating is subjected to a second annealing at the second temperature to expand and increase the second heating a density of one of the oxygen precipitates in the germanium wafer; cooling the germanium wafer that has been a second annealed to cool from the second temperature to an unloading temperature; and cooling the crucible that has been cooled The wafer is unloaded from the heating device at the unloading temperature, wherein the heat treatment of the germanium wafer occurs prior to the loading of the heat treated tantalum wafer. The method of claim 27, wherein the loading temperature ranges from approximately 600 ° C to approximately 700 ° C. The method of claim 27, wherein the rate of temperature rise of the first heating of the germanium wafer that has been loaded ranges from approximately 5 ° C/minute to approximately 8 ° C/minute. The method of claim 27, wherein the first temperature range is approximately 750 ° C to approximately 800 ° C. The method of claim 27, wherein the second heating rate of the second heating of the tantalum wafer that has been subjected to the first annealing ranges from approximately 5 ° C/min to approximately 8 ° C/min. The method of claim 27, wherein the second temperature ranges from approximately 1000 ° C to approximately 1150 ° C. The method of claim 27, wherein the cooling rate of the cooling of the tantalum wafer that has been subjected to the second annealing ranges from approximately 2 ° C/min to approximately 4 ° C/min. The method of claim 27, wherein the unloading temperature ranges from approximately 750 ° C to approximately 800 ° C. The method of claim 27, wherein the unloading the germanium wafer is performed using nitrogen (N ₂ ) gas. The method of claim 27, wherein the first annealing and the second annealing are performed using oxygen (O ₂ ) gas.