CN101713098B - Silicon wafer and fabrication method thereof - Google Patents

Silicon wafer and fabrication method thereof Download PDF

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CN101713098B
CN101713098B CN2009101745256A CN200910174525A CN101713098B CN 101713098 B CN101713098 B CN 101713098B CN 2009101745256 A CN2009101745256 A CN 2009101745256A CN 200910174525 A CN200910174525 A CN 200910174525A CN 101713098 B CN101713098 B CN 101713098B
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silicon wafer
temperature
annealing
annealing process
body regions
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CN101713098A (en
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朴正求
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Aisi Kaifang Semiconductor Co ltd
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Abstract

Provided is a silicon wafer including: a first denuded zone DZ1 formed with a predetermined depth from a top surface 101 of the silicon wafer 100; and a bulk area BK formed between the first denuded zone DZ1 and a backside 102 of the silicon wafer 100, wherein the first denuded zone DZ1 is formed with a depth ranging from approximately 20 [mu]m to approximately 80 [mu]m from the top surface 101, and wherein a concentration of oxygen in the bulk area BK is uniformly distributed within a variation of 10 % over the bulk area BK. The invention also provides a fabrication method thereof.

Description

Silicon wafer and manufacture method thereof
Related application
The present invention requires the right of priority of the korean patent application submitted to Korea S Department of Intellectual Property on September 29th, 2008 and on January 16th, 2009 10-2008-0095462 number and 10-2009-0003697 number, incorporates it into this paper by reference.
Technical field
The present invention relates to semiconductor fabrication, more specifically relate to silicon wafer and manufacture method thereof.
Background technology
In such as nmos pass transistor and the transistorized most of high voltage devices of PMOS, trap forms from about 5 microns to the 10 microns degree of depth of substrate surface usually.Only use ion implantation technology to be difficult to realize that the degree of depth is the dopant profiles of 5 microns to 10 microns trap.For this reason, after ion implantation technology, should use high-temperature heat treatment to implement dopant diffusion processes.
Yet, because high-temperature heat treatment can not realize oxygen precipitate fully in silicon body (bulk).This causes being used for shallow trench isolation and lattice defect such as the ring-type dislocation occurs at silicon substrate behind the etch process of (STI).
In addition, these lattice defects make good article rate reduce, and and the electrical parameter characteristic of the leakage current homogeneity during the ready mode of the threshold voltage of deterioration such as high voltage device and static RAM (SRAM).In addition, during making the essential foreign impurity matters test process of implementing of semiconducter device institute, these lattice defects increase the time that is used for checking and analyzing a large amount of defectives, thereby cause making the increase of the overall process time of semiconducter device.
Summary of the invention
One embodiment of the invention relate to a kind of silicon wafer, and it prevents because the generation of the lattice defect that the heat budget that follow-up high-temperature heat treatment process causes causes by increasing the gettering site fully.
Another embodiment of the invention relates to a kind of silicon wafer, and it has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of method of making silicon wafer, and it prevents because the generation of the lattice defect that the heat budget that follow-up high-temperature heat treatment process causes causes by increasing the gettering site fully.
Another embodiment of the invention relates to a kind of method of making silicon wafer, and described silicon wafer has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of by using the semiconducter device of above-mentioned silicon wafer manufacturing.
Another embodiment of the invention relates to a kind of by using above-mentioned method for the manufacture of silicon wafer to make the method for semiconducter device.
According to an aspect of the present invention, provide a kind of silicon wafer, it comprises: first denuded zone (denuded zone), and it forms the predetermined depth that has from the silicon wafer end face; And body regions, it is formed between the back side of first denuded zone and silicon wafer, wherein first denuded zone form have from end face about 20 microns to about 80 microns degree of depth, and wherein in the body regions variation in 10% in whole body regions of the concentration of oxygen evenly distribute.
According to a further aspect in the invention, provide a kind of method of making silicon wafer, it comprises: the silicon wafer with denuded zone and body regions is provided; Under first temperature, this silicon wafer is implemented first annealing process, produce oxygen precipitate nuclear and oxygen precipitate in body regions, to replenish; And silicon wafer is implemented second annealing process being higher than under second temperature of first temperature, to increase the oxygen precipitate in the body regions.
According to another aspect of the invention, provide a kind of method of making silicon wafer, it comprises: silicon wafer is provided; Under loading temperature, silicon wafer is loaded into heating unit inside; Enforcement is loaded first heating process that temperature is heated to first temperature certainly with silicon wafer; Under first temperature, implement to make first annealing process of this silicon wafer annealing to produce oxygen precipitate; Enforcement is heated above silicon wafer second heating process of second temperature of first temperature from first temperature; Second annealing process of implementing to make silicon wafer annealing under second temperature is to increase oxygen precipitate with for increasing its density; Enforcement is cooled to silicon wafer the process for cooling of unloading temperature from second temperature; And the silicon wafer self-heating apparatus is offloaded to the outside.
Other purpose of the present invention and advantage can be understood by following description, and become apparent with reference to embodiment of the present invention.And it will be apparent to one skilled in the art that: objects and advantages of the present invention can realize by means and the combination thereof of claim.
Description of drawings
Fig. 1 is the cross-sectional view according to the silicon wafer of one embodiment of the invention;
Fig. 2 makes the cross-sectional view of the method for silicon wafer according to first embodiment of the invention for explanation;
Fig. 3 makes the cross-sectional view of the method for silicon wafer according to second embodiment of the invention for explanation;
Fig. 4 makes the cross-sectional view of the method for silicon wafer according to third embodiment of the invention for explanation;
Fig. 5 makes the cross-sectional view of the method for silicon wafer according to four embodiment of the invention for explanation;
Fig. 6 is the figure of explanation two step annealing process according to an embodiment of the invention;
Fig. 7 illustrates the figure of bmd density under various conditions;
Fig. 8 illustrates the figure of the degree of depth of denuded zone under various conditions;
Fig. 9 to Figure 12 for explanation under various conditions according to the figure of the degree of depth of the bmd density of oxygen concn and denuded zone;
Figure 13 is the cross-sectional view according to the silicon wafer of Comparative Examples manufacturing;
Figure 14 is the cross-sectional view according to the silicon wafer of one embodiment of the invention manufacturing;
Figure 15 explanation is according to the lattice defect figure of body regions in the silicon wafer of Comparative Examples manufacturing;
Figure 16 illustrates the lattice defect figure of body regions in the silicon wafer that use two step annealing processs according to an embodiment of the invention make;
Figure 17 A to Figure 17 D makes the method for semiconducter device according to an embodiment of the invention for explanation;
Figure 18 explanation is according to the assay of the lattice defect in the silicon wafer of Comparative Examples preparation;
Figure 19 is scanning electronic microscope (SEM) photo by the silicon wafer of the oxidizing process preparation of Comparative Examples;
Figure 20 is the plane picture by the silicon wafer of the oxidizing process preparation of Comparative Examples;
Figure 21 carries out the micro image that bmd density is analyzed for showing the silicon wafer that the oxidizing process by Comparative Examples is prepared;
The assay of the lattice defect of Figure 22 explanation silicon wafer according to an embodiment of the invention;
Figure 23 is the plane picture of silicon wafer according to an embodiment of the invention;
Figure 24 is for showing the Photomicrograph that silicon wafer is according to an embodiment of the invention carried out the bmd density analysis;
Figure 25 is the comparative result figure of explanation leakage current during static RAM (SRAM) ready mode; And
Figure 26 is the comparative result figure of explanation good article rate.
Embodiment
By the following description of the embodiment of described accompanying drawing after the reference, advantage of the present invention, feature and aspect can become apparent.
In the accompanying drawings, in order to clearly demonstrate, the size in layer and zone is amplified.Also should be understood that when one deck (or film) is called as at another layer or substrate ' on ' can also can there be the middle layer in it directly on another layer or substrate.In addition, should be understood that when one deck is called as at another layer ' descending ' that can also can there be one or more interposed layer in it directly under another layer.In addition, should be understood that also when one deck to be called as when two-layer ' between ' that also can there be one or more interposed layer in the sole layer that it can be between two-layer.
The present invention can realize high and uniform bmd density in the body regions by wafer silicon being used two step annealing processs.As a result, the present invention can gettering site (gettering site) prevents because the generation of the lattice defect that the heat budget that follow-up high-temperature heat treatment process causes causes by increasing fully.
Fig. 1 is the cross-sectional view according to the silicon wafer of one embodiment of the invention.
As shown in Figure 1, silicon wafer 100 comprises: the first denuded zone DZ1, and the first denuded zone DZ1 forms the predetermined depth that has from silicon wafer end face 101; And body regions BK, this body regions BK is formed between the first denuded zone DZ1 and the back side 102.Silicon wafer 100 also comprises the second denuded zone DZ2, and the second denuded zone DZ2 forms has from this back side 102 predetermined depths towards the direction of this end face 101.
The first denuded zone DZ1 that formation has from the predetermined depth of end face 101 direction of 102 towards the back side is area free from defect (DFZ), and there is not the lattice defect such as room and dislocation in it.Preferably, the first denuded zone DZ1 form have from end face 101 direction of 102 towards the back side about 20 microns to about 80 microns degree of depth.
The second denuded zone DZ2 also has from the back side 102 towards the direction of end face 101 degree of depth identical with the first denuded zone DZl degree of depth for DFZ and forming, or according to the glossing to the back side 102, the second denuded zone DZ2 forms the degree of depth that has less than the degree of depth of the first denuded zone DZ1.That is when both indistinguishably carried out mirror polish to the end face 101 of silicon wafer 100 and the back side 102, the first denuded zone DZl and the second denuded zone DZ2 form had same depth.On the contrary, when mirror polish is not carried out at the back side 102 when end face 101 is carried out mirror polish, the second denuded zone DZ2 forms the degree of depth that has less than the first denuded zone DZl degree of depth, and this is because form oxygen precipitates according to the close back side 102 of the roughness at the back side 102.
The body regions BK that forms between the first denuded zone DZl and the second denuded zone DZ2 comprises this bulky micro defect (BMD) 103.It is even that BMD 103 keeps in whole body regions.BMD 103 comprises throw out and body stacking fault (bulk stacking fault).In addition, can control BMD 103 among the body regions BK to have sufficient density, gettering is via follow-up high-temperature heat treatment process or thermal process and the metal pollutant that spreads on the surface of silicon wafer by this.BMD 103 among the body regions BK can keep density to be preferably about 1 * 10 5Ea/cm 2To about 1 * 10 7Ea/cm 2, more preferably about 1 * 10 6Ea/cm 2To 1 * 10 7Ea/cm 2The concentration of oxygen among the body regions BK (hereinafter referred to as ' oxygen concn ') and oxygen precipitate are closely related, preferred oxygen concentration change profile in 10% and remain about 10.5～about 13PPMA (atom PPM) in whole body regions BK.
Fig. 2 makes the cross-sectional view of the method for silicon wafer according to first embodiment of the invention for explanation.
With reference to figure 2, preparation silicon wafer 200.At this moment, silicon wafer 200 can be naked wafer.Can form silicon wafer 200 according to following steps.At first, behind growing single-crystal silicon, silicon single crystal is cut into wafer shape.Implement etch process with etching through the surface of cut crystal or make behind the sphering of the side of cut crystal, mirror polish is carried out at end face 201 and the back side 202 of silicon wafer 200.At this moment, use crystal growth vertical pulling method (Czochralski, CZ) silicon single crystal of growing.In addition, can after subsequent thermal technology, implement mirror-polishing process to silicon wafer 200.
Enforcement is to first thermal process of silicon wafer 200, makes the end face 201 of silicon wafer 200 and the oxide elements 203 between the back side 202 to internal divergence.As a result, form the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.First thermal process can be RTP (rapid hot technics) or uses the annealing process of furnace apparatus.Preferably, first thermal process comprises RTP.
Be the end face 201 of rapid diffusion silicon wafer 200 and the oxide elements 203 in the back side 202, use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its combination at high temperature implements first thermal process.When first thermal process is RTP, is 1050 ℃ in scope and implements first thermal process to about 1150 ℃ temperature and last about 10 seconds to about 30 seconds.When first thermal process is annealing process, is 1050 ℃ in scope and implements first thermal process to about 1150 ℃ temperature and last about 100 minutes to about 300 minutes.
Then, implement second thermal process to silicon wafer 200, make oxide elements 203 combinations among the body regions BK.As a result, produce oxygen precipitate nuclear 204.Similar with first thermal process, second thermal process can be RTP or uses the annealing process of furnace apparatus.Second thermal process preferably includes RTP.
For being easy to form oxygen precipitate nuclear 204, use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its be combined under the temperature of the temperature that is lower than first thermal process and implement second thermal process.When second thermal process is RTP, is about 950 ℃ in scope and implements second thermal process to about 1000 ℃ temperature and last about 10 seconds to about 30 seconds.When second thermal process is annealing process, is about 950 ℃ in scope and implements second thermal process to about 1000 ℃ temperature and last about 100 minutes to about 200 minutes.
Subsequently, after finishing second thermal process, silicon wafer 200 is implemented first annealing process.Use furnace apparatus to implement first annealing process.By heating silicon wafer 200 under the preset temperature of the temperature that is lower than second thermal process, replenish the oxygen precipitate nuclear 204 that produces among the body regions BK, simultaneously, produce oxygen precipitate 205A.Preferably, being about 750 ℃ in scope implements first annealing process to about 800 ℃ temperature and lasts about 100 minutes to about 180 minutes.In addition, at oxygen (O 2) atmosphere encloses and implement down first annealing process.
After finishing first annealing process, silicon wafer 200 is implemented second annealing process.Also use furnace apparatus to implement second annealing process.By heating silicon wafer 200 under the preset temperature of the temperature that is higher than first annealing process, increase oxygen precipitate 205A.As a result, the oxygen precipitate 205B of generation through increasing.Preferably, being about 1000 ℃ in scope implements second annealing process to about 1150 ℃ temperature and lasts about 100 minutes to about 180 minutes.In addition, at oxygen (O 2) atmosphere encloses and implement down second annealing process.
Hereinafter, describe first annealing process and second annealing process in detail.Hereinafter, first annealing process and second annealing process are called two step annealing processs.
Fig. 6 is the graphic representation of explanation according to two step annealing processs of an embodiment of the present invention.
Referring to Fig. 6, use the annealing process of furnace apparatus to comprise use oxygen (O 2) gas is at first annealing process (II) that makes silicon wafer 200 annealing under first temperature and be higher than second annealing process (IV) of implementing to make silicon wafer 200 annealing under second temperature of first temperature.Implement first annealing process (II) and second annealing process (IV) and all last about 100 minutes to about 180 minutes.The scope of first temperature of first annealing process (II) is about 750 ℃ to about 800 ℃, and the scope of second temperature of second annealing process (IV) is about 1000 ℃ to about 1150 ℃.
Effect for improvement oxidizing process and thermal treatment process, (II) is preceding at first annealing process, can comprise further that according to the two step annealing processs of embodiment of the present invention that silicon wafer 200 is loaded into furnace apparatus is inner and then silicon wafer 200 is retained to the loading process (L) that loading temperature lasts a predetermined lasting time.And, behind second annealing process (IV), can further be included in according to the two step annealing processs of embodiment of the present invention and silicon wafer 200 to be retained to the uninstall process (UL) that unloading temperature lasts a predetermined lasting time before silicon wafer 200 is offloaded to the furnace apparatus outside.
The loading temperature of loading process (L) is lower than first temperature.Preferably, the scope of loading temperature is about 600 ℃ to about 700 ℃.During loading process (L) not with oxygen supply to furnace apparatus.As a result, silicon wafer 200 is not subjected to oxidation during loading process (L).The unloading temperature of uninstall process (UL) equals first temperature substantially.Preferably, the scope of unloading temperature is about 750 ℃ to about 800 ℃.During uninstall process (UL), not supply oxygen and the supply of nitrogen only.The scope of the flow rate of nitrogen is that about 9slm is to about 11slm.
In addition, according to the two step annealing processs of embodiment of the present invention can further be included between loading process (L) and first annealing process (II) be used for loading temperature be heated to first heating process (I) of first temperature and between first annealing process (II) and second annealing process (IV) for second heating process (III) that first temperature is heated to second temperature.When the per minute temperature rise rate was too high during first heating process (I) and second heating process (III), chip architecture may be out of shape.Therefore, the temperature rise rate in first heating process (I) and second heating process (III) can be set at about 5 ℃/minute to about 8 ℃/minute scope.
And, can further be included in the process for cooling (V) that is used for second temperature is cooled to unloading temperature between second annealing process (IV) and the uninstall process (UL) according to the two step annealing processs of embodiment of the present invention.The scope of the rate of temperature fall of process for cooling (V) can be about 2 ℃/minute to about 4 ℃/minute.
In two step annealing processs according to embodiment of the present invention, the annealing of silicon wafer 200 mainly realizes during first annealing process and second annealing process (II, IV) substantially, because supply oxygen during these technologies only.The scope of the flow rate of the oxygen of supplying during first annealing process and second annealing process (II, IV) can be about 50sccm to about 120sccm.Can implement first annealing process and second annealing process (II, IV) and all last about 100 minutes to about 180 minutes.
The following embodiment according to the present invention that can be applicable to show among Fig. 3 to Fig. 5 as the two step annealing processs of describing among Fig. 6 is for the manufacture of first annealing process and second annealing process of the method for silicon wafer.
Fig. 3 is the cross-sectional view for the manufacture of the method for silicon wafer of explanation according to second embodiment of the present invention.
Referring to Fig. 3, implement the thermal process to silicon wafer 300, make the end face 301 of silicon wafer 300 and the oxide elements 303 between the back side 302 to internal divergence.As a result, form the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.Thermal process can be RTP or uses the annealing process of furnace apparatus.Preferably, first thermal process comprises RTP.
For the end face 301 of rapid diffusion silicon wafer 300 and the oxide elements 303 at the back side 302, at high temperature implement thermal process.When thermal process is RTP, is 1050 ℃ in scope and implements thermal process to about 1150 ℃ temperature and last about 10 seconds to about 30 seconds.When thermal process is annealing process, is 1050 ℃ in scope and implements thermal process to about 1150 ℃ temperature and last about 100 minutes to about 200 minutes.
Subsequently, silicon wafer 300 is implemented first annealing process, make oxide elements 203 combinations among the body regions BK.As a result, form oxygen precipitate nuclear 304.Under the preset temperature of the temperature that is lower than thermal process, use furnace apparatus to implement first annealing process.Preferably, being about 750 ℃ in scope implements first annealing process to about 800 ℃ temperature and lasts about 100 minutes to about 180 minutes.In addition, at oxygen (O 2) atmosphere encloses and implement down first annealing process.
Silicon wafer 300 is implemented second annealing process.Also use furnace apparatus to implement second annealing process.By heating silicon wafer 300 under the preset temperature of the temperature that is higher than first annealing process, produce oxygen precipitate 305.Preferably, being about 1000 ℃ in scope implements second annealing process to about 1150 ℃ temperature and lasts about 100 minutes to about 180 minutes.In addition, at oxygen (O 2) atmosphere encloses and implement down second annealing process.
Fig. 4 is the cross-sectional view for the manufacture of the method for silicon wafer of explanation according to the 3rd embodiment of the present invention.
In Fig. 4, the thermal process before being implemented in first annealing process under the temperature of the thermal process temperature that is lower than Fig. 3.
With reference to figure 4, under the temperature of the thermal process temperature that is lower than Fig. 3, silicon wafer 400 is implemented thermal process.Therefore, produce oxygen precipitate nuclear 404.Because thermal process is implemented at low temperatures, so in the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK, form oxygen precipitate nuclear 404.Thermal process can be RTP or annealing process.Preferably, first thermal process comprises RTP.When thermal process is RTP, to about 1000 ℃ temperature, implemented thermal process about 10 seconds to about 30 seconds at about 950 ℃.When thermal process is annealing process, to about 1000 ℃ temperature, implemented thermal process about 100 minutes to about 200 minutes at about 950 ℃.
Subsequently, silicon wafer 400 is implemented first annealing process and second annealing process successively, make to produce oxygen precipitate nuclear 404 and oxygen precipitate 405A.Under the condition identical with those conditions of first annealing process of Fig. 3 and second annealing process, implement first annealing process and second annealing process.
Fig. 5 makes the cross-sectional view of the method for silicon wafer according to four embodiment of the invention for explanation.
With reference to figure 5, different with the annealing process shown in Fig. 2 to Fig. 4, need not extra heat technology before first annealing process and second annealing process according to the annealing process of four embodiment of the invention.That is, be provided as the silicon wafer 500 of naked wafer, and silicon wafer 500 is implemented first annealing process and second annealing process successively, make to form the first denuded zone DZl and the second denuded zone DZ2 and body regions BK.To the identical condition of those conditions of first annealing process shown in Figure 4 and second annealing process, implementing first annealing process and second annealing process with Fig. 2.
In Fig. 5, Reference numeral ' 501 ' expression end face, ' 502 ' the expression back side, ' 503 ' expression oxide elements, ' 504 ' expression oxygen precipitate nuclear, ' 505A ' represents oxygen precipitate, the oxygen precipitate that ' 505B ' expression increases.
The method of silicon wafer constructed in accordance is described referring to figs. 2 to Fig. 5 as mentioned above.As previously mentioned, to first to the 3rd embodiment shown in Figure 4, RTP preferably was used for thermal process before first annealing process and second annealing process at Fig. 2.
The subsurface defect of the oxygen precipitate in the silicon wafer or void defects can be controlled during monocrystalline silicon growing, or control by thermal process behind monocrystalline silicon growing.As indicated above, thermal process can comprise the RTP that uses halogen lamp and the annealing process that uses furnace apparatus.
At argon (Ar) gas or hydrogen (H 2) atmosphere encloses down and to be higher than the annealing process of implementing to use furnace apparatus under about 1000 ℃ high temperature greater than about 100 minutes long-time.Diffusion and the silicon of oxide elements are reset in the silicon wafer that causes by annealing process thus, form device ideal area (that is nondefective zone (DFZ)) in the part of the end face of silicon wafer.Yet along with silicon wafer sizes increases, this annealing process is difficult to control pollution or the slip dislocation of silicon wafer owing to high-temperature heat treatment.
Therefore, RTP obtains to be better than the silicon wafer characteristic of annealing process.Yet, when the silicon wafer that uses various defect detecting methods assessments to be made by RTP, the control oxygen precipitate only from end face about 3 microns to about 10 microns degree of depth.In addition, when when only implementing RTP and make silicon wafer once or twice, exist realizing the restriction of high bmd density in the body regions.More specifically, when once making silicon wafer by enforcement RTP, bmd density is through being defined as 1 * 10 6Ea/cm 2To 3 * 10 6Ea/cm 2, and be difficult to make bmd density to exceed this scope.
In embodiments of the invention, to shown in Figure 4, after thermal process, implement two step annealing processs as Fig. 2, remove void defects and oxygen precipitate near the silicon wafer end face thus.As a result, the present invention can guarantee nondefective zone (DFZ) and increase to comprise that the body in the body regions piles up the bmd density of defective and oxygen precipitate, improve the gettering effect by the gettering site that increases in the body regions thus.
Hereinafter, reference table 1 and table 2 are described the characteristic of the silicon wafer of being made by embodiment of the present invention in detail.
[table 1]
Condition 1 Condition 2 Condition 3 Condition 4
High temperature RTP 1050℃～1150℃ 1050℃～1150℃ Omit Omit
Low temperature RTP 950℃～1000℃ Omit 950℃～1000℃ Omit
Low temperature annealing process 750℃～800℃ 750℃～800℃ 750℃～800℃ 750℃～800℃
High-temperature annealing process 1000℃～1150℃ 1000℃～1150℃ 1000℃～1150℃ 1000℃～1150℃
[table 2]
Figure G2009101745256D00111
In table 1, use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its combination, under rapid thermal process, implement ' high temperature RTP ' and ' low temperature RTP ' about 10 seconds to about 30 seconds.Use oxygen (O 2) gas implemented ' low temperature annealing process ' and ' high-temperature annealing process ' about 100 minutes to about 180 minutes.
In table 1 and table 2, ' first embodiment shown in the condition 1 ' presentation graphs 2, ' second embodiment shown in the condition 2 ' presentation graphs 3, ' the 3rd embodiment shown in the condition 3 ' presentation graphs 4, ' the 4th embodiment shown in the condition 4 ' presentation graphs 5.Table 2 shows bmd density and denuded zone (DZ) degree of depth according to the oxygen concn in each condition (Oi).
Fig. 7 to Figure 12 is the figure of the parameter of indicator gauge 1 and table 2.Particularly, Fig. 7 is the figure of explanation for the bmd density of each condition.Fig. 8 is the figure of explanation for the DZ degree of depth of each condition.Fig. 9 to Figure 12 is the figure of explanation for oxygen concn in the body regions of each condition.
Reference table 2 and Fig. 7 all obtain greater than 1 * 10 under all conditions 5Ea/cm 2Bmd density.Particularly, regardless of oxygen concn, all obtain greater than 1 * 10 for 1 time in condition 6Ea/cm 2Bmd density.Although do not show that measurable this bmd density is compared significantly lower with the bmd density under the above condition for the data of the bmd density by only implementing the silicon wafer that RTP makes once or twice.
As previously mentioned, control metal pollutant by gettering BMD.Yet, because bmd density tends to reduce during high-temperature technology, during making silicon wafer, need to guarantee high bmd density.Generally speaking, the high voltage device that need under high voltage environment, operate of semiconducter device.For making this high voltage device, must implement severe ion implantation technology and high-temperature annealing process, this is because need have the tie region (that is doped region) of dark distribution.When bmd density reduces during high-temperature annealing process, not only owing to defect estimation but also owing to low gettering ability, so after (STI), occur the ring-type dislocation at follow-up shallow trench isolation.
As the result who measures bmd density, when bmd density is about 2.5 * 10 5Ea/cm 2The time part ring-type dislocation appears, but when bmd density be about 4.4 * 10 5Ea/cm 2The time ring-type dislocation do not appear.Therefore, need the control bmd density greater than at least 1 * 10 5Ea/cm 2In the present embodiment, during making silicon wafer, regardless of conventional thermal process, all to implement two step annealing processs in addition for the initial process of making semiconducter device.Initial process is included in the ion implantation oxidizing process of implementing before that forms trap.Oxidizing process is corresponding to the technology that is used to form screen oxide layer during forming ion implantation (hereinafter, be called trap ion implantation) of trap.
Reference table 2 and Fig. 8 show the DZ degree of depth according to each condition.The DZ degree of depth and bmd density and oxygen concn are closely related.Along with bmd density and oxygen concn increase, the DZ degree of depth reduces.When oxygen concn under each condition all when identical (for example, being 11.6 in the table 2), the bmd density under condition 1 and the condition 2 is higher than the bmd density under condition 3 and the condition 4, but the DZ degree of depth under condition 1 and the condition 2 is lower than the DZ degree of depth under condition 3 and the condition 4.Therefore, the DZ degree of depth can be the tolerance of bmd density.
Reference table 2 and Fig. 9 to Figure 12 show under each condition bmd density and the DZ degree of depth according to oxygen concn.Along with oxygen concn (Oi) increases, bmd density increases and the DZ degree of depth reduces.Therefore, oxygen concn (Oi) also is the tolerance of bmd density.That is, can calculate bmd density in the body regions by measuring the DZ degree of depth and oxygen concn (Oi).
Figure 13 and Figure 14 are the cross-sectional view of silicon wafer.
Particularly, RTP does not have two step annealing processs with the cross-sectional view of the silicon wafer of manufacturing by only implementing in Figure 13 demonstration, and Figure 14 shows according to the cross-sectional view of one embodiment of the invention by the silicon wafer of enforcement two step annealing processs manufacturing.
As shown in the figure, a plurality of silicon dislocations in the silicon wafer of Figure 13, occur, but in the silicon wafer of Figure 14, do not have the silicon dislocation.In addition, when forming epitaxial film by the use epitaxy, the lattice defect in the body regions of silicon wafer (wherein forming epitaxial film) is significantly reduced.
Figure 15 and Figure 16 illustrate the lattice defect figure of body regions in the silicon wafer (wherein forming epitaxial film).Use is implemented this check by the verifying attachment that KLA company makes.
As shown in Figure 15, when implementing not have the oxidizing process of two step annealing processs, a large amount of lattice defects are distributed among the figure.At this, oxidizing process forms screen oxide layer during trap is ion implantation.On the contrary, as shown in Figure 16, when implementing to have the oxidizing process of two step annealing processs of the present invention, lattice defect significantly reduces.
Hereinafter, will describe the method for making the semiconducter device with trap that is used for high voltage device in detail referring to figs. 17A through Figure 17 D, this method comprises two step annealing processs according to an embodiment of the invention.
Figure 17 A to Figure 17 D makes the method for semiconducter device according to an embodiment of the invention for explanation.
With reference to figure 17A, use the two step annealing processs that show among Fig. 6 to form screen oxide layer 601 at silicon wafer 600.Silicon wafer 600 can be the enforcement RTP wafer once or twice described in Fig. 2 to Fig. 4, or is the naked wafer of not implementing RTP as shown in Figure 5.Screen oxide layer 601 can be silicon oxide layer, and forms approximately
Figure G2009101745256D00131
To about
Figure G2009101745256D00132
Thickness.
With reference to figure 17B, in silicon wafer 600, form trap 602 to one predetermined depths.Trap 602 can be p-type or n type conduction type according to the conduction type of high voltage device.
Form trap 602 by ion implantation technology and diffusion technique.Use ion implantation technology only to be difficult to be formed for the trap of high voltage device.Therefore, should after finishing ion implantation technology, implement diffusion technique and ion implantation technology, the trap 602 that has the dopant profiles of Figure 17 B with formation in addition.By using the annealing process implemented for long periods diffusion technique such as the high-temperature heating equipment of stove.Preferably, use only nitrogen (N 2) gas implemented diffusion technique about 6 hours to about 10 hours at about 1100 ℃ to about 1250 ℃ temperature.
Referring to Figure 17 C, pad nitride layer (not shown) as hard mask is formed on the screen oxide layer 601, or pad nitride layer is formed on the buffer layer (not shown), and this buffer layer is by implementing the excess oxygen metallization processes and form removing screen oxide layer 601 backs.The reason that removes screen oxide layer 601 is that screen oxide layer 601 is not suitable for buffer layer, and this is because screen oxide layer 601 is damaged during ion implantation technology.Be formed for forming the photoresist material pattern 604 of sti trench groove then in pad nitride layer.
Pad nitride layer can be passed through low-pressure chemical vapor deposition (LPCVD) technology and form, to prevent that by being minimized in the stress that is applied to silicon wafer 600 during the depositing operation silicon wafer 600 is impaired.Pad nitride layer can be formed by silicon nitride.Pad nitride layer can form approximately
Figure G2009101745256D00141
To about
Figure G2009101745256D00142
Figure G2009101745256D00143
Thickness.
Make that pattern 604 is as etching mask with photoresist, partly etching pad nitride layer, screen oxide layer 601 and silicon wafer 600 form pad nitride pattern 603, screen oxide pattern 601A, silicon wafer 600A and trap 602A thus successively.As a result, in silicon wafer 600A, form the groove 605 with predetermined depth and slope.
Referring to Figure 17 D, form the device isolation structure 606 of filling groove 605, remove pad nitride pattern 603 and screen oxide pattern 601A subsequently.Device isolation structure 606 can be formed by the high density plasma with excellent gap-filling properties (HDP) layer.
In method more of the present invention and Comparative Examples, the beneficial effect of above embodiment of the present invention will be described hereinafter.Method of the present invention comprises that the oxidizing process by using two step annealing processs forms screen oxide layer, and Comparative Examples comprises that the oxidizing process by using a step annealing technology forms screen oxide layer.In the oxidizing process of this Comparative Examples, use wet oxidation process silicon wafer under 800 ℃ to 850 ℃ single temperature.
Figure 18 to Figure 21 explanation is by the defective in the silicon wafer of the oxidizing process preparation of Comparative Examples.
Specifically, Figure 18 explanation forms groove via STI technology in the silicon wafer of the oxidizing process preparation by Comparative Examples after, the diagram data of the lattice defect of being checked by the verifying attachment of KLA company manufacturing.As shown in figure 18, can be observed the lattice defect that exists in most of defect chips such as ring-type silicon dislocation.
Silicon wafer scanning electronic microscope (SEM) photo that Figure 19 and Figure 20 obtain for the verifying attachment by the manufacturing of KLA company.
Particularly, Figure 19 is for showing the SEM image in silicon wafer cross section, and Figure 20 is plane inclination STM image.As Figure 19 and shown in Figure 20, can be observed and have lattice defect and dislocation.
Figure 21 is for showing the Photomicrograph that the silicon wafer with ring-type defective is carried out this bulky micro defect (BMD) density analysis.
As shown in Figure 21, can be observed most of BMD near the end face formation of silicon wafer, and only have minority BMD to be formed in the middle body of silicon wafer, that is, be formed in the body regions.That is, the bmd density of body regions significantly is lower than the bmd density of the end face of silicon wafer.
Figure 22 to Figure 24 is the assay by lattice defect in the silicon wafer that uses the oxidizing process preparation of two step annealing processs according to embodiments of the present invention.This check uses the verifying attachment of being made by KLA company to implement.
Specifically, the assay of the lattice defect of silicon wafer after Figure 22 explanation forms groove via STI technology in the silicon wafer of the oxidizing process preparation of the two step annealing processs of the application of the invention.As shown in figure 22, can be observed that lattice defect is removed and only detect some particulates or dust.
Figure 23 is the plane inclination STM image of the silicon wafer that obtained by the verifying attachment of KLA company manufacturing.Similar with the result of Figure 22, can be observed and only detect some particles.
Figure 24 carries out the Photomicrograph that bmd density is analyzed for showing the silicon wafer to the oxidizing process preparation of the application of the invention two step annealing processs.As shown in figure 24, can be observed the even BMD of formation in whole silicon wafer.
Figure 25 is the comparative result figure of explanation leakage current during static RAM (SRAM) ready mode.In Figure 25, the figure on the left side shows the sample of the high voltage device that the oxidizing process of the application of the invention two step annealing processs prepares, and the figure on the right shows the sample of the high voltage device of Comparative Examples.As shown in figure 25, compare with the sample of oxidizing process preparation by Comparative Examples, the sample that can be observed by oxidizing process preparation of the present invention shows even leakage current characteristic.
Figure 26 is the comparative result figure of explanation good article rate.In Figure 26, the figure on the left side shows the sample of the high voltage device that the oxidizing process of the application of the invention two step annealing processs prepares, and the figure on the right shows the sample of the high voltage device of Comparative Examples.As shown in figure 26, compare the high about 5%-9% of good article rate of the sample by oxidizing process of the present invention preparation with the sample of Comparative Examples.
According to the present invention, at first, can in silicon wafer, produce the gettering site fully by under differing temps, implementing two step annealing processs.This makes and can prevent because the generation of the lattice defect that the heat budget that follow-up high-temperature heat treatment process causes causes.
Secondly, the present invention can be provided at the silicon wafer that has height and Uniform B MD density in the body regions by implement two step annealing processs under differing temps.
The 3rd, according to the present invention, under differing temps, silicon wafer implemented two step annealing processs after, use epitaxy to form epitaxial film at silicon wafer.As a result, the present invention can provide the semiconducter device that forms the epitaxial film with excellent specific property.
The 4th, according to the present invention, by under differing temps, silicon wafer being implemented two step annealing processs with after forming screen oxide layer at silicon wafer, implement ion implantation technology in silicon wafer, to form trap by using screen oxide layer as the ion mask.As a result, the present invention can produce the gettering site fully in silicon wafer, to prevent thus because the generation of the lattice defect that heat budget was caused that causes of follow-up high-temperature heat treatment process.
Although described the present invention for particular, those skilled in the art obviously can make various changes and modification under the situation that does not depart from the spirit of the present invention that limited by following claim and category.

Claims (5)

1. silicon wafer, it comprises:
First denuded zone, it is formed in the described silicon wafer; With
Body regions, it is formed between the back side of described first denuded zone and described silicon wafer,
Wherein said first denuded zone forms the degree of depth that has from 20 microns to 80 microns of described end faces,
The variation in 10% in whole described body regions of oxygen concn in the wherein said body regions evenly distributes, and
The density of this bulky micro defect is greater than 5.43 * 10 in the wherein said body regions 6Ea/cm 2And be less than or equal to 1 * 10 7Ea/cm 2
2. silicon wafer as claimed in claim 1, the oxygen concn in the wherein said body regions is 10.5 to 13 atom PPMs.
3. silicon wafer as claimed in claim 1, it also comprises epitaxial film, described epitaxial film is formed on the end face of described silicon wafer by epitaxy.
4. silicon wafer as claimed in claim 1, it also comprises second denuded zone, described second denuded zone is formed at described body regions below and has the predetermined depth towards the direction of described end face from the described back side.
5. silicon wafer as claimed in claim 4, wherein said second denuded zone forms the degree of depth that has from 20 microns to 80 microns at the described back side.
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