JPS62179731A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62179731A JPS62179731A JP2232186A JP2232186A JPS62179731A JP S62179731 A JPS62179731 A JP S62179731A JP 2232186 A JP2232186 A JP 2232186A JP 2232186 A JP2232186 A JP 2232186A JP S62179731 A JPS62179731 A JP S62179731A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- defect
- oxygen
- heating
- recrystallized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 129
- 239000001301 oxygen Substances 0.000 claims abstract description 34
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 31
- 230000007547 defect Effects 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 18
- 239000002344 surface layer Substances 0.000 claims abstract description 13
- 238000001953 recrystallisation Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000002244 precipitate Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- -1 oxygen ion Chemical class 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
Ｓｏｌ（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｏｎ Ｉｎ５ｕ
ｌａｔｏｒ）膜の表面に無欠陥層を、内部に欠陥層を形
成し、無欠陥層に素子形成を行う。内部の欠陥層による
有害不純物のゲッタリングにより無欠陥層の小数キャリ
アのライフタイムを大きくし、リーク電流等の素子特性
を向上する。[Detailed Description of the Invention] [Summary] Sol (Semiconductor On In5u
(lator) A defect-free layer is formed on the surface of the film, a defect-free layer is formed inside the film, and elements are formed on the defect-free layer. Gettering of harmful impurities by the internal defect layer increases the lifetime of minority carriers in the defect-free layer, improving device characteristics such as leakage current.
本発明はＳＯＴ膜に素子を形成してなる半導体装置に関
する。The present invention relates to a semiconductor device in which elements are formed on an SOT film.
ＳＯＴ構造は、基板の浮遊容量が小さく高速素子の形成
ができ、またＣＭＯＳデバイスで問題となっているｐｎ
ｐｎスイッチによるランチアップ現象がなく、さらに多
層素子の形成が可能となる。The SOT structure has a small stray capacitance on the substrate, making it possible to form high-speed devices.
There is no launch-up phenomenon caused by a pn switch, and it is possible to form a multilayer element.
しかしながら、現状ではＳｏｌは微小欠陥が多数存在し
、前記ライフタイムが通常のバルク珪素（Ｓｉ）の場合
より２桁程度小さくなる。However, at present, Sol has many micro defects, and the lifetime is about two orders of magnitude shorter than that of ordinary bulk silicon (Si).
Ｓｏｌ膜の形成はつぎのように行う。 The formation of the Sol film is performed as follows.
例えば、Ｓｉ基板上に絶縁層として二酸化珪素（ＳｔＯ
ｌ）層を被着し、この上に多結晶半導体層を形成し、こ
の層にレーザビーム等を照射して局部的に溶融しながら
再結晶化して再結晶半導体層を形成する。For example, silicon dioxide (StO) is used as an insulating layer on a Si substrate.
l) A layer is deposited, a polycrystalline semiconductor layer is formed thereon, and this layer is irradiated with a laser beam or the like to locally melt and recrystallize to form a recrystallized semiconductor layer.
この場合、再結晶半導体層の単結晶化は難しく、また単
結晶化されたとしても結晶欠陥密度が大きく、従ってこ
の層に素子を形成しても、よい特性の素子は得られなか
った。In this case, it is difficult to make the recrystallized semiconductor layer into a single crystal, and even if it is made into a single crystal, the density of crystal defects is large, so even if an element is formed in this layer, an element with good characteristics cannot be obtained.
従来のｓｏｒ膜は結晶欠陥数が多かった。 Conventional SOR films have a large number of crystal defects.
上記問題点の解決は、絶縁層上に再結晶半導体層を形成
し、該再結晶半導体層に酸素を導入し、第１の加熱によ
り該再結晶半導体層の表面層の酸素濃度を低減し、該第
１の加熱より低温で行う第２の加熱により該再結晶半導
体層の内部の高酸素濃度領域に結晶欠陥核を生成させ、
該第２の加熱より高温で行う第３の加熱により該結晶欠
陥核を成長させ、該再結晶半導体層の表面層に無欠陥層
を形成し、該無欠陥層に素子を形成してなる半導体装置
、あるいは
絶縁層上に再結晶半導体層を形成し、該再結晶半導体層
の表面層を除いて該再結晶半導体層の内部に酸素導入領
域を形成し、第１の加熱により該酸素導入領域に結晶欠
陥核を生成させ、該第１の加熱より高温で行う第２の加
熱により該結晶欠陥核を成長させ、該再結晶半導体層の
表面層に無欠陥層を形成し、該無欠陥層に素子を形成し
てなる半導体装置により達成される。The above problem can be solved by forming a recrystallized semiconductor layer on the insulating layer, introducing oxygen into the recrystallized semiconductor layer, and reducing the oxygen concentration in the surface layer of the recrystallized semiconductor layer by first heating. generating crystal defect nuclei in a high oxygen concentration region inside the recrystallized semiconductor layer by second heating performed at a lower temperature than the first heating;
A semiconductor in which the crystal defect nuclei are grown by third heating performed at a higher temperature than the second heating, a defect-free layer is formed in the surface layer of the recrystallized semiconductor layer, and an element is formed in the defect-free layer. A recrystallized semiconductor layer is formed on a device or an insulating layer, an oxygen introduction region is formed inside the recrystallization semiconductor layer except for the surface layer of the recrystallization semiconductor layer, and the oxygen introduction region is removed by first heating. to generate crystal defect nuclei, grow the crystal defect nuclei by second heating performed at a higher temperature than the first heating, form a defect-free layer in the surface layer of the recrystallized semiconductor layer, and form a defect-free layer in the surface layer of the recrystallized semiconductor layer. This is achieved by a semiconductor device in which elements are formed in a semiconductor device.
前記無欠陥層と酸素導入領域との境界に絶縁層を形成し
てなる半導体装１は、素子形成された無欠陥層を内部欠
陥層から絶縁するためのものであり、ちょうどＳｏｌ膜
の中にさらに３０１構造を形成したものといえる。The semiconductor device 1, which is formed by forming an insulating layer at the boundary between the defect-free layer and the oxygen-introduced region, is for insulating the defect-free layer in which the element is formed from the internal defect layer. Furthermore, it can be said that a 301 structure is formed.
また、無欠陥層の厚さが素子形成用としで簿すぎる場合
は、無欠陥層の上にエピタキシャル成長を行って、所望
の厚さを得ることができる。Furthermore, if the thickness of the defect-free layer is too large for device formation, epitaxial growth can be performed on the defect-free layer to obtain the desired thickness.
Ｓｏｌ膜の内部に高濃度酸素導入層を形成し、熱処理を
行ってこの層に酸素の析出物による内部欠陥層を形成し
、また表面の酸素濃度を下げることにより表面を無欠陥
層とする。A high-concentration oxygen-introduced layer is formed inside the Sol film, and heat treatment is performed to form an internal defect layer of oxygen precipitates in this layer, and the surface is made defect-free by lowering the oxygen concentration on the surface.
この内部欠陥層のゲッタリング（半導体デバイス形成に
有害な、重金属、ナトリウム等デバイス特性の劣化に関
連する原子を内部欠陥層が吸収する作用）によりデバイ
ス特性を向上させることができる。Device characteristics can be improved by gettering of this internal defect layer (an effect in which the internal defect layer absorbs atoms harmful to semiconductor device formation and associated with deterioration of device characteristics, such as heavy metals and sodium).
また、表面無欠陥層と内部欠陥層の境界に絶縁層を挟ん
で、表面無欠陥層に形成した素子を内部欠陥層より電気
的に絶縁して、素子形成の自由度を上げることができる
。さらにこの絶縁層を介して内部欠陥層をバンクチャネ
ル制御用の第２ゲートとして用いることも可能である。Further, by sandwiching an insulating layer between the surface defect-free layer and the internal defect-free layer, the element formed in the surface defect-free layer is electrically insulated from the internal defect layer, thereby increasing the degree of freedom in device formation. Furthermore, it is also possible to use the internal defect layer as a second gate for bank channel control via this insulating layer.
第１図（１１〜（５）は第１の発明による半導体素子の
形成工程を説明する断面図である。FIGS. 11-(5) are cross-sectional views illustrating the steps of forming a semiconductor element according to the first invention.
第１図（１）において、■は基板でＳｉ基板、この上に
絶縁層としてＳｉＯ□層２、再結晶半導体層として厚さ
４０００人の再結晶Ｓｉ層３を形成する。In FIG. 1 (1), ``■'' is a Si substrate, on which a SiO□ layer 2 is formed as an insulating layer, and a recrystallized Si layer 3 with a thickness of 4000 nm is formed as a recrystallized semiconductor layer.
第１図（２）において、酸素イオンＯ＋注入等により酸
素をドープして、再結晶Ｓｉ層３を酸素濃度が１０ＩＢ
ＣＩ１１−３程度の高濃度酸素導入領域３Ｂ’にする。In FIG. 1 (2), the recrystallized Si layer 3 is doped with oxygen by oxygen ion O+ implantation or the like to have an oxygen concentration of 10 IB.
The high concentration oxygen introduction region 3B' has a CI of about 11-3.
第１図（３）において、
１０００℃以上で数１０分以上第１の加熱を行い、酸素
のアウトディフュージョンにより再結晶Ｓｉ層３（高濃
度酸素導入領域３Ｂ′）の表面層の酸素濃度を下げ、５
×１０１７ｃｍ４以下にする。In FIG. 1 (3), the first heating is performed at 1000° C. or higher for several tens of minutes or more, and the oxygen concentration in the surface layer of the recrystallized Si layer 3 (high-concentration oxygen introduced region 3B') is lowered by oxygen outdiffusion. ,5
x1017cm4 or less.
つぎに、６００℃程度で数時間第２の加熱を行い、内部
の高濃度酸素導入領域に酸素の析出物による結晶欠陥核
を形成させ、
つぎに、１０００℃以上で数１０分以上第３の加熱を行
い結晶欠陥核を成長させることにより、再結晶Ｓｉ層３
０表面に厚さ約１０００への表面無欠陥層３Ａ、その下
側に内部欠陥層３Ｂを形成する。Next, a second heating is performed at about 600°C for several hours to form crystal defect nuclei due to oxygen precipitates in the internal high-concentration oxygen introduction region, and then a third heating is performed at 1000°C or more for several tens of minutes or more. By heating and growing crystal defect nuclei, the recrystallized Si layer 3
A surface defect-free layer 3A having a thickness of approximately 1000 mm is formed on the 0 surface, and an internal defect layer 3B is formed below the surface defect-free layer 3A.
第１図（４）において、０１イオン注入により表面無欠
陥層３八と内部欠陥層３Ｂの境界に絶縁層としてＳｉ０
２層４を形成する。In FIG. 1 (4), Si0 is formed as an insulating layer at the boundary between the surface defect-free layer 38 and the internal defect layer 3B by 01 ion implantation.
Two layers 4 are formed.
０′イオン注入条件は、エネルギ６０ＫｅＶ 、ドーズ
量ｌＸｌ０”ｃｍ−２、アニール窒素中１０００℃以上
である。The 0' ion implantation conditions are an energy of 60 KeV, a dose of 1X10'' cm-2, and annealing temperature of 1000 DEG C. or higher in nitrogen.
第１図（５）において、通常の工程を用いて表面無欠陥
層３Ａにソース、ドレイン領域Ｓ、Ｄを形成し、ゲート
絶縁層５を介してゲート電極Ｇを形成する。In FIG. 1(5), source and drain regions S and D are formed in the surface defect-free layer 3A using a normal process, and a gate electrode G is formed via the gate insulating layer 5.
第２図（１１〜（５）は第２の発明による半導体素子の
形成工程を説明する断面図である。FIGS. 2(11-5) are cross-sectional views illustrating the steps of forming a semiconductor element according to the second invention.
第２図（１）において、１は基板でＳｉ基板、この上に
絶縁層としてＳｉＯ□層２、再結晶半導体層として厚さ
４０００人の再結晶Ｓｉ層３を形成する。In FIG. 2(1), reference numeral 1 denotes a Si substrate, on which a SiO□ layer 2 is formed as an insulating layer, and a recrystallized Si layer 3 with a thickness of 4000 nm is formed as a recrystallized semiconductor layer.
第２図（２）において、酸素イオンθ′″を再結晶Ｓｉ
層３に注入し、再結晶Ｓｔ層３の内部に酸素濃度が１０
Ｉ８０Ｉｆｉ−３程度の高濃度酸素導入領域３Ｂ’を形
成する。In Fig. 2 (2), oxygen ions θ''' are recrystallized into Si
The oxygen concentration inside the recrystallized St layer 3 is 10
A high concentration oxygen introduction region 3B' of about I80Ifi-3 is formed.
０′イオン注入条件は、エネルギ１６０Ｋｅν、ドーズ
量５Ｘ１０”ｃｍ−２である。The 0' ion implantation conditions are an energy of 160 Keν and a dose of 5.times.10" cm.sup.-2.
第２図（３）において、
６００℃程度で数時間第１の加熱を行い、内部の高濃度
酸素導入領域に酸素の析出物による結晶欠陥核を形成さ
せ、
つぎに、１０００℃以上で数１０分以上第２の加熱を行
い結晶欠陥核を成長させることにより、再結晶Ｓｉ層３
の表面に厚さ約１０００人の表面無欠陥層３＾、その下
側に内部欠陥層３Ｂを形成する。In Fig. 2 (3), first heating is performed at about 600°C for several hours to form crystal defect nuclei due to oxygen precipitates in the internal high-concentration oxygen introduced region, and then heated at 1000°C or higher for several tens of hours. The recrystallized Si layer 3
A surface defect-free layer 3^ with a thickness of about 1000 layers is formed on the surface of the substrate, and an internal defect layer 3B is formed below the surface defect-free layer 3^.
第２図（４）において、０′イオン注入により表面無欠
陥層３Ａと内部欠陥層３Ｂの境界に絶縁層としてＳｉ０
２層４を形成する。In FIG. 2 (4), Si0 is formed as an insulating layer at the boundary between the surface defect-free layer 3A and the internal defect layer 3B by 0' ion implantation.
Two layers 4 are formed.
０′イオン注入条件は、第１図（４）の場合と同様であ
る。The 0' ion implantation conditions are the same as in the case of FIG. 1(4).
第２図（５）において、通常の工程を用いて表面無欠陥
層３Ａにソース、ドレイン領域Ｓ、Ｄを形成し、ゲート
絶縁層５を介してゲート電極Ｇを形成する。In FIG. 2(5), source and drain regions S and D are formed in the surface defect-free layer 3A using a normal process, and a gate electrode G is formed via the gate insulating layer 5.
第３図は本発明による２層構造の素子の断面図である。FIG. 3 is a cross-sectional view of a two-layer structure element according to the present invention.
図は第１図（５）、または第２図（５）のＳｉ基板の代
わりに、素子が形成された基板を用い、その上に本発明
を適用したものである。In the figure, a substrate on which elements are formed is used instead of the Si substrate in FIG. 1 (5) or FIG. 2 (5), and the present invention is applied thereon.
図において、３１はＳｉ基板、３２はフィールド絶縁層
、３３はゲート毎色縁層である。In the figure, 31 is a Si substrate, 32 is a field insulating layer, and 33 is a gate color edge layer.
Ｇ′、Ｓ′、Ｄ′はそれぞれゲート電極、ソース領域、
ドレイン領域で基板３１に通常の素子が形成され、この
上にＳｉＯ□層２を被着し、再結晶Ｓｉ層３を形成後、
第１図、または第２図によりＳＯＩデバイスを形成する
。G', S', and D' are the gate electrode, source region, and
A conventional element is formed on the substrate 31 in the drain region, and after depositing the SiO□ layer 2 and forming the recrystallized Si layer 3,
An SOI device is formed according to FIG. 1 or FIG. 2.
以上詳細に説明したように本発明によるＳＯＩ膜は結晶
欠陥数が低減して、小数キャリアのライフタイムが大き
くなり、リーク電流の減少等デバイスの特性が向上する
。As described above in detail, the SOI film according to the present invention has a reduced number of crystal defects, a longer lifetime of minority carriers, and improved device characteristics such as reduced leakage current.
第１図（１）〜（５）は第１の発明による半導体素子の
形成工程を説明する断面図、
第２図（Ｌｉ−（５）は第２の発明による半導体素子の
形成工程を説明する断面図、
第３図は本発明による２層構造の素子の断面図である。
図おいて、
１は基板でＳｉ基板、
２は絶縁層でＳｉＯ□層、
３は再結晶半導体−で再結晶Ｓｉ膚、
３Ａは表面無欠陥層、
３Ｂは内部欠陥層、
３Ｂ’は高濃度酸素導入領域、
４は境界絶縁層で５ｉ０２層、
５はゲート絶縁層、
Ｇはゲート電極
ＳＸＤはソース、ドレイン領域
間ケち１ の オ帯ζ日Ｙ１ σ） −１１面 ＬンΔ
垢１図
躬２／）亀甲／１１面口
第２図
本春ａ月１による２層素子の
ｗｒＩ品図
垢う図Figures 1 (1) to (5) are cross-sectional views explaining the process of forming a semiconductor element according to the first invention; Figure 2 (Li-(5)) is a cross-sectional view explaining the process of forming a semiconductor element according to the second invention. 3 is a cross-sectional view of a device with a two-layer structure according to the present invention. In the figure, 1 is a substrate, which is a Si substrate, 2 is an insulating layer, which is an SiO□ layer, and 3 is a recrystallized semiconductor. Si layer, 3A is a surface defect-free layer, 3B is an internal defect layer, 3B' is a high concentration oxygen introduced region, 4 is a boundary insulating layer, 5i02 layer, 5 is a gate insulating layer, G is a gate electrode, SXD is a source and drain region Interval 1 O band ζ day Y1 σ) -11 plane Ln Δ
Figure 1 Figure 2/) Tortoise shell/11 sides Figure 2 Figure 2 of the two-layer element according to Honharu August 1
Claims (4)
導体層に酸素を導入し、第１の加熱により該再結晶半導
体層の表面層の酸素濃度を低減し、該第１の加熱より低
温で行う第２の加熱により該再結晶半導体層の内部の高
酸素濃度領域に結晶欠陥核を生成させ、該第２の加熱よ
り高温で行う第３の加熱により該結晶欠陥核を成長させ
、該再結晶半導体層の表面層に無欠陥層を形成し、該無
欠陥層に素子を形成してなることを特徴とする半導体装
置。(1) A recrystallized semiconductor layer is formed on the insulating layer, oxygen is introduced into the recrystallized semiconductor layer, and the oxygen concentration in the surface layer of the recrystallized semiconductor layer is reduced by first heating. A second heating performed at a lower temperature than the heating generates crystal defect nuclei in a high oxygen concentration region inside the recrystallized semiconductor layer, and a third heating performed at a higher temperature than the second heating causes the crystal defect nuclei to grow. A semiconductor device comprising: forming a defect-free layer on a surface layer of the recrystallized semiconductor layer; and forming an element on the defect-free layer.
導体層の表面層を除いて該再結晶半導体層の内部に酸素
導入領域を形成し、第１の加熱により該酸素導入領域に
結晶欠陥核を生成させ、該第１の加熱より高温で行う第
２の加熱により該結晶欠陥核を成長させ、該再結晶半導
体層の表面層に無欠陥層を形成し、該無欠陥層に素子を
形成してなることを特徴とする半導体装置。(2) Forming a recrystallized semiconductor layer on the insulating layer, forming an oxygen introduction region inside the recrystallization semiconductor layer except for the surface layer of the recrystallization semiconductor layer, and heating the oxygen introduction region by first heating. to generate crystal defect nuclei, grow the crystal defect nuclei by second heating performed at a higher temperature than the first heating, form a defect-free layer in the surface layer of the recrystallized semiconductor layer, and form a defect-free layer in the surface layer of the recrystallized semiconductor layer. 1. A semiconductor device comprising an element formed in a semiconductor device.
形成してなることを特徴とする特許請求の範囲第１項記
載の半導体装置。(3) The semiconductor device according to claim 1, further comprising an insulating layer formed at the boundary between the defect-free layer and the oxygen-introduced region.
形成してなることを特徴とする特許請求の範囲第２項記
載の半導体装置。(4) The semiconductor device according to claim 2, further comprising an insulating layer formed at the boundary between the defect-free layer and the oxygen-introduced region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61022321A JPH0795550B2 (en) | 1986-02-04 | 1986-02-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61022321A JPH0795550B2 (en) | 1986-02-04 | 1986-02-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62179731A true JPS62179731A (en) | 1987-08-06 |
| JPH0795550B2 JPH0795550B2 (en) | 1995-10-11 |
Family
ID=12079457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61022321A Expired - Fee Related JPH0795550B2 (en) | 1986-02-04 | 1986-02-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795550B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62222627A (en) * | 1986-03-24 | 1987-09-30 | Sharp Corp | Manufacture of semiconductor device |
| JPS62287615A (en) * | 1986-06-06 | 1987-12-14 | Sony Corp | Formation of polycrystalline silicon film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860544A (en) * | 1981-10-06 | 1983-04-11 | Mitsubishi Electric Corp | Gettering method for crystal defect |
| JPS5892227A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Gettering for crystal defect |
-
1986
- 1986-02-04 JP JP61022321A patent/JPH0795550B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860544A (en) * | 1981-10-06 | 1983-04-11 | Mitsubishi Electric Corp | Gettering method for crystal defect |
| JPS5892227A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Gettering for crystal defect |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62222627A (en) * | 1986-03-24 | 1987-09-30 | Sharp Corp | Manufacture of semiconductor device |
| JPS62287615A (en) * | 1986-06-06 | 1987-12-14 | Sony Corp | Formation of polycrystalline silicon film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0795550B2 (en) | 1995-10-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |