JPH01276617A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a semiconductor element selectively in a crystallized region by executing crystal growth of an amorphous silicon layer by making use of an uninsulated region of a polycrystalline silicon layer as a seed. CONSTITUTION:A silicon oxide region 103 is formed in one part of a polycrystalline silicon layer 102 by an ion implantation method; seed regions 104 are formed selectively. An amorphous silicon layer 106 is formed on the seed regions; the amorphous silicon layer 106 is crystal-grown by making use of the seed regions (i.e. unoxidized regions in the polycrystalline silicon layer) as seeds; a semiconductor element is formed in a crystallized region 108. When the seed regions are formed by using the ion implantation method, the seed regions and the silicon oxide region can be formed nearly on a plane. As a result, a defect such as a crack or the like is not caused in the amorphous silicon layer; a problem that a polycrystalline nucleus is generated is solved. By this setup, the semiconductor element can be formed selectively in the crystallized region.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

Attempts have been made to form high-performance semiconductor elements (for example, thin film transistors, etc.) on insulating amorphous substrates such as glass and quartz, or insulating amorphous layers such as NSC. In particular, in recent years, as the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, three-dimensional ICs, etc. has increased, the realization of high-performance semiconductor devices such as those described above has been eagerly awaited. .

Thin film transistor (“r” FT) on insulating amorphous material
) For example, (1) Plasma CVD
TPT using amorphous silicon as element material by method etc., (2
)TP using polycrystalline silicon as element material by CVD method etc.
T has been applied to liquid crystal panels, etc., and put into practical use. However, the field effect mobility of these TPTs is
Compared to MOS transistors using single-crystal silicon as the element material, it is significantly lower (amorphous silicon TPT<ICIII
/V.

v, sec, polycrystalline solicon TFT ~IOJ/V.

! ; e c ), it has been difficult to realize a high-performance TPT.

Therefore, a method of solid-phase growth of polycrystalline silicon with a large grain size (approximately 1 to several tens of micrometers) has attracted attention, and research is underway. Nhin 5olid Filis, 100 (19
8B) P, 227, JJAP VOl, 25 No.
, 2 (1986) P, L121, etc.) [Problem to be solved by the invention] However, with the conventional technology, it is difficult to sufficiently control the grain size of polycrystalline silicon and the location where the grain boundaries exist. .

Even if polycrystalline silicon with a large grain size of about 100 μm could be formed, the TPT formed inside the crystal grain and the TP with the TPT channel region located at the grain boundary.
Since the characteristics differ greatly between TFT'''C''
The operating speed of the configured scanning circuit may be limited by the poor characteristics, the characteristics of the T'F T located at the grain boundary, or in the worst case, serious problems may occur, such as the circuit not operating. .

Therefore, an object of the present invention is to form a seed region and selectively grow crystals in an amorphous layer in order to control the positions where crystal grain boundaries exist. Can now be formed selectively.

[Means for solving Section U]

The method for manufacturing a semiconductor device of the present invention includes a first step of forming a polycrystalline silicon layer on an insulating wire amorphous material, a second step of forming an insulating region in a part of the polycrystalline silicon layer, and a second step of forming an insulating region on a part of the polycrystalline silicon layer. a third step of laminating a crystalline silicon layer; a fourth step of crystal-growing the amorphous silicon layer using the uninsulated region of the polycrystalline silicon layer as a seed; and a fourth step of forming a semiconductor element in the crystallized region. It is characterized by having at least five steps.

〔Example〕

1 and 2 are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention, with FIG. 1 showing a cross-sectional view and FIG. 2 showing a plan view. In this example, TPT is used as the semiconductor element.
' (thin film transistor) is taken as an example.

In FIGS. 1 and 2, (a) is a step of forming a polycrystalline silicon layer 102 on an insulating amorphous substrate such as glass or fluorite, or an insulating amorphous material 101 such as NSC. It is. (b) is a step in which a silicon oxide region 103 is formed in a part of the polycrystalline silicon layer by the ion 7+ method, and a seed region 104 is selectively formed. (C
) is a step of forming an amorphous silicon layer 106 on the silicon oxide region and the seed region. In this embodiment, the groove 107 is formed in the amorphous silicon layer after the amorphous silicon layer 106 is formed. (d
) is a step of growing crystals of the amorphous silicon layer using a seed region (that is, an unoxidized region of the polycrystalline silicon layer) as a seed.

(e) is a step of forming a semiconductor element in the crystallized region 108. In addition, in FIG. 1(e), 109 is a gate electrode, 110 is a source electrode, and in FIG.
A drain region, 111 an interlayer insulating film, 112 a contact hole, 113 a wiring, and 114 a gate insulating film.

Next, the manufacturing conditions and technical points of each process will be described.

Step (a) is a step of forming a polycrystalline silicon layer 102 on an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer 101 such as NSC.Features of the present invention One is to use a part of the polycrystalline silicon layer as a seed region, and make the rest into a silicon oxide region by ion implantation,
The point is that crystal growth is performed. Therefore, the crystal grain size and orientation of the polycrystalline silicon are important parameters. That is, the larger the crystal grain size of polycrystalline silicon and the better its orientation, the more similar crystal growth will be achieved when single crystal silicon is used as a seed. As a method for forming polycrystalline silicon, there is a method of forming a polycrystalline silicon film using a CVD method or the like. This method is the most common film formation method,
In terms of forming polycrystalline silicon using a simple method, (1) A method of forming amorphous silicon by a method such as a plasma CVD method, an evaporation method, an EB evaporation method, an MB method, a CVD method, a sputtering method, etc., and polycrystallizing it by heat treatment at about 500 to 700°C, etc. (2) ) After forming microcrystalline silicon, polycrystalline silicon, etc. by plasma CVD method, CVD method, vapor deposition method, MBE method, EB vapor deposition method, sputtering method, etc., St, Ar, B, P
A method of ion-implanting elements such as , N, He, Ne, Kr, H, etc. to make the microcrystalline silicon, polycrystalline silicon, etc. amorphous, and then polycrystallizing it by heat treatment at about 500 to 700 ° C. There is. Polycrystalline silicon formed by these methods has a good orientation and a large crystal grain size of about 1 μTn to several tens of μrn or more, and therefore is effective as a method for forming a polycrystalline silicon layer. Among them, vapor deposition method, EB vapor deposition method,
Amorphous silicon formed by MBE method etc. is heated to 500°C to 60°C.
Polycrystalline silicon obtained by heat treatment at about 0°C can have a grain size of several tens of μm or more, and
Since the crystal orientation is also good, this method is particularly effective as a method for forming a polycrystalline silicon layer. Further, impurities (for example, P
) to shorten the time required for polycrystallization (
It is possible to reduce the amount by a maximum of about 1/10). moreover,
The above method is also effective in increasing crystal grain size. In addition, since a silicon oxide region is formed in a portion other than the seed region in the next step (b), the profile of impurities added to the amorphous silicon layer is low near the surface of the amorphous silicon layer.
It is desirable to dope the region closer to the amorphous material layer 101 (for example, the quartz substrate) so that the doping becomes higher. easily realized.

Step (b) is a step of forming a silicon oxide region 103 in a part of the polycrystalline silicon layer by ion implantation, and selectively forming a seed region 104. First, a mask 105 (for example, a mask material such as resist, metal, silicon oxide, silicon nitride, polycrystalline silicon, etc.) is applied to the portion of the polycrystalline silicon layer 102 formed in step (a) that will become the seed region. ) can be formed. Subsequently, oxygen ions are implanted by an ion implantation method to form a silicon oxide region 103 in a region other than the seed region 104 covered with a mask. In this case, polycrystalline silicon layer 1
It is desirable that a silicon oxide layer having a composition close to the stoichiometric SiO□ is formed near the surface of the silicon oxide layer. Dose amount 1
017~10"ion s/cl, acceleration voltage 20
~80 K e V or so is desirable. In particular, doping amount 1
0” ~1019i ons/-1 acceleration voltage 25~40
Upon dyeing with KeV, good quality SiO2 was formed from the surface to a depth of several hundred nm. Furthermore, after ion implantation,
When annealing is performed at 800° C. to 1200° C. for 1 to 3 hours in an atmosphere of nitrogen or the like, a silicon oxide layer having characteristics close to those of thermal oxidation 5 in 2 can be obtained. In addition, if a low melting point material such as glass is used as the substrate, instead of the above-mentioned annealing, the substrate after ion implantation can be subjected to oxygen plasma treatment at a lower temperature of about 250°C to 700°C. In particular, silicon oxide near the surface is thermally oxidized S i O2
A method of modifying silicon oxide to have properties similar to those of silicon oxide is also extremely effective. There is also a method of forming a silicon oxide region only by oxygen plasma treatment.

Step (c) is a step of forming an amorphous silicon layer 106 in the silicon oxide region 103 and seed region 104-L after removing the mask 105.

The amorphous silicon layer is formed by plasma CVD method, vapor deposition method, E
A method of forming amorphous silicon into a film by methods such as B evaporation method, MBE method, sputtering method, CVD method, etc., and a method of forming microcrystalline silicon, polycrystalline silicon, etc. by plasma CVD method, CVD method, evaporation method, EB evaporation method, After forming the microcrystalline silicon, polycrystalline silicon, etc. by a method such as the MBE method or the scattering method, the microcrystalline silicon, polycrystalline silicon, etc. There is a method of forming an amorphous silicon layer by crystallization or the like. In this embodiment, a case where the amorphous silicon layer 106 is formed with 107 layers is taken as an example.

Step (d) is a seed region 10 not formed in step (b).
4 as a seed, the amorphous silicon layer 106 is grown as a crystal. The crystal can be grown by a melt recrystallization method such as a linear heating zone melt recrystallization method, a laser beam recrystallization method, or an electron beam recrystallization method. As the method, there is a solid phase growth method in which crystals are grown in a solid phase without melting the amorphous layer.

This method has the characteristic that crystal growth is performed at a low temperature of about 500°C to 700°C, and has excellent advantages such as using an inexpensive glass substrate as a substrate and easily increasing the size of the substrate. There is.

The annealing conditions in the above-mentioned solid phase growth method vary depending on the method of forming the amorphous silicon layer 106.

A suitable value for the heat treatment temperature exists between 500°C and 900°C. However, as the heat treatment temperature increases, the time required for crystallization becomes shorter, but nucleation and crystal growth become more likely to occur in regions other than the seed region. As a result, the amorphous layer tends to grow into random polycrystalline silicon. Therefore, the heat treatment temperature is preferably about 500° C. to 700° C. since polycrystalline nuclei are less likely to occur. Furthermore, the time required for heat treatment (that is, the time required for crystallization) differs depending on the method of forming the amorphous silicon layer 106 even at the same heat treatment temperature. For example, amorphous silicon formed by plasma CVD (especially amorphous silicon formed at a substrate temperature of about 350°C or lower) is difficult to crystallize when heat treated at about 600°C; Heat treatment time of 10 hours or more is required at high temperature, and nucleation and crystal growth are likely to occur from areas other than the seed region.Also, even in amorphous silicon formed by plasma CVD, the substrate temperature is 450°C to 600°C.
Unlike the amorphous silicon described above, a film formed at a high temperature of about 600°C undergoes crystal growth by heat treatment at about 600°C, and selective crystal growth from the seed region is likely to occur.
Amorphous silicon formed at temperatures below about 350°C using the plasma CVD method contains a few percent to several percent of hydrogen in the film, and these hydrogens are completely removed by annealing at about 600°C. Since there is no residual hydrogen, it is thought that the remaining hydrogen hinders crystal growth. On the other hand, even when the substrate temperature is 450°C to 600°C, a film formed at a high temperature of about 500°C to 550°C is
600 because it is amorphous and the amount of hydrogen in the film is extremely small.
It is thought that crystal growth is likely to occur even with annealing at a temperature of around 10°C. Furthermore, when the amorphous silicon layer 106 is formed by a vapor deposition method, an EB vapor deposition method, an MBE method, etc.,
Crystal growth can occur by annealing at a relatively low temperature of about 600° C., and the time required for crystal growth can be shortened to about several hours. The above-mentioned method has the advantage that amorphous silicon containing no hydrogen or impurities can be formed by increasing the degree of vacuum during vapor deposition, preferably about 10-6 to 10-8 Pa).

In addition, in the solid phase growth method described above, the solid phase growth distance is at most 1
It is short, about 0 μm. An effective method for reducing this growth distance is to dope an impurity such as P in an amount of about 10+9 to 102'1-3 into a region of the amorphous silicon layer 106 where no element will be formed.

In this case, the growth distance of solid phase growth is 20 μm to 30 μm.
Expand to a certain degree.

Finally, the advantages of forming the seed region 104 by ion implantation as in the present invention will be described.

In the method of forming a silicon seed region on an amorphous material and crystal-growing the amorphous silicon layer stacked thereon, the simplest method for forming the seed region is to form a silicon seed region on the amorphous material (for example, a quartz substrate). There is a method in which a polycrystalline silicon layer is formed on a glass substrate, a glass substrate, an NSC, etc.), and the polycrystalline silicon layer is patterned to form silicon islands. In this case, the amorphous silicon layer laminated on the silicon island needs to cover the step caused by the silicon island, and there is a problem in that defects such as cracks are likely to occur in the step.

Also, during crystal growth by heat treatment, there is a problem in that polycrystalline nuclei are likely to be generated at the stepped portions, and polycrystals rather than single crystals are likely to grow on one silicon island (seed). .

On the other hand, in the method of forming a seed region using ion implantation according to the present invention, there is no large step difference between the seed region and the silicon oxide region, and the amount of oxygen ions implanted and the implanted region (for example, from the surface to It is also possible to form the seed region and the silicon oxide region almost on a flat surface by implanting the seed region and the silicon oxide region on a substantially flat surface.As a result, it is possible to prevent cracks, etc. This also eliminates the occurrence of defects, and also solves the problem of polycrystalline nucleation during crystal growth due to heat treatment.

Step (e) is a step of forming a semiconductor element in the crystallized region 108. The position of the crystallized region 108 can be controlled by the groove 107 provided in the amorphous silicon layer 106.

In this embodiment, TP is used as a semiconductor element in this region 108.
The case of forming a T is taken as an example. As an example of a TPT forming method, a crystallized silicon layer is patterned, and then a gate insulating film 114 is formed.

The gate insulating film is formed by a thermal oxidation method (high temperature process), a CVD method, a plasma CVD method, etc.
Low temperature below 00°C (preferably below 500°C)
In low-temperature processes, inexpensive glass substrates can be used as substrates, making it possible to manufacture semiconductor devices such as large liquid crystal display panel-contact image sensors at low cost. Even in the case of forming a semiconductor element in the upper layer, the semiconductor element can be formed in the upper layer without adversely affecting the element in the lower layer (for example, diffusion of impurities, etc.). Subsequently, after forming the gate electrode 109,
The source/drain region 110 is formed by a method such as an ion implantation method, a thermal diffusion method, or a plasma doping method, and the interlayer insulating film 111 is formed by a method such as a CVD method, a sputtering method, or a plasma CVD method. Furthermore, a contact hole 112 is opened in the interlayer insulating film 111 and a wiring 113 is formed, thereby forming a TPT.

Next, the characteristics of the TPT manufactured by the method of manufacturing a semiconductor device based on the present invention will be described. The field effect mobility of the N-channel TPT manufactured by the manufacturing method of the present invention is 3
It became about 00 to 500 dl/V, secC. This characteristic is good and close to the characteristic of a MOS transistor formed on a silicon wafer. Furthermore, T.P.T.
In TPT where the thickness of the silicon layer in the channel region of
700-900-/V, which is better than OS transistors.
It is not possible to obtain a mobility close to that of bulk Si on the order of sec. The manufacturing method of the present invention is suitable for crystal growth of a thin amorphous silicon layer (because there are no steps and defects such as cracks are less likely to occur in the amorphous layer), and the manufacturing method is suitable for growing a thin amorphous silicon layer. The present invention is particularly excellent as a method for manufacturing thin TPT.

〔Effect of the invention〕

As described above, according to the present invention, it has become possible to selectively grow crystals in an amorphous silicon layer using a seed region and to control the positions where crystal grain boundaries exist. As a result, it has become possible to selectively form semiconductor elements in crystallized regions.

According to the present invention, MO formed on a silicon wafer
TPTs and the like with high performance similar to (and in some cases, exceeding) those of S transistors have been realized.

As a result, not only a large, high-resolution liquid crystal display panel and a high-speed, high-resolution contact image sensor have been realized, but if we take the contact image sensor as an example, the conventional type has a scanning circuit formed of TPT. However, according to the present invention, in addition to the scanning circuit, it is also possible to integrate an IJ circuit, an arithmetic circuit, a memory circuit, etc. in addition to the scanning circuit. can.

In addition, when forming a MOS type semiconductor element such as TPT, the gate insulating film is formed using the CVD method or the thermal oxidation method.
If formed by a low-temperature process such as plasma CVD, an inexpensive glass substrate or the like can be used as the substrate, and semiconductor devices such as large liquid crystal display panels and contact image sensors can be manufactured at low cost. In addition, since it does not go through a high-temperature process, there is very little warping or deformation of the substrate, which is a problem especially with large substrates.In addition, even when forming three-dimensional ICs, it may be harmful to the underlying elements (for example, impurities). It is also possible to form a semiconductor element in the upper layer without applying any diffusion (diffusion, etc.).

In the embodiments of the present invention, TPT is used as the semiconductor element, but in addition to TPT, MIS type F E
Needless to say, the present invention can be applied to semiconductor devices in general, including transistors, bipolar transistors, and static induction transistors.

Further, in the embodiments of the present invention, a case has been described in which a silicon oxide region is formed by ion implantation, but the invention is not limited to this. Silicon nitride, a silicon layer containing oxygen and nitrogen (SiOxN
Any insulating layer such as y) may be used.

[Brief explanation of the drawing]

FIGS. 1(a)-(e) and FIGS. 2(a)-(e) are process diagrams for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a cross-sectional view, and FIG. 2 shows a plan view. 101... Insulating amorphous material 102... Polycrystalline silicon layer 103... Silicon oxide region 104... Seed region 105... Mask 106... Amorphous silicon layer 108... Crystal Activated region 109...Gate electrode 110...Source/drain region 111...Interlayer insulating film 113...Wiring 114...Gate insulating film and above Applicant Seiko Epson Corporation Agent Patent attorney Kamiyanagi Masa Homare (1 other person) (b) Figure 1 (d) Figure 1 XXXXXXX XXXXXXX XXXXX (b) Figure 2 (d) Figure 2

Claims (2)

[Claims] (1) A first step of forming a polycrystalline silicon layer on an insulating amorphous material, a second step of forming an insulating region on a part of the polycrystalline silicon layer, and laminating an amorphous silicon layer. A third step, a fourth step of growing crystals of the amorphous silicon layer using an uninsulated region of the polycrystalline silicon layer as a seed, and a fifth step of forming a semiconductor element in the crystallized region. A method for manufacturing a semiconductor device, characterized by: (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that the insulating region is formed by ion implantation.