JPS6210033B2 - - Google Patents
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- Publication number
- JPS6210033B2 JPS6210033B2 JP53020654A JP2065478A JPS6210033B2 JP S6210033 B2 JPS6210033 B2 JP S6210033B2 JP 53020654 A JP53020654 A JP 53020654A JP 2065478 A JP2065478 A JP 2065478A JP S6210033 B2 JPS6210033 B2 JP S6210033B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- mis type
- semiconductor
- electron beam
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 93
- 238000010894 electron beam technology Methods 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 230000005669 field effect Effects 0.000 description 25
- 239000000758 substrate Substances 0.000 description 17
- 239000010410 layer Substances 0.000 description 13
- 230000001678 irradiating effect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005524 hole trap Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、MIS型半導体素子を具備する半導体
集積回路装置の製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device including an MIS type semiconductor element.
MIS型半導体素子を具備する半導体集積回路装
置において、そのMIS型半導体素子の閾値電圧
は、そのMIS型半導体素子を構成している半導体
領域の不純物濃度、MIS型半導体素子を構成して
いる絶縁膜の厚さ、MIS型半導体素子を構成して
いる絶縁膜中に残留している電荷などをパラメー
タとして決められる。 In a semiconductor integrated circuit device equipped with an MIS type semiconductor element, the threshold voltage of the MIS type semiconductor element is determined by the impurity concentration of the semiconductor region constituting the MIS type semiconductor element, and the insulating film constituting the MIS type semiconductor element. It can be determined using parameters such as the thickness of the MIS semiconductor device and the charge remaining in the insulating film that makes up the MIS semiconductor device.
従来の半導体集積回路装置においては、その
MIS型半導体素子の閾値電圧が、そのMIS型半導
体素子を構成している半導体領域の不純物濃度を
パラメータとして決められているか、またはMIS
型半導体素子を構成している絶縁膜の厚さをパラ
メータとして決められているのを普通としてい
た。 In conventional semiconductor integrated circuit devices,
Is the threshold voltage of an MIS semiconductor device determined using the impurity concentration of the semiconductor region that makes up the MIS semiconductor device as a parameter?
The thickness of the insulating film constituting the type semiconductor device was normally determined as a parameter.
従つて、従来のMIS型半導体素子を有する半導
体集積回路装置の製法は、半導体領域の不純物濃
度の制御により、所望の閾値電圧を有するMIS型
半導体素子を形成する、という方法であるか、ま
たは絶縁膜の厚さの制御により、所望の閾値電圧
を有するMIS型半導体素子を形成するという方法
であるのを普通としていた。 Therefore, the conventional method for manufacturing a semiconductor integrated circuit device having an MIS type semiconductor element is to form a MIS type semiconductor element having a desired threshold voltage by controlling the impurity concentration of the semiconductor region, or to form an MIS type semiconductor element having a desired threshold voltage. The conventional method was to form an MIS type semiconductor device having a desired threshold voltage by controlling the thickness of the film.
しかしながら、このような従来の半導体集積回
路装置の製法の場合、多くのMIS型半導体素子
を、それら中のMIS型半導体素子については、他
のあるMIS型半導体素子とは異なる閾値電圧を有
するものとして形成する場合、多くのフオトマス
クを用いた工程を必要し、従つて、半導体集積回
路装置を、簡易に、しかも歩留り良く製造するこ
とができるものとは云い得ないものであつた。 However, in the case of such a conventional manufacturing method of a semiconductor integrated circuit device, many MIS type semiconductor elements are processed as having threshold voltages different from those of other MIS type semiconductor elements. In the case of formation, a process using many photomasks is required, and therefore, it cannot be said that a semiconductor integrated circuit device can be easily manufactured with a high yield.
よつて、本発明者などは、第１図に示すよう
な、半導体基板１内に、その主面側から、半導体
基板１側とは逆の導電型を有する半導体領域２及
び３がそれぞれソース領域及びドレイン領域とし
て形成され、また、半導体基板１の主面上に、絶
縁膜４がゲート絶縁膜として形成され、さらに、
この絶縁膜４上の、半導体領域２及び３間領域に
対応している領域に、導電性層５が、ゲート電極
として付されている構成を有する（なお、第１図
において、６は素子間分離用絶縁膜、７は絶縁膜
４及び絶縁膜６上に導電性層５を埋設して延長し
ている層間絶縁膜、８及び９はそれぞれ半導体領
域２及び３に連結して層間絶縁膜７上に延長して
いるソース電極乃至配線層及びドレイン電極乃至
配線層としての導電性層を示す）MIS型電界効果
半導体素子をMIS型半導体素子として具備する半
導体集積回路装置を製造するにつき、種々の実験
を行なつた結果、MIS型電界効果半導体素子の絶
縁膜４に、電子線を照射すれば、その絶縁膜４中
にホールトラツプが形成され、そのホールトラツ
プに、電子線の照射に基づき発生するエレクトロ
ン・ホール対中のホールがトラツプされ、このた
め、絶縁膜４中に、正の電荷が発生し、それが残
留すること、しかしながら、絶縁膜４への電子線
の照射によつてその絶縁膜４に電荷を発生せしめ
た場合、これと同時に、半導体基板１と絶縁膜４
との間の界面に、界面準位が発生し、それが残留
する、ということを確認するに到つた。 Therefore, the present inventors have proposed that semiconductor regions 2 and 3 having a conductivity type opposite to that of the semiconductor substrate 1 are formed as source regions in a semiconductor substrate 1 from the main surface side, as shown in FIG. and a drain region, an insulating film 4 is formed as a gate insulating film on the main surface of the semiconductor substrate 1, and further,
A conductive layer 5 is provided as a gate electrode in a region on this insulating film 4 corresponding to the region between the semiconductor regions 2 and 3 (in FIG. An isolation insulating film 7 is an interlayer insulating film extending by embedding a conductive layer 5 on the insulating film 4 and the insulating film 6, and 8 and 9 are interlayer insulating films 7 connected to the semiconductor regions 2 and 3, respectively. In manufacturing a semiconductor integrated circuit device having an MIS type field effect semiconductor element as an MIS type semiconductor element (showing a conductive layer as a source electrode or wiring layer extending upwardly and a conductive layer as a drain electrode or wiring layer), there are various steps. As a result of experiments, it was found that when the insulating film 4 of a MIS type field effect semiconductor device is irradiated with an electron beam, a hole trap is formed in the insulating film 4, and the electrons generated due to the electron beam irradiation are formed in the hole trap. - The hole in the hole pair is trapped, and therefore a positive charge is generated in the insulating film 4, and this remains. However, when the insulating film 4 is irradiated with an electron beam, the insulating film 4 is When a charge is generated in the semiconductor substrate 1 and the insulating film 4, at the same time
We have now confirmed that an interface state is generated and remains at the interface between the two.
また、本発明者などは、絶縁膜４への電子線の
照射によつてその絶縁膜４に発生して残留する電
荷は、MIS型電界効果半導体素子の閾値電圧を決
定するパラメータにはなるが、それ以外のMIS型
電界効果半導体素子の特性に影響を及ぼすパラメ
ータにはならないこと、しかしながら、絶縁膜４
への電子線の照射によつて半導体基板１と絶縁膜
４との間の界面に発生して残留する界面準位は、
半導体基板１の表面におけるキヤリアの移動度を
低下させたり、半導体領域２及び３間のリーク電
流を増加させたりするので、MIS型電界効果半導
体素子の特性に悪影響を及ぼすパラメータとなる
ことも確認するに到つた。 In addition, the present inventors have discovered that the residual charge generated in the insulating film 4 by irradiation of the insulating film 4 with an electron beam is a parameter that determines the threshold voltage of the MIS type field effect semiconductor device. However, the insulating film 4 should not be a parameter that affects the characteristics of other MIS type field effect semiconductor devices.
The interface states generated and remaining at the interface between the semiconductor substrate 1 and the insulating film 4 due to electron beam irradiation are as follows:
It is also confirmed that this is a parameter that adversely affects the characteristics of the MIS type field effect semiconductor device because it reduces the carrier mobility on the surface of the semiconductor substrate 1 and increases the leakage current between the semiconductor regions 2 and 3. I reached it.
さらに、本発明者などは、上述した絶縁膜４へ
の電子線の照射によつてその絶縁膜４に発生して
残留する電荷、及び半導体基板１を絶縁膜４との
間の界面に発生して残留する界面準位は、熱処理
によつて消滅させることができるが、その消滅率
が、絶縁膜４に発生して残留する電荷と、半導体
基板１と絶縁膜４との間の界面に発生して残留す
る界面準位とでは、後者が、前者に比し十分大な
る関係で、互に異なることも確認する到つた。 Furthermore, the present inventors have discovered that electric charges generated and remaining in the insulating film 4 due to the irradiation of the electron beam to the insulating film 4 described above, and charges generated at the interface between the semiconductor substrate 1 and the insulating film 4. The remaining interface states can be annihilated by heat treatment, but the rate of annihilation depends on the charge generated and remaining in the insulating film 4 and the interface state between the semiconductor substrate 1 and the insulating film 4. We have also confirmed that the latter differs from the remaining interface states in a sufficiently larger relationship than the former.
このことは、第１図に示すMIS型電界効果半導
体素子が、その半導体基板１をして、ボロンを
1016atom／cm3の量ドープしているＰ型シリコン基
板（その主面は＜100＞）でなり、また、半導体
領域２及び３をして、半導体基板１内にその主面
側から0.25μｍの深さに砒素のイオンが打込まれ
て得られたＮ型半導体領域でなり、さらに、絶縁
膜４をして、500Åの厚さを有するシリコン酸化
膜でなり、また、導電性層５をして、3000Åの厚
さを有し且つ砒素をドープしている多結晶シリコ
ンでなる（なお、絶縁層６をして、約0.7μｍの
厚さを有するシリコン酸化層でなり、また、層間
絶縁膜７をして、5000Åの厚さを有し且つ燐を僅
かに添加しているシリコン酸化膜でなり、さら
に、導電性層８及び９をして、6000Åの厚さを有
し且つモリブデンでなる導電性層でなる）、とい
う具体的構成を有する場合において、その絶縁膜
４に、20KVの加速電圧を有する電子線を、２×
10-3クーロン／cm2の量照射し、次に熱処理を行な
つたときの、その熱処理温度Ｔ（℃）で対するフ
ラツトバンド電圧の変化量Ｖ（ボルト）を測定し
たところ、第２図に示すように、熱処理温度Ｔを
450℃にしても、フラツトバンド電圧の変化Ｖが
約1.5ボルトしか変化しないことが明らかになつ
た。なお、このような約1.5ボルトのフラツトバ
ンド電圧の変化量の場合、絶縁膜４には、電荷が
6.5×1011個／cm2の量残留している。 This means that the MIS type field effect semiconductor device shown in FIG. 1 uses boron as its semiconductor substrate 1.
It consists of a P-type silicon substrate doped with an amount of 10 16 atoms/cm 3 (its main surface is <100>), and semiconductor regions 2 and 3 are formed in the semiconductor substrate 1 by 0.25% from the main surface side. It is an N-type semiconductor region obtained by implanting arsenic ions to a depth of μm, and an insulating film 4 is made of a silicon oxide film having a thickness of 500 Å, and a conductive layer 5 is formed. The insulating layer 6 is made of polycrystalline silicon doped with arsenic and has a thickness of 3000 Å. The insulating film 7 is a silicon oxide film having a thickness of 5000 Å and is slightly doped with phosphorus, and the conductive layers 8 and 9 are made of molybdenum and having a thickness of 6000 Å. ), the insulating film 4 is irradiated with an electron beam having an acceleration voltage of 20 KV at 2×
When irradiating at a dose of 10 -3 coulombs/cm 2 and then performing heat treatment, we measured the change in flat band voltage V (volts) at the heat treatment temperature T (°C), as shown in Figure 2. The heat treatment temperature T is
It was revealed that even at 450°C, the flat band voltage change V only changes by about 1.5 volts. In addition, in the case of such a change in flat band voltage of about 1.5 volts, the insulating film 4 has no charge.
An amount of 6.5×10 11 pieces/cm 2 remains.
また、MIS型電界効果半導体素子が、上述した
具体的構成を有する場合において、その絶縁層４
に、20KVの加速電圧を有する電子線を照射した
ときの、その電子線の照射量Ｑ（クーロン／cm2）
に対するフラツトバンド電圧の変化量Ｖ（ボル
ト）を測定したところ、第３図に示すように、照
射量Ｑが大になるのに応じて、フラツトバンド電
圧が負側に変化する態様で、フラツトバンド電圧
の変化量Ｖが変化することも明らかとなつた。 Further, in the case where the MIS type field effect semiconductor device has the above-described specific configuration, the insulating layer 4
is irradiated with an electron beam having an accelerating voltage of 20KV, the irradiation amount Q (coulombs/cm 2 ) of the electron beam is
When we measured the amount of change V (volts) in the flat band voltage for It has also become clear that the quantity V varies.
さらに、MIS型電界効果半導体素子が上述した
具体的構成を有する場合において、上述したよう
に、絶縁膜４に、20KVの加速電圧を有する電子
線を２×10-3クーロン／cm2の量照射し、次に熱処
理を行なつたときの、その熱処理温度Ｔ（℃）に
対する半導体基板１の主面上でのキヤリアの移動
度（絶縁膜４に発生する界面準位に応じた値を有
する）の回復率Ｍ（％）（絶縁膜４に発生する界
面準位が熱処理によつて消滅する、その消滅に応
じた値を有する）を測定したところ、第４図に示
すように、熱処理温度Ｔを450℃とするとき、キ
ヤリア移動度の回復率Ｍが95％となることが明ら
かとなつた。 Further, in the case where the MIS type field effect semiconductor device has the above-described specific configuration, the insulating film 4 is irradiated with an electron beam having an acceleration voltage of 20 KV at a dose of 2×10 −3 coulombs/cm 2 as described above. Then, when the next heat treatment is performed, the carrier mobility on the main surface of the semiconductor substrate 1 with respect to the heat treatment temperature T (° C.) (has a value depending on the interface state generated in the insulating film 4) When the recovery rate M (%) (the interface state generated in the insulating film 4 disappears by heat treatment, and has a value corresponding to its disappearance), as shown in FIG. 4, it was found that the heat treatment temperature T It has become clear that when the temperature is 450°C, the carrier mobility recovery rate M is 95%.
また、本発明者などは、絶縁膜４への電子線の
照射によつてその絶縁膜４に発生して残留する電
荷、及び半導体基板１と絶縁膜４との間の界面に
発生して残留する界面準位の熱処理による消滅率
が、上述したように、確認されたため、絶縁膜４
への電子線の照射を行ない、次に適当な熱処理を
行なえば、絶縁膜４への電子線の照射によつて半
導体基板１と絶縁膜４との間の界面に発生して残
留する界面準位を、MIS型電界効果半導体素子の
特性に影響を及ぼすパラメータに実質的にならな
いのに十分な程度、消滅させ得、しかしながら、
絶縁膜４への電子線の照射によつて絶縁膜４に発
生して残留する電荷を、MIS型電界効果半導体素
子の閾値電圧を決定するパラメータとなるのに十
分な量、残留させ得、よつて、MIS型電界効果半
導体素子を、半導体基板１の不純物濃度をパラメ
ータとして決められた閾値電圧を有する、または
絶縁膜の厚さをパラメータとして決められた閾値
電圧を有するMIS型電界効果半導体素子としてで
はなく、絶縁膜４への電子線の照射によつてその
絶縁膜に発生して残留する電荷をパラメータとし
て決められた閾値電圧を有するMIS型電界効果半
導体素子として製造することができることも、確
認するに到つた。 In addition, the present inventors have proposed that charges generated and remaining in the insulating film 4 due to electron beam irradiation on the insulating film 4, and charges generated and remaining at the interface between the semiconductor substrate 1 and the insulating film 4. As mentioned above, the extinction rate of the interface states due to heat treatment was confirmed, so the insulating film 4
By irradiating the insulating film 4 with an electron beam and then performing an appropriate heat treatment, the interface quasi generated and remaining at the interface between the semiconductor substrate 1 and the insulating film 4 due to the irradiation of the insulating film 4 with the electron beam can be removed. However,
The electric charge generated and remaining in the insulating film 4 by irradiating the insulating film 4 with an electron beam can be left in an amount sufficient to become a parameter for determining the threshold voltage of the MIS type field effect semiconductor device. Therefore, the MIS type field effect semiconductor device can be used as a MIS type field effect semiconductor device having a threshold voltage determined using the impurity concentration of the semiconductor substrate 1 as a parameter, or having a threshold voltage determined using the thickness of the insulating film as a parameter. It was also confirmed that it is possible to manufacture an MIS type field effect semiconductor device having a threshold voltage determined by using the charge generated and remaining in the insulating film 4 as a parameter by irradiating the insulating film 4 with an electron beam. I came to the point.
また、本発明者などは、MIS型電界効果半導体
素子を具備する半導体集積回路装置の製法におい
て、そのMIS型電界効果半導体素子を、上述した
ように、絶縁膜４への電子線の照射、続く熱処理
によつて、絶縁膜に電荷を残留させることによつ
て、その残留電荷をパラメータとして決められた
閾値電圧を有するMIS型電界効果半導体素子とし
て形成する場合、その電子線の照射は、MIS型電
界効果半導体素子の絶縁膜４のみに、局部的に、
容易に行なうことができ、また電子線の照射量も
容易に制御し得るので、半導体集積回路装置を多
数のMIS型電界効果半導体素子を具備し、そし
て、その多数のMIS型電界効果半導体素子中のあ
るMIS型電界効果半導体素子については、他のあ
るMIS型電界効果半導体素子とは異なる閾値電圧
を有するような半導体集積回路装置として製造す
る場合であつても、その半導体集積回路装置を、
MIS型電界効果半導体素子を構成する半導体領域
の不純物濃度の制御によつて、またはMIS型電界
効果半導体素子を構成する絶縁層の厚さの制御に
よつて、所望の閾値電圧を有するMIS型電界効果
半導体素子を有するものとして製造する場合に比
し、格段的に簡易に、しかも、歩留り良く製造す
ることができることも、確認するに到つた。 In addition, in a method for manufacturing a semiconductor integrated circuit device including an MIS type field effect semiconductor element, the present inventors et al. When forming an MIS type field effect semiconductor element having a threshold voltage determined using the residual electric charge as a parameter by leaving electric charge in the insulating film through heat treatment, the electron beam irradiation is applied to the MIS type field effect semiconductor element. Locally, only on the insulating film 4 of the field effect semiconductor element,
This can be easily carried out, and the amount of electron beam irradiation can also be easily controlled. Even if a certain MIS type field effect semiconductor device is manufactured as a semiconductor integrated circuit device having a threshold voltage different from that of other MIS type field effect semiconductor devices, the semiconductor integrated circuit device is
By controlling the impurity concentration of the semiconductor region constituting the MIS type field effect semiconductor device or by controlling the thickness of the insulating layer constituting the MIS type field effect semiconductor device, an MIS type electric field having a desired threshold voltage can be obtained. It has also been confirmed that it can be manufactured much more easily and with a higher yield than when manufacturing it as having an effect semiconductor element.
本発明は、以上に基づき、絶縁膜への電子線の
照射によつて絶縁膜に電荷を発生させ、次に、熱
処理によつて上記電荷は残留させるが上記電荷の
発生と同時に発生する界面準位は消滅させ、よつ
て、上記残留電荷をパラメータとして決められた
閾値電圧を有するMIS型電界効果半導体素子を形
成する、という本発明による新規な半導体集積回
路装置の製法を提案するものである。 Based on the above, the present invention generates charges in an insulating film by irradiating the insulating film with an electron beam, and then heat-treats the film to cause the charges to remain, but an interface layer is generated simultaneously with the generation of the charges. The present invention proposes a novel method for manufacturing a semiconductor integrated circuit device, in which a MIS type field effect semiconductor device having a threshold voltage determined using the residual charge as a parameter is formed.
このような、本発明による半導体集積回路装置
の製法によれば、前述したところから明らかなよ
うに、そのMIS型半導体素子の閾値電圧を決めて
いるパラメータを、絶縁膜への電子線の照射、続
く熱処理によつて絶縁膜に残留させた電荷によつ
て決めているので、多数のMIS型半導体素子を、
そのあるMIS型半導体素子については、他のある
MIS型半導体素子とは異なる閾値電圧を有するも
のとして、簡易に、しかも歩留り良く、形成する
ことができる特徴を有する。 According to the method for manufacturing a semiconductor integrated circuit device according to the present invention, as is clear from the foregoing, the parameters determining the threshold voltage of the MIS type semiconductor element can be changed by irradiating the insulating film with an electron beam, Since it is determined by the charge left in the insulating film by the subsequent heat treatment, many MIS type semiconductor devices can be
Regarding certain MIS type semiconductor devices, other
Since it has a threshold voltage different from that of an MIS type semiconductor element, it has the feature that it can be formed simply and at a high yield.
第１図は、本発明による半導体集積回路装置の
製法の説明に供する、MIS型電界効果半導体素子
の略線的断面図である。第２図は、MIS型電界効
果半導体素子の絶縁膜への電子線の照射後、熱処
理を行なつた場合の、その熱処理温度Ｔ（℃）に
対するフラツトバンド電圧の変化量Ｖ（ボルト）
の実測結果を示す図である。第３図は、MIS型電
界効果半導体素子の絶縁膜に電子線を照射した場
合の、その電子線の照射量Ｑ（クーロン／cm2）に
対するフラツトバンド電圧の変化量Ｖ（ボルト）
の実測結果を示す図である。第４図は、MIS型電
界効果半導体素子の絶縁膜への電子線の照射後、
熱処理を行なつた場合の、その熱処理温度Ｔ
（℃）に対する半導体基板の主面上でのキヤリア
の移動度の回復率Ｍ（％）の実測結果を示す図で
ある。
１……半導体基板、２，３……半導体領域、４
……絶縁膜、５……導電性層。
FIG. 1 is a schematic cross-sectional view of an MIS type field effect semiconductor element, which is used to explain a method for manufacturing a semiconductor integrated circuit device according to the present invention. Figure 2 shows the amount of change in flat band voltage V (volts) with respect to the heat treatment temperature T (°C) when heat treatment is performed after electron beam irradiation on the insulating film of a MIS type field effect semiconductor device.
FIG. 3 is a diagram showing actual measurement results. Figure 3 shows the amount of change in flat band voltage V (volts) with respect to the electron beam irradiation amount Q (coulombs/cm 2 ) when an insulating film of a MIS type field effect semiconductor device is irradiated with an electron beam.
FIG. 3 is a diagram showing actual measurement results. Figure 4 shows that after the insulating film of the MIS field effect semiconductor device is irradiated with an electron beam,
Heat treatment temperature T when heat treatment is performed
FIG. 3 is a diagram showing actual measurement results of recovery rate M (%) of carrier mobility on the main surface of a semiconductor substrate with respect to temperature (° C.). 1... Semiconductor substrate, 2, 3... Semiconductor region, 4
...Insulating film, 5... Conductive layer.
Claims (1)
装置の製法において、 上記MIS型半導体素子の絶縁膜への電子線の照
射、続く熱処理を行うことによつて、上記電子線
の照射によつて上記絶縁膜に発生した電荷は残留
させるが、界面準位は消滅させ、よつて、上記
MIS型半導体素子を、上記絶縁膜に残留している
電荷をパラメータとして決められた閾値電圧を有
するMIS型半導体素子として形成することを特徴
とする半導体集積回路装置の製法。[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device including an MIS type semiconductor element, the electron beam is irradiated with an insulating film of the MIS type semiconductor element, followed by heat treatment. Although the charges generated in the insulating film by the irradiation remain, the interface states disappear, and the above
A method for manufacturing a semiconductor integrated circuit device, characterized in that an MIS type semiconductor element is formed as an MIS type semiconductor element having a threshold voltage determined using the charge remaining in the insulating film as a parameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2065478A JPS54114081A (en) | 1978-02-24 | 1978-02-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2065478A JPS54114081A (en) | 1978-02-24 | 1978-02-24 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54114081A JPS54114081A (en) | 1979-09-05 |
| JPS6210033B2 true JPS6210033B2 (en) | 1987-03-04 |
Family
ID=12033195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2065478A Granted JPS54114081A (en) | 1978-02-24 | 1978-02-24 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54114081A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62147773A (en) * | 1985-12-20 | 1987-07-01 | Nec Corp | Manufacture of semiconductor device |
| JPS63221632A (en) * | 1987-03-10 | 1988-09-14 | Nec Corp | Manufacture of semiconductor device |
| JP2523376B2 (en) * | 1989-07-03 | 1996-08-07 | 東京瓦斯株式会社 | Method of manufacturing MOS transistor and integrated circuit |
-
1978
- 1978-02-24 JP JP2065478A patent/JPS54114081A/en active Granted
Non-Patent Citations (5)
| Title |
|---|
| IEEE TRANSACTIONS ON ELECTRON DEVICES=1968 * |
| IEEE TRANSACTIONS ON NUCLEAR SCIENCE=1975 * |
| IEEE TRANSACTIONS ON NUELEAR SCIENCE=1976 * |
| PROCEEDINGS OF THE IEEE=1967 * |
| RCA REVIEW 28=1976 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54114081A (en) | 1979-09-05 |
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