JPS644069A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a process and to fine a semiconductor element without a necessity of estimating a margin on a design of a semiconductor element, by forming contact holes in a self-alignment manner in source/drain diffusion layers. CONSTITUTION:A silicon oxide film 5 is made to grow on an active region to perform growth of a polycrystalline silicon film and removed except on a part of a gate electrode 6 by an etching method. Next heat treatment is performed to form a nitride film 7 on the surface of a gate electrode 6. An ion implantation layer 8 is formed on the exposed surface. A Ti film 9 is piled and an annealing process is performed in an inactive gas so that the upper part of the ion implantation layer 8 is made to become a titanium silicide layer 10. Next heat treatment is performed in an N2 gas atmosphere so as to form a titanium silicide film 11 on the titanium silicide layer 10 on the source/drain diffusion layer, and heat treatment oxidation is performed in an O2 atmosphere. A dry etching process is used to remove the oxide film and to form an ion implantating layer 8, a titanium silicide layer 10, a source/drain diffusion layer 14. Piling of wiring metals and patterning of them are performed to form metallic wirings 15 connected with the source/drain diffusion layer 14.