JPH0352221B2 - - Google Patents
Info
- Publication number
- JPH0352221B2 JPH0352221B2 JP13242482A JP13242482A JPH0352221B2 JP H0352221 B2 JPH0352221 B2 JP H0352221B2 JP 13242482 A JP13242482 A JP 13242482A JP 13242482 A JP13242482 A JP 13242482A JP H0352221 B2 JPH0352221 B2 JP H0352221B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- oxide film
- resistant
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003647 oxidation Effects 0.000 claims description 36
- 238000007254 oxidation reaction Methods 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、選択酸化法を利用した半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device using a selective oxidation method.
従来、MOS形半導体装置の製造方法としては、
シリコン基板上の酸化膜に耐酸化性マスクとして
作用するパターン化されたシリコン窒化膜を形成
した後、該シリコン窒化膜でおおわれていないフ
イールド領域を酸化処理して比較的肉厚のフイー
ルド酸化膜を形成し、ひきつづきシリコン窒化膜
及びその下の酸化膜を除去してシリコン基板を露
出させ、再び酸化してゲート酸化膜を形成する、
いわゆる選択酸化法の工程が採用され、高密度集
積回路に欠かせぬ技術として注目されている。
Conventionally, the manufacturing method for MOS type semiconductor devices is as follows:
After forming a patterned silicon nitride film that acts as an oxidation-resistant mask on the oxide film on the silicon substrate, the field region not covered with the silicon nitride film is oxidized to form a relatively thick field oxide film. forming a silicon nitride film and subsequently removing the silicon nitride film and the oxide film thereunder to expose the silicon substrate, and oxidizing it again to form a gate oxide film;
The so-called selective oxidation process is used and is attracting attention as an essential technology for high-density integrated circuits.
しかしながら、上記方法にあつてはシリコン窒
化膜を耐酸化性マスクとして水蒸気中で酸化処理
すると、水蒸気とシリコン窒化膜とが反応してア
ンモニアを発生する。このアンモニアはシリコン
窒化膜下のシリコン酸化膜中を拡散してゆき、そ
の下のシリコン基板表面に到達してその表面を窒
化する。この表面窒化物はその後の工程で再び耐
酸化性マスクとなるため、例えばこの領域にゲー
ト酸化膜を形成すると、そのゲート酸化膜自体の
耐圧が極端に低下する。最近ではこの酸化膜耐圧
の劣化を防ぐために、ゲート酸化前に一度シリコ
ン表面を酸化し、上記ゲート酸化のマスクとなる
窒化膜を除去する方法が一般に採られている。し
かしこのような手段をとつてもなおかつ、選択酸
化法によるゲート酸化膜の酸化膜欠陥密度は超高
密度集積回路で使用できる程十分なレベルまで低
下しない。 However, in the above method, when oxidation treatment is performed in water vapor using the silicon nitride film as an oxidation-resistant mask, the water vapor and the silicon nitride film react to generate ammonia. This ammonia diffuses through the silicon oxide film under the silicon nitride film, reaches the surface of the silicon substrate underneath, and nitrides the surface. Since this surface nitride becomes an oxidation-resistant mask again in a subsequent process, for example, if a gate oxide film is formed in this region, the withstand voltage of the gate oxide film itself is extremely reduced. Recently, in order to prevent this oxide film breakdown voltage from deteriorating, a method has generally been adopted in which the silicon surface is oxidized once before gate oxidation, and the nitride film that serves as a mask for the gate oxidation is removed. However, even with such measures, the oxide film defect density of the gate oxide film obtained by the selective oxidation method cannot be reduced to a level sufficient for use in ultra-high density integrated circuits.
本発明の目的は、選択酸化法によりフイールド
酸化膜を形成する半導体装置において、選択酸化
後に基板表面に形成するゲート酸化膜等の絶縁膜
を欠陥のない良質なものとする方法を提供するこ
とにある。
An object of the present invention is to provide a method for making an insulating film such as a gate oxide film formed on a substrate surface after selective oxidation defect-free in a semiconductor device in which a field oxide film is formed by a selective oxidation method. be.
本発明の骨子は、耐酸化性膜として用いる
CVDシリコン窒化膜を形成直後もしくはフイー
ルド酸化直前に不活性ガス中で熱処理し、CVD
シリコン窒化膜中の原子の結合を強め、フイール
ド酸化中にCVDシリコン窒化膜に拡散してくる
酸化剤（水蒸気や酸素）がCVDシリコン窒化膜
と反応するのを抑制することにある。
The gist of the present invention is to use it as an oxidation-resistant film.
CVD silicon nitride film is heat-treated in an inert gas immediately after formation or immediately before field oxidation, and CVD
The purpose of this method is to strengthen the bonds between atoms in the silicon nitride film and to prevent the oxidizing agents (water vapor and oxygen) that diffuse into the CVD silicon nitride film during field oxidation from reacting with the CVD silicon nitride film.
すなわち本発明は、半導体基板表面に第１の酸
化膜を形成しその上に耐酸化性膜を形成する工程
と、上記耐酸化性膜を選択エツチングして耐酸化
性マスクを形成し高温熱酸化によりフイールド酸
化膜を形成する工程と、前記耐酸化性マスクおよ
び第１の酸化膜を除去し露出した基板表面に第２
の酸化膜または窒化膜を形成する工程とを有する
半導体装置の製造方法において、前記耐酸化性膜
として気相成長法により形成したシリコン窒化膜
を用い、該膜形成直後もしくはフイールド酸化直
前に1000〔℃〕以上の不活性ガス中で熱処理を施
すようにした方法である。 That is, the present invention includes the steps of forming a first oxide film on the surface of a semiconductor substrate and forming an oxidation-resistant film thereon, selectively etching the oxidation-resistant film to form an oxidation-resistant mask, and performing high-temperature thermal oxidation. a step of forming a field oxide film by removing the oxidation-resistant mask and the first oxide film and forming a second field oxide film on the exposed substrate surface;
In the method of manufacturing a semiconductor device, the oxidation-resistant film is a silicon nitride film formed by a vapor phase epitaxy method, and a silicon nitride film formed by a vapor phase epitaxy method is used as the oxidation-resistant film. This is a method in which heat treatment is performed in an inert gas at a temperature of 10°C or higher.
本発明によれば、ゲート絶縁膜等として用いら
れる第２の酸化膜または窒化膜を効果的に無欠陥
膜とすることができ、従つてMOS集積回路等の
素子の一層の小形化、高集積化を信頼性よく達成
することが可能となる。
According to the present invention, it is possible to effectively make the second oxide film or nitride film used as a gate insulating film or the like defect-free, thereby further downsizing and highly integrating elements such as MOS integrated circuits. This makes it possible to achieve reliable results.
以下、この発明をMOS半導体装置に適用した
実施例につき図面を参照して説明する。
Hereinafter, embodiments in which the present invention is applied to a MOS semiconductor device will be described with reference to the drawings.
第１図ａに示すように面方位（100）、比抵抗５
〜20〔Ω−cm〕のＰ型シリコン基板１を用意し、
その表面を1150〔℃〕のArと微量酸素雰囲気中で
２時間酸化し、表面に500〔Å〕のシリコン酸化膜
２（第１の酸化膜）を形成し次いで、例えば
CVD法によつて耐酸化性膜である1000〔Å〕程度
のシリコン窒化膜３を堆積する。続いて、1000
〔℃〕の不活性ガス中でシリコン窒化膜３を熱処
理する。次に、第１図ｂに示すように写真蝕刻工
程により素子形成領域上にレジスト膜４を形成
し、このレジスト膜４をマスクとしてシリコン窒
化膜３を選択的にエツチング除去し、さらにレジ
スト膜４とシリコン窒化膜３をマスクとしてフイ
ールド領域のシリコン基板中にボロンイオン注入
層５を形成する。つづいてレジスト膜４を除去し
たのち第１図ｃに示すようにシリコン窒化膜３を
マスクとして1000〔℃〕、ウエツト酸素雰囲気中で
酸化を行ない厚さ1.0〔μｍ〕のフイールド酸化膜
６を成長させる。これにより、イオン注入層５は
活性化してP+層７となる。ひきつづき、緩衡フ
ツ化水素液でシリコン窒化膜３上に形成されたシ
リコン酸化膜８を除去した後、CF4とO2を高周波
で励起したガス中でシリコン窒化膜３を除去す
る。このあと再び1000〔℃〕のウエツト酸素雰囲
気で20分酸化処理を施し、第１図ｅに示すように
シリコン酸化膜９を形成する。このあと、素子形
成領域にある酸化膜９を除去し、続いて乾燥酸素
雰囲気中で第１図ｅに示すようにゲート酸化膜と
なる厚さ400〔Å〕のシリコン酸化膜１２（第２の
酸化膜）を成長させ、その上に厚さ3000〔Å〕の
燐添加多結晶シリコン膜をCVD法によつて堆積
したのち、写真蝕刻法によりこの燐添加多結晶シ
リコン膜をパターニングしてゲート電極１３を形
成する。次にこのゲート電極１３をマスクとし酸
化膜１２をエツチングし、前記フイールド酸化膜
６とゲート電極１３をマスクとして砒素イオンの
注入を行なつて、第１図ｆに示すようにｎ型の高
濃度不純物層としての深さ0.6〔μｍ〕のソース１
４及びドレイン１５を形成し、次いで、全面に厚
さ3000〔Å〕のCVD酸化膜１６及び厚さ4000〔Å〕
の燐硅化ガラス膜１７（PSG膜）を堆積する。
そして第１図ｇに示すように、ソース１４及びド
レイン１５に対応する部分に写真蝕刻法によりコ
ンタクトホールを形成し、全面にAl膜を真空蒸
着し写真蝕刻法によりパターニングして取出し、
電極１８，１９を形成して、ｎチヤンネルMOS
電界効果トランジスタを製造した。 As shown in Figure 1a, the surface orientation (100) and the specific resistance 5
Prepare a P-type silicon substrate 1 of ~20 [Ω-cm],
The surface is oxidized for 2 hours in an Ar and trace oxygen atmosphere at 1150 [°C] to form a 500 [Å] silicon oxide film 2 (first oxide film) on the surface, and then, for example,
A silicon nitride film 3 having a thickness of approximately 1000 Å is deposited by the CVD method as an oxidation-resistant film. Then 1000
The silicon nitride film 3 is heat-treated in an inert gas at [° C.]. Next, as shown in FIG. 1B, a resist film 4 is formed on the element formation region by a photolithography process, and the silicon nitride film 3 is selectively etched away using this resist film 4 as a mask. Then, a boron ion implantation layer 5 is formed in the silicon substrate in the field region using the silicon nitride film 3 as a mask. After removing the resist film 4, as shown in FIG. 1c, oxidation is performed in a wet oxygen atmosphere at 1000 [°C] using the silicon nitride film 3 as a mask to grow a field oxide film 6 with a thickness of 1.0 [μm]. let As a result, the ion implantation layer 5 is activated and becomes the P + layer 7. Subsequently, the silicon oxide film 8 formed on the silicon nitride film 3 is removed using a buffered hydrogen fluoride solution, and then the silicon nitride film 3 is removed in a gas in which CF 4 and O 2 are excited at a high frequency. Thereafter, oxidation treatment is performed again for 20 minutes in a wet oxygen atmosphere at 1000°C to form a silicon oxide film 9 as shown in FIG. 1e. After that, the oxide film 9 in the element formation region is removed, and then the silicon oxide film 12 (second silicon oxide film) with a thickness of 400 Å, which will become the gate oxide film, is removed in a dry oxygen atmosphere as shown in FIG. 1e. After growing a 3000 Å thick phosphorus-doped polycrystalline silicon film on it using the CVD method, this phosphorus-doped polycrystalline silicon film is patterned using photolithography to form a gate electrode. form 13. Next, the oxide film 12 is etched using the gate electrode 13 as a mask, and arsenic ions are implanted using the field oxide film 6 and the gate electrode 13 as masks to form an n-type high-concentration material as shown in FIG. Source 1 with a depth of 0.6 [μm] as an impurity layer
4 and drain 15 are formed, and then a CVD oxide film 16 with a thickness of 3000 [Å] and a thickness of 4000 [Å] is formed on the entire surface.
A phosphorus silicide glass film 17 (PSG film) is deposited.
Then, as shown in FIG. 1g, contact holes are formed in portions corresponding to the source 14 and drain 15 by photolithography, and an Al film is vacuum deposited on the entire surface and patterned by photolithography to take it out.
By forming electrodes 18 and 19, an n-channel MOS
A field effect transistor was manufactured.
この実施例によれば、耐酸化性膜として用いる
CVDシリコン窒化膜を形成直後に1000〔℃〕以上
の不活性ガス中で熱処理することによりシリコン
酸化膜２とシリコン基板１との界面に窒化物が形
成されるのを抑制でき、ゲート酸化膜の欠陥を著
しく減少させることが可能となつた。第２図ａ，
ｂはゲート酸化膜の耐圧分布を示す特性図で、ａ
は従来方法、ｂは本実施例方法によるものを示し
ている。この図からもゲート酸化膜の欠陥が著し
く減少されるのが明らかである。 According to this example, it is used as an oxidation-resistant film.
Immediately after forming the CVD silicon nitride film, heat treatment in an inert gas at a temperature of 1000 [°C] or higher can suppress the formation of nitride at the interface between the silicon oxide film 2 and the silicon substrate 1. It has become possible to significantly reduce defects. Figure 2a,
b is a characteristic diagram showing the breakdown voltage distribution of the gate oxide film;
1 shows the conventional method, and b shows the method of this embodiment. It is clear from this figure that defects in the gate oxide film are significantly reduced.
なお、本発明は上述した実施例に限定されず、
種々変更を加え得るものである。例えば前記耐酸
化性膜としてのCVDシリコン窒化膜の熱処理は、
該膜形成直後に限るものではなく、フイールド酸
化直前に行つてもよい。また、MOSトランジス
タに限らず、各種の半導体装置に適用できるのは
勿論のことである。 Note that the present invention is not limited to the above-mentioned embodiments,
Various changes can be made. For example, the heat treatment of the CVD silicon nitride film as the oxidation-resistant film is
The process is not limited to immediately after the film is formed, but may be performed immediately before the field oxidation. Moreover, it goes without saying that the present invention can be applied not only to MOS transistors but also to various semiconductor devices.
第１図ａ〜ｇは本発明の一実施例に係わる
MOSトランンジスタ製造工程を示す断面図、第
２図ａ，ｂはゲート酸化膜の耐圧分布を示す特性
図でａは従来方法によるもの、ｂは上記実施例方
法によるものである。
１……シリコン基板、２……シリコン酸化膜
（第１の酸化膜）、３……シリコン窒化膜（耐酸化
性膜）、４……レジスト膜、５……イオン注入層、
６……フイールド酸化膜、７……P+層、９……
シリコン酸化膜、１２……シリコン酸化膜（第２
の酸化膜）、１３……ゲート電極、１４……ソー
ス、１５……ドレイン、１６……CVD酸化膜、
１７……PSG膜、１８，１９……取出し電極。
Figures 1a to 1g relate to one embodiment of the present invention.
FIGS. 2A and 2B are cross-sectional views showing the manufacturing process of a MOS transistor. FIGS. 2A and 2B are characteristic diagrams showing the breakdown voltage distribution of a gate oxide film, where A is a result obtained by the conventional method and FIG. 2B is a result obtained by the method of the above embodiment. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Silicon oxide film (first oxide film), 3...Silicon nitride film (oxidation-resistant film), 4...Resist film, 5...Ion implantation layer,
6...Field oxide film, 7...P + layer, 9...
Silicon oxide film, 12...Silicon oxide film (second
oxide film), 13...gate electrode, 14...source, 15...drain, 16...CVD oxide film,
17...PSG film, 18, 19... Extraction electrode.
Claims (1)
上に耐酸化膜を形成する工程と、上記耐酸化性膜
を選択エツチングして耐酸化性マスクを形成し高
温熱酸化によりフイールド酸化膜を形成する工程
と、前記耐酸化性マスクおよび第１の酸化膜を除
去し露出した基板表面に第２の酸化膜または窒化
膜を形成する工程とを有する半導体装置の製造方
法において、前記耐酸化性膜として気相成長法に
より形成したシリコン窒化膜を用い、該膜形成直
後もしくはフイールド酸化直前に1000〔℃〕以上
の不活性ガス中で熱処理を施すことを特徴とする
半導体装置の製造方法。[Claims] 1. A step of forming a first oxide film on the surface of a semiconductor substrate and forming an oxidation-resistant film thereon, selectively etching the oxidation-resistant film to form an oxidation-resistant mask, and etching the oxidation-resistant film at high temperature. A method for manufacturing a semiconductor device, comprising: forming a field oxide film by oxidation; and removing the oxidation-resistant mask and first oxide film and forming a second oxide film or nitride film on the exposed substrate surface. A semiconductor characterized in that a silicon nitride film formed by a vapor phase growth method is used as the oxidation-resistant film, and heat treatment is performed in an inert gas at a temperature of 1000 [°C] or more immediately after the film is formed or immediately before field oxidation. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13242482A JPS5922343A (en) | 1982-07-29 | 1982-07-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13242482A JPS5922343A (en) | 1982-07-29 | 1982-07-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5922343A JPS5922343A (en) | 1984-02-04 |
| JPH0352221B2 true JPH0352221B2 (en) | 1991-08-09 |
Family
ID=15081048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13242482A Granted JPS5922343A (en) | 1982-07-29 | 1982-07-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922343A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887161A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for restraining doping atoms from diffusing in gate dielectric |
-
1982
- 1982-07-29 JP JP13242482A patent/JPS5922343A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5922343A (en) | 1984-02-04 |
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