JPS628023B2 - - Google Patents
Info
- Publication number
- JPS628023B2 JPS628023B2 JP14732179A JP14732179A JPS628023B2 JP S628023 B2 JPS628023 B2 JP S628023B2 JP 14732179 A JP14732179 A JP 14732179A JP 14732179 A JP14732179 A JP 14732179A JP S628023 B2 JPS628023 B2 JP S628023B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- ion implantation
- film
- substrate
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 34
- 230000003647 oxidation Effects 0.000 claims description 29
- 238000007254 oxidation reaction Methods 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- -1 oxygen ions Chemical class 0.000 claims description 4
- 230000010354 integration Effects 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特に
微細素子を高集積化するための素子分離の方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of element isolation for highly integrating fine elements.
従来より、微細な半導体素子を高集積度に形成
するための素子分離法として、選択酸化により半
導体基板のフイールド領域に厚いフイールド酸化
膜を形成する方法が知られている。例えば、Si基
板を用いた場合、素子形成に先だつてその素子形
成領域に厚さ300Å程度のシリコン酸化膜を介し
て厚さ3000Å程度のシリコン窒化膜を堆積した耐
酸化性マスクを形成し、熱酸化を行つて厚さ約１
μｍのフイールド酸化膜を形成することが行われ
る。しかしこの方法では、熱酸化が基板の深さの
方向だけでなく横方向にも進行するため、フイー
ルド酸化膜の端部は耐酸化性マスク下の素子形成
領域にまで鳥の口ばし状に食い込む。この食い込
みは上記条件で約0.7μｍにも達する。このた
め、微細な素子を集積した場合、例えばMOSデ
バイスであればチヤネル幅が狭くなる等により、
設計どおりの動作ができなくなる。所望の動作を
得るには、予め素子形成領域に形成する耐酸化性
マスクを、フイールド酸化膜の食い込みを見込ん
で面積を大きくすればよいが、これは集積度向上
の妨げとなる。また、上述した食い込みを小さく
するには、耐酸化性マスクのシリコン酸化膜を薄
く、シリコン窒化膜を厚くすることがある程度有
効である。しかし、これは本質的解決にはなら
ず、またシリコン窒化膜を厚くすることでフイー
ルド酸化膜の食い込みを抑えると、基板表面に歪
による欠陥が生じ、これが形成される素子の特性
に悪影響をおよぼす。 2. Description of the Related Art Conventionally, a method of forming a thick field oxide film in a field region of a semiconductor substrate by selective oxidation has been known as an element isolation method for forming fine semiconductor elements with a high degree of integration. For example, when using a Si substrate, prior to device formation, an oxidation-resistant mask is formed by depositing a silicon nitride film approximately 3000 Å thick through a silicon oxide film approximately 300 Å thick in the element formation region, and After oxidation, the thickness is about 1
A field oxide film of .mu.m is formed. However, with this method, thermal oxidation progresses not only in the depth direction of the substrate but also in the lateral direction, so the edge of the field oxide film forms a bird's beak shape that extends into the element formation area under the oxidation-resistant mask. Dig into it. This intrusion reaches approximately 0.7 μm under the above conditions. For this reason, when fine elements are integrated, for example, in the case of MOS devices, the channel width becomes narrower.
It will no longer work as designed. In order to obtain the desired operation, the area of the oxidation-resistant mask formed in advance in the element formation region may be increased in anticipation of the encroachment of the field oxide film, but this hinders the improvement of the degree of integration. Further, in order to reduce the above-mentioned bite, it is somewhat effective to make the silicon oxide film of the oxidation-resistant mask thinner and the silicon nitride film thicker. However, this is not an essential solution, and if the silicon nitride film is made thicker to suppress the encroachment of the field oxide film, defects due to distortion will occur on the substrate surface, which will adversely affect the characteristics of the devices formed. .
この発明は上記の点に鑑み、フイールド酸化膜
の素子形成領域への食い込みを効果的に防止し
て、設計値どおりの微細素子を高集積度に形成す
ることを可能とした半導体装置の製造方法を提供
するものである。 In view of the above-mentioned points, the present invention has been devised to effectively prevent the field oxide film from digging into the element formation region, and to form a semiconductor device manufacturing method that makes it possible to form fine elements as designed with a high degree of integration. It provides:
この発明は、半導体基板の素子形成領域にマス
クを設け、イオン注入によつてフイールド領域の
基板内部から少くともマスク端部下の基板表面に
まで延びる埋込み絶縁膜を形成し、この埋込み絶
縁膜で囲まれたフイールド領域に熱酸化によりフ
イールド酸化膜を形成することを骨子とする。 This invention provides a mask in an element formation region of a semiconductor substrate, forms a buried insulating film extending from the inside of the substrate in a field region to at least the surface of the substrate under the edge of the mask by ion implantation, and surrounds the semiconductor substrate with the buried insulating film. The main idea is to form a field oxide film by thermal oxidation in the field region where the oxidation process is performed.
以下この発明の実施例を図面を用いて説明す
る。第１図ａ〜ｃはMOSデバイスに適用した一
実施例の製造工程図である。まず、ｐ型Si基板１
の素子形成領域に、よく知られた方法で厚さ約
600Åのシリコン酸化膜２に厚さ約6000Åのシリ
コン窒化膜３を重ねた耐酸化性マスクを兼ねた耐
イオン注入マスクを設け、酸素イオンを加速電圧
210kV、ドーズ量５×1016／cm2で注入し、酸素雰
囲気中、1000℃で熱処理をしてフイールド領域の
基板内部約5000Åの深さのところからマスク端部
下の基板表面にまで延びる形で約3000Åのシリコ
ン酸化膜４を埋込むａ。この後シリコン窒化膜３
をそのまま耐酸化性マスクとして、水蒸気雰囲気
中、1000℃で360分間熱酸化して、シリコン酸化
膜４で囲まれた領域にフイールド酸化膜５を形成
するｂ。そしてシリコン窒化膜３、シリコン酸化
膜２を順次エツチング除去して素子形成領域の基
板表面を露出させ、従来と同様の方法でゲート酸
化膜６を介して多結晶シリコン膜からなるゲート
電極７を形成し、ゲート電極７をマスクとして例
えばAsをイオン注入してn+型のソース８、ドレ
イン９を形成し、CVD法によるシリコン酸化膜
１０で全体をおおい、コンタクトホールをあけて
Al膜の蒸着、パターニングにより必要な電極１
１，１２を配設して完成するｃ。 Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1a to 1c are manufacturing process diagrams of an embodiment applied to a MOS device. First, p-type Si substrate 1
A thickness of approximately
An ion implantation-resistant mask that also serves as an oxidation-resistant mask is prepared by overlapping a silicon nitride film 3 with a thickness of about 6000 Å on a silicon oxide film 2 with a thickness of 600 Å, and oxygen ions are accelerated at a voltage.
It was implanted at 210 kV and at a dose of 5 x 10 16 /cm 2 and heat-treated at 1000°C in an oxygen atmosphere to extend from a depth of about 5000 Å inside the substrate in the field region to the substrate surface under the edge of the mask. A silicon oxide film 4 of about 3000 Å is buried. After this, silicon nitride film 3
Using as an oxidation-resistant mask, thermal oxidation is performed at 1000° C. for 360 minutes in a steam atmosphere to form a field oxide film 5 in the area surrounded by the silicon oxide film 4 b. Then, the silicon nitride film 3 and the silicon oxide film 2 are sequentially etched away to expose the substrate surface in the element formation region, and a gate electrode 7 made of a polycrystalline silicon film is formed via the gate oxide film 6 in the same manner as in the conventional method. Then, using the gate electrode 7 as a mask, for example, As is ion-implanted to form an n + type source 8 and drain 9, and the whole is covered with a silicon oxide film 10 by CVD method, and a contact hole is made.
Electrode 1 required for Al film deposition and patterning
Complete by placing 1 and 12 c.
この実施例によれば、フイールド酸化の工程前
にフイールド領域の基板内部から素子形成領域の
端部の基板表面に延びる形の埋込み絶縁膜を形成
しているため、この埋込み絶縁膜によつてフイー
ルド酸化の横方向への進行が阻害される。従つ
て、形成されるフイールド酸化膜５の端部は耐イ
オン注入マスクの端部とほぼ一致して定義され、
フイールド酸化膜の素子領域への食い込みがない
ためMOSデバイスのチヤネル幅の減少といつた
問題がなく、設計値どおりの微細素子を高集積化
することが可能となる。 According to this embodiment, before the field oxidation step, a buried insulating film extending from the inside of the substrate in the field region to the substrate surface at the end of the element formation region is formed, so that the field is Lateral progress of oxidation is inhibited. Therefore, the edge of the field oxide film 5 to be formed is defined to almost coincide with the edge of the ion implantation mask,
Since there is no encroachment of the field oxide film into the element region, there is no problem such as a reduction in the channel width of the MOS device, and it is possible to highly integrate fine elements as designed.
なお、上記実施例ではイオン注入後熱処理をし
て埋込み絶縁膜を形成したが、熱処理工程を省略
し、これを次のフイールド酸化膜を形成する熱酸
化と兼ねてもよい。また上記実施例では酸素イオ
ン注入によりシリコン酸化膜を埋込んだが、窒素
イオン注入によりシリコン窒化膜を埋込んでもよ
い。更に、フイールド酸化は埋込み絶縁膜で囲ま
れた領域の全体が酸化膜になるまで行うことは必
ずしも必要ではない。即ち埋込み絶縁膜は、フイ
ールド領域の基板内部に埋込まれている部分が本
質的なものではなく、必要なのは素子領域の端部
でフイールド酸化の食い込みを阻止する部分であ
るから、所定のフイールド酸化を行つた後に深さ
方向に埋込み絶縁膜との間に酸化されない部分が
残つても何ら差支えない。 In the above embodiment, the buried insulating film was formed by heat treatment after ion implantation, but the heat treatment step may be omitted and this may also be used as thermal oxidation to form the next field oxide film. Further, in the above embodiment, the silicon oxide film was buried by oxygen ion implantation, but a silicon nitride film may be buried by nitrogen ion implantation. Furthermore, it is not necessarily necessary to perform field oxidation until the entire region surrounded by the buried insulating film becomes an oxide film. In other words, the part of the buried insulating film that is buried inside the substrate in the field region is not essential, and what is needed is a part that prevents field oxidation from digging into the edge of the element region. There is no problem even if a portion that is not oxidized remains between the buried insulating film and the buried insulating film in the depth direction after performing this process.
また上記実施例では埋込み絶縁膜をフイールド
領域の基板内部から素子形成領域端部の基板表面
に延びる形で設けたが、素子形成領域全体の基板
表面にまで連続的に設けるようにしてもよい。そ
の場合、イオン注入に窒素を用いれば、素子形成
領域の基板表面に形成されるシリコン窒化膜を後
のフイールド酸化のための耐酸化性マスクとして
用いることができる。そのようにした実施例を第
２図により説明する。まずｐ型Si基板２１に耐イ
オン注入マスクとして素子形成領域に厚さ4000Å
のシリコン酸化膜２２を形成し、次に窒素を加速
電圧180kV、ドーズ量５×1016／cm2でイオン注入
し、窒素雰囲気中、1000℃で熱処理してフイール
ド領域の基板内部約5000Åの位置に埋込まれた厚
さ約3000Åのシリコン窒化膜２３１とこれに連続
的に素子形成領域の基板表面をおおう厚さ約1500
Åのシリコン窒化膜３２２を形成するｂ。そして
シリコン酸化膜２２を除去し、素子形成領域の基
板表面にあるシリコン窒化膜２３２を耐酸化性マ
スクとして利用して例えば水蒸気雰囲気中、1000
℃で約360分の熱酸化を行つてフイールド酸化膜
２４を形成するｂ。この後は素子形成領域のシリ
コン窒化膜２３２を除去して、先の実施例と同様
に所望の素子を形成して完成する。 Further, in the above embodiment, the buried insulating film is provided extending from the inside of the substrate in the field region to the substrate surface at the end of the element forming region, but it may be provided continuously to the substrate surface in the entire element forming region. In that case, if nitrogen is used for ion implantation, the silicon nitride film formed on the substrate surface in the element formation region can be used as an oxidation-resistant mask for later field oxidation. Such an embodiment will be explained with reference to FIG. 2. First, a p-type Si substrate 21 was coated with a thickness of 4000 Å in the element formation region as an ion implantation mask.
A silicon oxide film 22 is formed, and then nitrogen ions are implanted at an acceleration voltage of 180 kV and a dose of 5 x 10 16 /cm 2 , and heat treated at 1000°C in a nitrogen atmosphere to form a silicon oxide film 22 at a position of about 5000 Å inside the substrate in the field region. A silicon nitride film 23 1 with a thickness of approximately 3000 Å is embedded in the silicon nitride film 23 1 and a silicon nitride film 23 1 with a thickness of approximately 1500 Å continuously covers the surface of the substrate in the element formation region.
Forming a silicon nitride film 322 with a thickness of 1.5 Å thick. Then, the silicon oxide film 22 is removed, and the silicon nitride film 232 on the surface of the substrate in the element formation region is used as an oxidation-resistant mask to remove the
A field oxide film 24 is formed by thermal oxidation at a temperature of about 360 minutes b. After this, the silicon nitride film 232 in the element formation region is removed, and the desired element is formed and completed in the same manner as in the previous embodiment.
この実施例によつても、イオン注入により埋込
まれたシリコン窒化膜２３１，２３２がフイール
ド酸化膜の素子領域への食い込みを阻止する結
果、先の実施例と同様の効果が得られる。 In this embodiment as well, the silicon nitride films 23 1 and 23 2 buried by ion implantation prevent the field oxide film from digging into the element region, so that the same effect as in the previous embodiment can be obtained.
以上では半導体基板としてｐ型Si基板を用いた
が、ｎ型Si基板を用いる場合は勿論、他の半導体
材料基板を用いる場合にもこの発明を適用でき
る。また、イオン注入による埋込み絶縁膜の直下
にイオン注入により反転防止層を設けるとか、基
板平坦化のためにフイールド酸化工程前にフイー
ルド領域の基板表面を所定深さエツチングする等
の変形も可能であるし、勿論バイポーラ型半導体
装置にもこの発明を適用することができる。 In the above description, a p-type Si substrate was used as the semiconductor substrate, but the present invention is applicable not only to the case of using an n-type Si substrate but also to the case of using other semiconductor material substrates. Further, modifications such as providing an anti-reversal layer by ion implantation directly under the buried insulating film by ion implantation, or etching the substrate surface in the field region to a predetermined depth before the field oxidation process to flatten the substrate are also possible. Of course, the present invention can also be applied to bipolar semiconductor devices.
以上説明したように、この発明によれば、フイ
ールド酸化に先だつてイオン注入による埋込み絶
縁膜を形成することにより、フイールド酸化膜の
素子形成領域への食い込みを効果的に防止して、
設計値どおりの微細素子を高集積度に形成するこ
とができる。 As explained above, according to the present invention, by forming a buried insulating film by ion implantation prior to field oxidation, it is possible to effectively prevent the field oxide film from digging into the element formation region.
It is possible to form fine elements with a high degree of integration according to design values.
第１図ａ〜ｃはこの発明の一実施例の製造工程
断面図、第２図ａ，ｂは他の実施例の製造工程断
面図である。
１……ｐ型Si基板、２……シリコン酸化膜、３
……シリコン窒化膜（耐酸化性マスク兼耐イオン
注入マスク）、４……シリコン酸化膜（埋込み絶
縁膜）、５……フイールド酸化膜、２１……ｐ型
Si基板、２２……シリコン酸化膜（耐イオン注入
マスク）、２３１，２３２……シリコン窒化膜
（埋込み絶縁膜）。
1A to 1C are sectional views of the manufacturing process of one embodiment of the present invention, and FIGS. 2A and 2B are sectional views of the manufacturing process of another embodiment. 1... p-type Si substrate, 2... silicon oxide film, 3
...Silicon nitride film (oxidation-resistant mask and ion implantation-resistant mask), 4...Silicon oxide film (buried insulating film), 5...Field oxide film, 21...p-type
Si substrate, 22... silicon oxide film (ion implantation resistant mask), 23 1 , 23 2 ... silicon nitride film (embedded insulating film).
Claims (1)
スクを設け、イオン注入によりフイールド領域の
基板内部から少くとも耐イオン注入マスク端部下
の基板表面にまで延びる埋込み絶縁膜を形成し、
この埋込み絶縁膜で囲まれたフイールド領域に熱
酸化によりフイールド酸化膜を形成し、このフイ
ールド酸化膜で囲まれた素子形成領域に所望の素
子を形成することを特徴とする半導体装置の製造
方法。 ２ 耐イオン注入マスクはシリコン窒化膜であ
り、埋込み絶縁膜は酸素イオンまたは窒素イオン
の注入によるシリコン酸化膜またはシリコン窒化
膜であり、耐イオン注入マスクをそのまま耐酸化
性マスクとして熱酸化を行つてフイールド酸化膜
を形成するようにした特許請求の範囲第１項記載
の半導体装置の製造方法。 ３ 耐イオン注入マスクはシリコン酸化膜であ
り、埋込み絶縁膜は窒素イオン注入によるシリコ
ン窒化膜であつて、シリコン窒化膜をフイールド
領域の基板内部からイオン注入マスク下の素子形
成領域全体の基板表面にも連続的に形成し、素子
形成領域のシリコン窒化膜を耐酸化性マスクとし
て熱酸化を行つてフイールド酸化膜を形成するよ
うにした特許請求の範囲第１項記載の半導体装置
の製造方法。[Scope of Claims] 1. An ion implantation resistant mask is provided in the element formation region of the semiconductor substrate, and a buried insulating film is formed by ion implantation to extend from the inside of the substrate in the field region to at least the surface of the substrate under the edge of the ion implantation mask. ,
A method for manufacturing a semiconductor device, comprising forming a field oxide film by thermal oxidation in a field region surrounded by the buried insulating film, and forming a desired element in an element formation region surrounded by the field oxide film. 2. The ion implantation resistant mask is a silicon nitride film, and the buried insulating film is a silicon oxide film or silicon nitride film implanted with oxygen ions or nitrogen ions.The ion implantation mask is used as an oxidation resistant mask for thermal oxidation. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a field oxide film is formed. 3. The ion implantation resistant mask is a silicon oxide film, and the buried insulating film is a silicon nitride film formed by nitrogen ion implantation. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the field oxide film is formed by continuously forming the field oxide film and performing thermal oxidation using the silicon nitride film in the element formation region as an oxidation-resistant mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14732179A JPS5670645A (en) | 1979-11-14 | 1979-11-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14732179A JPS5670645A (en) | 1979-11-14 | 1979-11-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5670645A JPS5670645A (en) | 1981-06-12 |
| JPS628023B2 true JPS628023B2 (en) | 1987-02-20 |
Family
ID=15427532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14732179A Granted JPS5670645A (en) | 1979-11-14 | 1979-11-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5670645A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2563377B1 (en) * | 1984-04-19 | 1987-01-23 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN INSULATING LAYER BURIED IN A SEMICONDUCTOR SUBSTRATE, BY ION IMPLANTATION |
-
1979
- 1979-11-14 JP JP14732179A patent/JPS5670645A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5670645A (en) | 1981-06-12 |
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