JP2730650B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MIS (Metal Insulating Film Semiconductor) and a MOS (Metal Oxide) having fine dimensions and capable of being highly integrated. Film semiconductor).

Conventional technology DRAM (Dynamic Random Access Memory)
As for MOS (metal oxide semiconductor) type semiconductor elements represented by the above, chips are successively miniaturized and highly integrated, and chips having an element size of 1 μm or less and one million or more integrated chips have been developed. However, such miniaturization and high integration were not easily realized, and it was necessary to devise a manufacturing method, optimize a semiconductor element structure, and develop a new manufacturing apparatus.

For example, as a method of forming a field oxide film for separating transistors, a conventional LOCOS method (selective oxidation method) is generally used. With a separation width of about 2 to 3 μm, a step can be formed at a step portion of the field oxide film and a self-alignment method can be used. This is an excellent method for forming a channel stopper layer below the field oxide film. However, there is a problem that a field oxide film (bird's beak) and a channel stopper layer are formed up to the active region (region for forming an element such as a transistor) and a transistor cannot be formed.

In order to solve this problem, several improved LOCOS methods have been studied and proposed (Semiconductor World, May 1985, element isolation technology in the 0.5 μm era, pp. 99-104).

First, the lateral spread of the field oxide film is as follows: (1) The substrate is etched shallowly to form a side wall (side wall) of a silicon nitride film to prevent the lateral spread of the oxide film.

(2) Another film is previously deposited on the silicon nitride film so that the silicon nitride film is not lifted by the growth of the oxide film during oxidation.

(3) Polycrystalline silicon is formed under the silicon nitride film to prevent the silicon nitride film from lifting during oxidation.

(4) The silicon nitride film is grown directly on the substrate by gradually changing the composition of the silicon nitride film from a composition close to silicon to a nitride film.

(5) Use a silicon oxynitride film instead of a silicon nitride film.

Etc.

On the other hand, for the leaching of the channel stopper layer instead of the lateral spread of the field oxide film, a method is known in which a channel stopper is injected after the formation of the field oxide film to reduce thermal diffusion and prevent leaching. I have.

According to these improved methods, a method of forming a field oxide film in the reverse order, instead of forming a field oxide film after forming a well, and then forming a well is promising.

The method of manufacturing the conventional semiconductor device will be described below in the third.
Description will be made with reference to the drawings. FIG. 3 is a process chart for explaining a method of simultaneously performing well formation, channel stopper formation, and channel doping (diffusion) after forming a field oxide film. FIG. 3A shows a state in which a silicon oxide film 2 and a silicon nitride film 3 are sequentially grown on a semiconductor substrate 1 and then the silicon nitride film 3 is etched according to a predetermined pattern. Next, as shown in FIG. 3 (b), a field oxide film 4 is
Grow by.

Thereafter, the silicon nitride film 3 used as the mask is removed.
Next, as shown in FIG. 3C, after the first well resist mask 5 is formed, the first well implantation layer 6 (approximately 0.5 to 1.5 μm depth) and the channel stopper implantation layer 7 ( A channel dope injection layer 8 (approximately 0.1 to 0.3 μm deep) is formed simultaneously. Next, as shown in FIG. 3D, the first well resist mask 5 is removed, and a second well resist mask 9 is formed to cover the ion-implanted region in FIG. 3C.
The second well implantation layer 10 (about 0.5
Simultaneously, a channel stopper injection layer 11 (approximately 0.3 to 0.8 μm depth) and a channel dope injection layer 12 (approximately 0.1 to 0.3 μm depth) are formed. This completes the well and element isolation steps. Here, the first well injection layer 6 and the second well injection layer 10 are formed of impurities giving different conductivity types. Either the first well injection layer 6 or the second well injection layer 10 is not necessarily required and can be omitted if it is the same conductivity type as the semiconductor substrate 1.

SUMMARY OF THE INVENTION However, in the above-described conventional configuration, miniaturization is possible by a method of forming a well injection layer after forming a field oxide film, and a shallow well injection layer can be formed. However, since the well injection layer is shallow, Another problem is that the sheet resistance of the well injection layer increases. That is, when the sheet resistance of the well injection layer increases, the potential of the well tends to become unstable, and malfunction, increase in leak current, occurrence of latch-up, and the like are likely to occur.

As a method for preventing an increase in the sheet resistance of a well, (a) epitaxial growth is performed after forming a buried layer in a semiconductor substrate (the same as the method for manufacturing a bipolar transistor).

(B) An epitaxial layer having a high specific resistance is grown on a substrate having a low specific resistance (a method often used for MOS transistors).

(C) Impurity ions are implanted into relatively deep positions by high-acceleration ion implantation (acceleration energy is about 1 MeV).

And so on. However, both (a) and (b) use epitaxial growth, so that the manufacturing cost is significantly increased. In (c), since impurities are implanted with high energy, a damaged layer is formed near the surface, which has a significant effect on device characteristics, and it is difficult to recover.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, reduces the sheet resistance of a well, prevents junction leakage current, malfunctions,
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing a leak and a latch-up and designing a structure for obtaining predetermined characteristics even with high integration.

Means for Solving the Problems In order to achieve this object, a semiconductor device of the present invention is designed to reduce the sheet resistance of a semiconductor substrate or a shallow well injection layer by using high acceleration at a deep position in a region where a shallow well injection layer is formed. It has an ion implanted layer (hereinafter referred to as a deep well implanted layer) and forms a channel stopper layer above the shallow well implanted layer. This implantation layer needs to be implanted so as not to significantly affect the impurity distribution of the shallow well implantation layer formed thereon. That is, the introduction of impurities by high-acceleration ion implantation is performed at the designed depth and region,
In order to reduce damage and prevent deterioration of device characteristics, it is necessary to optimize the order of ion implantation, its energy, implantation amount, and heat treatment after implantation.

If the acceleration energy of ion implantation increases, physical sputtering (etching) becomes prominent, so the energy of the implanted ions must be about 900 eV or less to prevent deformation of the resist mask and decrease in film thickness. is there. This value corresponds to a depth of about 1.5 μm for boron and about 1.0 μm for phosphorus in terms of the ion arrival depth. On the other hand, the depth of the well injection layer required in the present invention is 0.5 to 1.5 μm for a shallow well injection layer and 1.0 to 3.0 μm for a deep well injection layer. If the energy is increased to perform deep well injection, the resist mask will be deformed and the film will be reduced.
Care must be taken with the resist material and its pattern shape.

In the present invention, the deep well implantation layer is implanted before removing the silicon nitride film after LOCOS. In this manner, since the surface of the semiconductor substrate includes the silicon nitride film and the silicon oxide film, the effect of suppressing the sputtering of the semiconductor substrate can be sufficiently provided without adding a new process. In addition, in order to prevent the reduction of the thickness of the resist mask and the change of the surface shape when the deep well injection layer is implanted, it is necessary to suppress the acceleration energy to 3 MeV or less and the implantation amount to 3 × 10 ¹³ cm ² or less.

After the deep well injection layer implantation, after removing the silicon nitride film and silicon oxide film used for the mask of LOCOS,
Annealing and formation of an oxide film as a protective film for the next implantation are performed.

This step is also convenient for recovering the damaged layer near the surface of the semiconductor substrate. 900 ° C. 30 between the deep well injection layer implantation step and the deep well injection layer implantation step.
When the heat treatment is performed for more than one minute, the occurrence of leakage at the junction is reduced.

For the above reasons, the order of the steps is implantation for forming a deep well injection layer, removal of a silicon nitride film and a silicon oxide film, heat treatment (at 900 ° C. for 30 minutes or more), resist patterning, and formation of a shallow first well injection layer. Implantation (simultaneous channel doping implantation and channel stop implantation),
The resist patterning, implantation for forming a shallow second well implantation layer (simultaneous channel doping implantation and channel stop implantation), and heat treatment (at 900 ° C. for 30 minutes or more) are performed.
If either the shallow first or second well injection layer is of the same conductivity type as the semiconductor substrate, it is not always necessary and can be omitted.

The following table shows the compatibility of the conduction type combination of the semiconductor substrate, the deep well injection layer, and the shallow well injection layer. In the table, ◎ indicates a good combination and X indicates a bad combination.

In the table, if the conductivity type of the semiconductor substrate is the same as that of the deep well injection layer, the sheet resistance of the deep well injection layer is reduced because the substrate concentration is increased (marked by 基板 in the table). When a conductive deep well injection layer different from a semiconductor substrate is formed, the semiconductor substrate and the deep well injection layer are separated by a PN junction, and the potential of the deep well injection layer becomes unstable. In order to solve this problem, it is necessary to connect the semiconductor substrate with a shallow well injection layer of the same conductivity type as the semiconductor substrate, and to connect a deep well injection layer of a conductivity type different from the semiconductor substrate to the same conductivity type as the semiconductor substrate. It must be prevented from forming under the shallow well injection layer (x in the table). In this case, as described above, it is necessary to perform a heat treatment between the implantation of the deep well implantation layer and the implantation of the shallow well implantation layer. Therefore, it is necessary to form a resist pattern twice before and after removing the silicon nitride film. There is.

Operation With this configuration, using double accelerated ion implantation,
The sheet resistance of a shallow well injection layer can be reduced without performing epitaxial growth. In addition, it is possible to accurately perform ion implantation to a predetermined region and a predetermined depth while preventing the effect of sputtering on the surface of the semiconductor substrate due to high-acceleration ion implantation, and to further reduce damage caused by ion implantation. As a result, an increase in manufacturing cost can be suppressed, and malfunction, leakage, and latch-up can be prevented. In addition, since the channel stopper is implanted into the well formation region in a step different from the well formation by the double high-acceleration ion implantation, the degree of freedom in the well structure design for obtaining predetermined characteristics even when the semiconductor device is highly integrated. This has the advantage of increasing

The following relates to a semiconductor device according to an embodiment of the present invention,
The manufacturing method will be described with reference to FIG.

FIG. 1 illustrates a method of forming a shallow well injection layer, a channel stopper injection layer, and a channel dope injection layer using the same mask after forming a deep well injection layer of the same conductivity type as the substrate. It was done. First
FIG. 1A shows a state in which an oxide film 2 and a silicon nitride film 3 are sequentially grown on a semiconductor substrate 1 and then the silicon nitride film 3 is etched according to a predetermined pattern. Next, as shown in FIG.
The field oxide film 4 is grown by COS. Thereafter, ion implantation is performed, and a deep well implantation layer 13 (about 1.
0-3.0 μm depth). This well injection layer 13
As is generally known, a portion having a high impurity concentration in an impurity distribution when ions are implanted with high energy is shown. The silicon nitride film 3 and the silicon oxide film 2 used for the mask are removed, and after the heat treatment (at 900 ° C. for 30 minutes), an oxide film for ion implantation (not shown) is formed. Next, as shown in FIG. 1 (c), after forming a first well resist mask 5, a first well injection layer 6 is formed by ion implantation.
(Approximately 0.5 to 1.5 μm depth), a channel stopper injection layer 7 (approximately 0.3 to 0.8 μm depth), and a channel dope injection layer 8 (approximately 0.1 to 0.3 μm depth). Next, as shown in FIG. 1 (d), after forming a second well resist mask 9, a second well implantation layer 10 (about 0.5 to 1.5 μm deep) and a channel stopper implantation layer 11 are also formed by ion implantation. (At a depth of about 0.3 to 0.8 μm) and a channel dope injection layer 12 (at a depth of about 0.1 to 0.3 μm) are simultaneously formed. This completes the well and element isolation steps.

Here, the first well injection layer 6 and the second well injection layer 10
It is formed of an impurity giving a conductivity type different from that of. Either the first well injection layer 6 or the second well injection layer 10 is not necessarily required and can be omitted if it is the same conductivity type as the semiconductor substrate 1.

FIG. 2 illustrates a method of forming a conductive deep well injection layer different from the substrate. FIG. 2A shows a state where the silicon oxide film 2 and the silicon nitride film 3 on the semiconductor substrate 1 are sequentially grown and then the silicon oxide film 3 is etched according to a predetermined pattern.

Next, as shown in FIG. 2B, a field oxide film 4 is grown by LOCOS in a region where the silicon nitride film 3 is not present. Thereafter, a predetermined resist pattern 14 is formed and ion implantation is performed, and a deep well implantation layer 13 is formed in a part of the semiconductor substrate 1.
(Approximately 1.0-3.0 μm depth). The silicon nitride film 3 and the silicon oxide film 2 used for the mask are removed, and after the heat treatment (at 900 ° C. for 30 minutes), an oxide film for ion implantation (not shown) is formed.

Next, as shown in FIG. 2C, after the first well resist mask 5 is formed, the first well injection layer 6 (about 0.5 to 1.5 μm deep) and the deep well injection layer 13 (about 0.5 to 1.5 μm deep) are formed by ion implantation. (Depth of about 1.0 to 3.0 μm). The deep well injection layer 13 and the first well injection layer 6 are of a conductivity type different from that of the semiconductor substrate 1. At the same time, the channel stopper injection layer 7
(Approximately 0.3-0.8 μm depth), channel dope injection layer 8
(Approximately 0.1-0.3 μm deep) at the same time. Next, as shown in FIG. 2D, after a second well resist mask 9 is formed, a second well implantation layer 10 (approximately 0.5 to 1.5 μm depth) and a channel stopper implantation layer 11 are similarly formed by ion implantation. (At a depth of about 0.3 to 0.8 μm) and a channel dope injection layer 12 (at a depth of about 0.1 to 0.3 μm) are simultaneously formed. Thus, the well injection layer and the element isolation process are completed.

Here, the first well injection layer 6 and the second well injection layer 10
It is formed of an impurity giving a conductivity type different from that of. In addition,
The second well injection layer 10 is not necessarily required and can be omitted if it is the same conductivity type as the semiconductor substrate 1. The order of the steps of the second well injection layer 6 and the second well injection layer 10 may be reversed. Further, in this embodiment, the deep well injection layer 13 is formed.
Although the first well implanted layer 6 is shallowly ion-implanted using the same mask, it is also possible to use a mask having a different pattern. At that time, the semiconductor substrate 1 and the semiconductor substrate 1
Any pattern may be used as long as the pattern is such that the shallow second well injection layer 10 of the same conductivity type as that described above is not divided.

The channel stopper injection layer 7 or 11 always has the same conductivity type as the well injection layer 6 or 10, but the channel dope injection layer 8 or 12 has a different conductivity type depending on the work function of the material to be the gate electrode.

Effects of the Invention As described above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to prevent the occurrence of sputtering or damage on the substrate surface due to high-acceleration ion implantation, and to reduce the sheet resistance of the well-implanted layer. As a result, the occurrence of junction leak current can be prevented, the performance of the element can be maintained, and malfunction and latch-up can be prevented.

[Brief description of the drawings]

1 (a) to 1 (d) are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are other embodiments of the present invention. 3 (a) to 3 (d) are process cross-sectional views for explaining a conventional semiconductor device and a method for manufacturing the same. 1 ... semiconductor substrate, 6 ... first well injection layer (shallow well), 13 ... deep well injection layer (deep well).

Claims (3)

(57) [Claims] A step of forming an oxidation-resistant mask in an element formation region on a semiconductor substrate; and a step of selectively growing an element isolation oxide film in a region of the semiconductor substrate that is not covered with the oxidation-resistant mask. A semiconductor device including a step of forming a deep first well by performing ion implantation through the oxidation resistant mask and the element isolation oxide film, and a step of forming a second well above the first well; Production method. A step of forming an oxidation-resistant mask in an element formation region on the semiconductor substrate; and a step of selectively growing an element isolation oxide film in a region of the semiconductor substrate which is not covered with the oxidation-resistant mask. Performing ion implantation through the oxidation-resistant mask and the element isolation oxide film to form a deep first well; and removing the oxidation-resistant mask.
A method for manufacturing a semiconductor device, comprising: a step of performing a heat treatment; and a step of forming a second well above the first well. A step of forming an oxidation-resistant mask in an element formation region on the semiconductor substrate; and a step of selectively growing an element isolation oxide film in a region of the semiconductor substrate that is not covered with the oxidation-resistant mask. Ion-implanting the entire surface through the oxidation-resistant mask and the element isolation oxide film to form a deep ion-implanted layer; and forming a well in a predetermined region of the semiconductor substrate and above the ion-implanted layer. A method for manufacturing a semiconductor device including: