JPH065791A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To protect a base region against damage due to etch back at the time of formation of side wall by forming the base region while exposing a silicon substrate providing the base region for a bipolar transistor. CONSTITUTION:Field oxide 6 is formed on a semiconductor substrate 1 except the region for forming the source.drain diffusion layer of MOS transistor and the region for forming the collector diffusion layer of bipolar transistor. Gate electrode 8 of the MOS transistor is then formed followed by formation of a lightly doped source.diffusion layer 9 through the use of the gate electrode 8. A side wall 10 is also formed for the gate electrode 8 and then the field oxide 6 is removed from the base region of the bipolar transistor. Subsequently, a heavily doped source-drain diffusion layer of the MOS transistor and the base 13 of the bipolar transistor are formed. This method protects the base region against damage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOS transistor and a bipolar transistor on the same semiconductor substrate.

[0002]

2. Description of the Related Art A conventional method for forming a MOS transistor and a bipolar transistor on the same semiconductor substrate is shown in FIG.
Will be explained. First, as shown in FIG.
An N type buried layer 2 and a P type buried layer 3 are formed in predetermined regions on the type silicon substrate 1, respectively. Next, the N-type epitaxial layer 4 is grown and boron is introduced into the N-type epitaxial layer 4 on the P-type buried layer 3 to form the P-well 5. Next, a field oxide film 6 is formed as an element isolation region. Further, a gate oxide film 7 is formed on the silicon substrate not covered with the field oxide film 6 by oxidation, and then polycrystalline silicon is grown, and this polycrystalline silicon is anisotropically etched into a predetermined shape. The gate electrode 8 is formed. And N channel M
By implanting phosphorus at a low dose with the gate electrode 8 as a mask only in the region to be an OS transistor, a low concentration N is obtained.
The mold diffusion layer 9 is formed.

Next, as shown in FIG. 3B, an oxide film is grown on the entire surface and anisotropically etched to form sidewalls 10 on the sidewalls of the gate electrode 8. Next, boron is implanted into the region serving as the base of the bipolar transistor to form the intrinsic base 13, and boron is implanted at a high dose into the base region in contact with the base electrode to form the graft base 15. Next, phosphorus is injected into the region in contact with the collector electrode to form the collector diffusion layer 16, and arsenic is injected into the MOS transistor portion and the collector portion at a high dose to form the high concentration N-type diffusion layer 14.

Next, as shown in FIG. 3C, an oxide film 31 is formed on the entire surface, and then the oxide film 31 on the intrinsic base 13 is opened to form an emitter contact 18. Next, polycrystalline silicon is grown, arsenic is implanted at a high dose, and then heat treatment is performed to remove the polycrystalline silicon by etching so as to cover the emitter contact 18 and the emitter extraction electrode 19
And An emitter diffusion layer 20 is formed on the surface of the intrinsic base 13 in contact with the emitter extraction electrode 19 by arsenic diffusion. By this manufacturing method, the LDD N-channel MOS transistor and the bipolar transistor are formed on the same semiconductor substrate.

[0005]

In the semiconductor device formed by such a conventional manufacturing method, it is necessary to form the side wall 10 on the side wall of the gate electrode 8 when forming the LDD type MOS transistor. The sidewall 10 is formed by anisotropically etching an oxide film grown on the entire surface. For this reason, during this etching back, the silicon substrate in the base region 13 of the bipolar transistor is damaged such as generation of lattice defects and interface states. Due to this damage, a recharge current is added to the base current of the completed bipolar transistor, which causes a problem that the electrical characteristics of the bipolar transistor are significantly impaired.

On the other hand, a method has been proposed in which the base region is covered with a resist at the time of etching back to reduce the damage, but there is a problem that the number of aligning steps in the photolithography technique for selectively forming the resist increases. is there. An object of the present invention is to provide a method for manufacturing a semiconductor device which prevents damage to the base region of a bipolar transistor and does not increase the number of manufacturing steps.

[0007]

The manufacturing method of the present invention is
A step of forming a field oxide film on the semiconductor substrate in a region excluding the source / drain diffusion layer of the OS transistor and a region of the bipolar transistor excluding the collector diffusion layer; a step of forming a gate electrode of the MOS transistor; A step of forming a low concentration source / drain diffusion layer using the electrodes, a step of forming a sidewall on a side wall of the gate electrode, a step of removing a field oxide film on a base region of a bipolar transistor,
Forming a high concentration source / drain diffusion layer of the OS transistor and a base of the bipolar transistor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, arsenic, boron and the like are ion-implanted and diffused into the N-type buried layer 2 and the P-type buried layer 3 in predetermined regions on the P-type silicon substrate 1, respectively. Form. Next, an N-type epitaxial layer 4 is grown on this to a thickness of about 2 μm, and the P-type buried layer 3 is formed.
Boron is added to the upper N-type epitaxial layer 4 by 5 × 10 ¹² (c
m ⁻² ) implantation and heat treatment are performed to form the P well 5. Next, a field oxide film 6 is formed as a device isolation region in a predetermined region by about 6000Å. At this time, the field oxide film 6 is also formed in the region that becomes the base of the bipolar transistor.
It is essential to form

Next, by processing in an oxygen atmosphere at 900 ° C., a 200 Å gate oxide film is formed on the silicon substrate not covered with the field oxide film 6. Further, polycrystalline silicon is grown at 4000 Å, and this is anisotropically etched into a predetermined shape to form the gate electrode 8. And N
Phosphorus 70KeV, 2 × 10 ¹³ (cm ^-2 ) with the gate electrode 8 as a mask only in the region to be the channel MOS transistor
By injecting, the low concentration N type diffusion layer 9 is formed.

Next, as shown in FIG. 1 (b), an oxide film of 2000 liters is formed by a chemical vapor deposition method, and this is anisotropically etched to form a sidewall 10 on the side wall of the gate electrode 8. Form. Next, after forming the first oxide film 11 of 600 Å by chemical vapor deposition, the first oxide film 11 and the field oxide film 6 on the base region are removed with hydrofluoric acid using the resist as a mask. After removing the resist, heat-treat it in an oxygen atmosphere at 900 ° C,
A 200 Å second oxide film 12 is formed. Then, boron is implanted at 10 KeV and 2 × 10 ¹³ (cm ⁻² ). At this time, boron is not implanted because there is a thick first oxide film on the silicon substrate other than the base region. Since only the thin second oxide film 12 is formed on the base region, boron is implanted. As a result, the intrinsic base 13 is formed.

Next, as shown in FIG. 1 (c), boron is implanted at 30 KeV, 5 × 10 ¹⁵ (cm ⁻² ) into the base region where the base electrode and the silicon substrate are in contact with each other by using the resist as a mask, and grafting is performed. The base 15 is formed. Further, the collector diffusion layer 16 is formed by implanting phosphorus at 100 KeV and 1E15 (cm ⁻² ) in a region where the collector electrode is in contact with the silicon substrate using the resist as a mask. Further, using the resist as a mask, arsenic is implanted into the N-channel MOS transistor portion and the collector portion at 150 KeV and 5 × 10 ¹⁵ (cm ⁻² ), thereby forming the high concentration N-type diffusion layer 14. Then, the entire surface is etched with hydrofluoric acid to the extent that the second oxide film 12 on the base region can be completely removed.

Then, as shown in FIG. 1D, a third oxide film 17 of 2000 Å is formed by a chemical vapor deposition method, and a hole is formed in the third oxide film 17 on the intrinsic base 13. The emitter contact 18 is formed. Next, polycrystalline silicon is grown to 2000 Å, arsenic is implanted at 40 KeV, 5E15 (cm ^-2 ), and then heat treatment is performed. Next, the emitter contact 1
Polycrystalline silicon is removed by etching so as to cover 8 and an emitter extraction electrode 19 is formed. An N-type emitter diffusion layer 20 is formed on the surface of the intrinsic base 13 in contact with the emitter extraction electrode 19 by arsenic diffusion. Further, the interlayer film 21
As a result, 8000 Å of BPSG is grown, and then a source electrode 22, a gate electrode 23, a drain electrode 24, a base electrode 25, an emitter electrode 26, and a collector electrode 27 are formed by forming holes at predetermined positions in the interlayer film 21 and providing electrodes. Form.

According to such a manufacturing method, after forming the sidewall 10 of the MOS transistor, the silicon substrate which becomes the base region 13 of the bipolar transistor is exposed on the surface. Therefore, the base region 13 is not damaged during the anisotropic etching for forming the sidewall 10. Therefore, a bipolar transistor with good characteristics can be realized. Moreover, in this embodiment, it is necessary to form a mask pattern in the step of removing the field oxide film on the base region.
Since the intrinsic base region is formed by full-face implantation, there is also an advantage that the number of aligning steps is the same as in the conventional example.

Next, a second embodiment of the present invention will be described. FIG. 2 is a sectional view showing the second embodiment in the order of manufacturing steps. First, since the forming method of FIG. 2A is the same as that of FIG. 1A of the first embodiment, the description thereof will be omitted. That is, the field oxide film 6 is formed also in the portion forming the base region of the bipolar transistor. Next, as shown in FIG. 2B, an oxide film is grown to 2000 Å by a chemical vapor deposition method and anisotropically etched to form a sidewall 10 on the side wall of the gate electrode 8. Next, the field oxide film 6 is etched with hydrofluoric acid using the resist 28 having an opening portion only in the base region as a mask. Continuing, using the resist 28 as a mask, boron 10 KeV, 2 × 10
^The intrinsic base region 13 is formed by implanting ¹³ (cm ⁻² ).

Next, as shown in FIG. 2C, heat treatment is performed in an oxygen atmosphere at 900 ° C. to form an oxide film 29 of about 200 Å on the silicon substrate. Then, using the resist as a mask, boron is implanted at 30 KeV, 5 × 10 ¹⁵ (cm ⁻² ) into the base region where the base electrode and the silicon substrate are in contact with each other, to form the graft base 15. Further, with the resist as a mask, phosphorus is added to the region where the collector electrode is in contact with the silicon substrate at 100 KeV,
By implanting 5 × 10 ¹⁵ (cm ^-2 ), the collector diffusion layer 1
6 is formed. Next, using the resist as a mask, arsenic is added to the N-channel MOS transistor section and the collector section at 100 KeV,
A high concentration N type diffusion layer 14 is formed by implanting 5 × 10 ¹⁵ (cm ⁻² ).

Next, as shown in FIG. 2D, after removing the 200 Å oxide film 29 on the silicon substrate with hydrofluoric acid,
An oxide film 30 is grown to 2000 Å by chemical vapor deposition, a hole is formed in the oxide film 30 on the intrinsic base 13, and an emitter contact 18 is formed. Next, polycrystalline silicon is grown to 2000 Å, arsenic is implanted at 40 KeV, 5E15 (cm ^-2 ), and then heat treatment is performed to etch the polycrystalline silicon so as to cover the emitter contact 18 and form an emitter extraction electrode 19. . Intrinsic base 13 in contact with emitter extraction electrode 19
An N type emitter diffusion layer 20 is formed on the surface by diffusion of arsenic.

In the manufacturing method of the second embodiment, the high concentration N type diffusion layer 14 and the graft base 1 of the MOS transistor are used.
Since the oxide film thickness on the silicon substrate can be made sufficiently thin to 200 Å or less at the time of ion implantation for forming No. 5, there is an advantage that the same ion implantation conditions as the conventional example can be used. Incidentally, since the thickness of the oxide film 11 on the silicon substrate was as thick as 600 Å in the first embodiment, it was necessary to change the implantation conditions from the conventional example. As a result, the characteristics of the MOS transistor can be made equal to those of the conventional example, the leakage of the base current can be reduced in the bipolar transistor, and the characteristics such as withstand voltage and speed can be made equal to those of the conventional example.

Further, the boron implantation for forming the intrinsic base 13 is performed with the silicon substrate exposed.
At this time, the substrate is damaged by the sidewall 10
It is sufficiently smaller than the etching back when forming. Therefore, this damage can be easily removed by, for example, wet etching the very surface silicon layer. It should be noted that in the above embodiments, the MOS transistor is described as an N-channel type only, but the same can be realized when a CMOS transistor including a P-channel type is formed.

[0019]

As described above, according to the manufacturing method of the present invention, after the sidewall of the LDD type MOS transistor is formed, the silicon substrate to be the base region of the bipolar transistor is exposed to form the base region. Therefore, the base region can be prevented from being damaged by etching back when the sidewall is formed. Therefore, since the bipolar transistor is formed on a clean silicon substrate without damage or contamination, it has an effect that good characteristics can be obtained. Moreover, the manufacturing method of the present invention does not increase the number of aligning steps as compared with the conventional steps, and has an effect that it can be realized by using the conventional mask pattern.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a conventional manufacturing method in process order.

[Explanation of symbols]

 1 P-type silicon substrate 4 N-type epitaxial layer 5 P-well 6 Field oxide film 8 Gate electrode 9 Low-concentration N-type diffusion layer 10 Sidewall 13 Intrinsic base 15 Graft base

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/336 29/784 7377-4M H01L 29/78 301 L

Claims (1)

[Claims] 1. An LDD type MOS on the same semiconductor substrate.
A method of manufacturing a semiconductor device having a transistor and a bipolar transistor, a step of forming a field oxide film on the semiconductor substrate in a region excluding a source / drain diffusion layer of a MOS transistor and a region excluding a collector diffusion layer of a bipolar transistor; A step of forming a gate electrode of a MOS transistor, a step of forming a low-concentration source / drain diffusion layer using this gate electrode, a step of forming a sidewall on a side wall of the gate electrode, A method of manufacturing a semiconductor device, comprising: a step of removing the field oxide film on a base region; and a step of forming a high concentration source / drain diffusion layer of a MOS transistor and a base of a bipolar transistor.