KR930008898B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The method is for improving the linear characteristic of DC forward current gain (hFE) of the bipolar transistor. To form the MOS transistor with a LDD (Lightly Doped Drain) structure, the residual oxide layer formed on the surface is dry etched with 200-500 angstroms of width, and the rest oxide layer is removed by wet etching process when forming the spacer formed on the side wall of the gate so that the oxide layer is removed regardless of the wafer position.

Description

Manufacturing Method of Semiconductor Device

1A to I are manufacturing process diagrams of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a bipolar transistor and a sea morph transistor are formed on the same substrate.

In recent years, electronic products such as home appliances have become light and thin, and high speed operation is required. Therefore, semiconductor devices having various functions are formed by forming devices having different functions or different driving voltages on the same chip. Racing on. In general, a semiconductor device in which a bipolar transistor and a CMOS transistor are formed in the same chip is referred to as biCMOS.

Bi-CMOS adopts a Lightly Doped Drain (LDD) structure to prevent breakdown voltage due to hot electrons in NMOS. That is, after forming gate electrodes on the N and P morph transistors, an oxide film having a thickness of about 2000 to 3000 mV is formed by a chemical vapor deposition (CVD) method, and the semiconductor substrate is exposed by a dry etching method such as reactive ion etching (RIE). Etch until a spacer is formed on sidewalls of the gate electrodes. Accordingly, since the ion is not implanted in the lower portion of the spacer for implantation of the drain regions and the impurity region of low concentration is formed during diffusion, the breakdown voltage is prevented from increasing.

However, when the oxide film is removed by a dry etching method such as RIE to form a spacer on the sidewalls of the gate electrodes of the N and P morph transistors, damage such as dislocations or the like on the surface of the substrate may be caused or equalization of the dry etching equipment. As a result, the degree of removal of the oxide film differs for each position in the wafer. The damage of the potential light causes the junction of the emitter and the base in the bipolar transistor to become unstable, thus degrading the linearity of the DC forward current gain (hFE), and also the dry etching equipment. Since the removal degree of the oxide film is different depending on the position in the wafer depending on the uniformity of, the hFE of the bipolar transistor is changed, thereby reducing the reliability. Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the linear characteristics of the hFE of a bipolar transistor.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a change in hFE according to the position of a chip in a wafer.

In order to achieve the above objects, the present invention provides a method of manufacturing a semiconductor device, comprising: first and second forming first and second buried layers of a second conductivity type in a predetermined portion of a semiconductor substrate of a first conductivity type; A first process of forming ion implantation regions, and diffusing ions of the first and second ion implantation regions to form first and second buried layers, and a third buried layer of a first conductivity type in the semiconductor substrate therebetween; Forming a third buried layer by diffusing ions of the third ion implanted region to form a third buried layer and forming a third buried layer on the surfaces of the first, second and third buried layers A third process of forming an epitaxial layer, a fourth process of forming first, second, and third wells in the same manner as the method of forming the first, second, and third buried layers in the epitaxial layer; A surface between the first, second and third wells Forming a field oxide films on a predetermined portion of the surface of the second well, and forming a collector region of a second conductivity type on the second well; forming a gate on the first and third wells; A sixth process of forming an oxide film on the substrate; a seventh process of first etching the oxide film with a predetermined thickness by dry etching; and a second etching of the remaining oxide film by wet etching to form spacers on sidewalls of the gates. An eighth process for forming and a ninth process for forming first and second conductive source and drain regions in the first and third wells, and simultaneously forming a first conductive base region in the second well; And forming a first intermediate oxide film on the entire surface of the structure described above, exposing a predetermined portion of the base region, forming an emitter connection region, and forming an emitter region of the second conductivity type by a self-matching method. 10th And an eleventh step of forming a second conductive oxide film and a passivation layer sequentially on the entire surface of the above-described structure, and then forming a metal conductive film through the contact hole.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are manufacturing process diagrams of a semiconductor device according to the present invention. Referring to FIG. 1A, the first pad oxide film 3, the first nitride film 5, and the photosensitive film are formed on the entire surface of the P-type semiconductor substrate 1 having a crystal surface of {100} and a specific resistance of about 2 to 20? After (7) is sequentially formed, a predetermined portion of the first pad oxide film 3 is exposed by a conventional photolithography method. Next, an N-type impurity such as Arsenic for forming N + buried layers in the exposed portion of the first pad oxide layer 3 may have energy of about 100 keV and 1 × 10 ^{15 to} 5 × 10 ¹⁵ ions / cm 2. The first and second ion implantation regions 9 and 11 are formed by implanting the same dose.

Referring to FIG. 1B, the second pad oxide film 13 is removed by thermally oxidizing an exposed portion of the first pad oxide film 3 using the first nitride film 5 as a mask after removing the photoresist film 7. Form. At this time, the ions of the first and second ion implantation regions 9 and 11 are diffused to form first and second buried layers 15 and 17. Next, boron (P +) is removed to form a buried layer of P + on the semiconductor substrate 1 under the first pad oxide film 3 by removing the first nitride film 5 and using the second pad oxide film 13 as a mask. P-type impurities such as Boron) are formed with the energy of about 100 keV and the dose of about 1 × 10 ^{13 to} 5 × 10 ¹³ ions / cm 2 to form the third ion implantation region 19.

Referring to FIG. 1C, after the ions in the third ion implantation region 19 are diffused to form a third buried layer 21, the first and second pad oxide layers 3 and 13 are removed. An epitaxial layer about 1.5 탆 thick is formed. Next, the first, second and third wells 23, 25, and 27 are formed. First and second wells (23) above, 25 is the (phosphorus), the N-type impurity such as, the third well 27 is adequate energy for P-type impurity such as boron and 1 × 10 ¹² ~3 × 10 ¹² ions / ㎠ degree of after the ion implantation dose to be heat-treated to form. Next, a third pad oxide layer 29 is formed on the surfaces of the first, second and third wells 23, 25, and 27.

Referring to FIG. 1D, field oxide layers 31 for defining active regions of respective devices are formed by a conventional LOCOS process. Subsequently, an energy of about 100 keV and ion implantation of about 3 × 10 ^{15 to} 5 × 10 ¹⁵ ions / cm 2 are applied to a predetermined portion of the third well 25 for forming a bipolar transistor, and then, 3 The pad oxide film 29 is removed.

Referring to FIG. 1E, a gate oxide film 35 having a thickness of about 200 to 500 mW and a gate 37 having a thickness of about 2000 to 3000 mW are formed on a predetermined portion of the first and third wells 23 and 27. Form. The gate 37 is formed of polycrystalline silicon or polycrystalline silicon and metal silicide. Next, a gate 37 is formed in the first and third wells 23 and 27 to form the monotransistors as a lightly doped drain (LDD) structure. Using a mask, P-type impurities such as boron and N-type impurities such as phosphorus are injected with appropriate energy and doses of about 1 × 10 ^{13 to} 5 × 10 ¹³ ions / cm 2, respectively to form the fourth and fifth ion implantation regions ( 39, 41 are formed. Subsequently, an oxide film 43 of about 2000 to 3000 Pa is formed on the entire surface of the structure described above by CVD or LTO (Low Temperature Oxide).

Referring to FIG. 1F, the oxide film 43 is removed by a dry etching method such as RIE until about 200 to 500 kPa is left to leave a residual oxide film 45. In this case, when the oxide layer 43 is removed by the RIE method, the surfaces of the first, second and third wells 23, 25, and 27 are damaged such as dislocations.

Referring to FIG. 1G, the residual oxide layer 45 is removed by a conventional wet etching method to expose the first, second and third wells 23, 25, and 27 of the active regions. In this case, spacers 47 are formed on sidewalls of the gates 37. Since the residual oxide film 45 is removed by the wet etching method, the surfaces of the first, second and third wells 23, 25, and 27 are not subjected to surface damage such as dislocations. In addition, since the oxide film 43 is removed except the residual oxide film 45 by a dry etching method such as RIE, the residual oxide film 45 is removed by a wet etching method, so that the oxide film 43 may be uniformly removed regardless of the position of the wafer. Can be. Next, a first interlayer oxide film 49 having a thickness of about 500 to 1500 Å is formed on the entire surface of the structure described above by CVD or LTO, and then the gates are formed on the first and third wells 23 and 27. Using the 37 as a mask, the 6th and 7th ion implantation regions 39 are ion-implanted with BF ² and phosphorus with a suitable energy and a dose of about 3 × 10 ^{15 to} 5 × 10 ¹⁵ ions / cm 2, respectively. 40 is formed. When the sixth ion implantation region 39 is formed, the seventh ion implantation region 57 is simultaneously formed in the region where the base region except for the emitter region of the bipolar transistor to be formed in the second well 25 is formed. . Then, the eighth ion implantation region 57 is ion-implanted by boron into the portion where the base region of the bipolar transistor is to be formed with an energy of about 80 keV and a dose of about 1 × 10 ¹³ to 2 × 10 ¹³ ions / cm 2. Form.

Referring to FIG. 1H, the first interlayer insulating film 49 over the portion where the emitter region of the bipolar transistor is to be formed is removed by conventional photolithography. At this time, the first interlayer insulating film 49 is exposed to a predetermined portion of the semiconductor substrate 1 by RIE, and then the semiconductor substrate 1 is dry-etched by plasma. The etching of the second well is performed by the RIE method. When the first interlayer oxide layer 49 is removed, the surface of the exposed second well 25 may be damaged, such as dislocations. Will remove surface damage. Next, after depositing polysilicon on the first interlayer oxide film 49, N-type impurities such as arsenic, which is an emitter source, are 5 × 10 ^{15 to} 8 × 10 ¹⁵ ions / cm 2. Ion implantation with degree of dose. Then, the polycrystalline silicon is patterned to form an emitter connection region 59, followed by a diffusion process, so that the source and drain regions 61 of the P MOS transistor and the source and drain regions of the N MOS transistor are formed. And the base region 65 of the bipolar transistor. At this time, an N-type impurity, such as an arsenic, doped in the emitter connection region 59 is diffused into a predetermined portion of the base region 65 to form an emitter region 67. In the above, the junction surface of the base region 65 and the emitter region 67 is stabilized to make the hFE linear characteristics of the bipolar transistor in operation good.

Referring to FIG. 1i, a first interlayer oxide film 69 of the CVD or HTO method is formed on the entire surface of the above-described structure. Subsequently, a passivation layer (71) is formed by applying a flowable PSG (Phospho Sillcate Glass) or BPSG (Boro-Phospho Silicate Glass) to the entire surface of the second interlayer oxide film 69. The contact hole is formed by a normal photolithography process. Then, metal conductive films 73 are formed through the contact hole.

As described above, when forming spacers on the sidewalls of the gates in order to form the MOS transistors LDD structure, the wet etching method does not remove all of the oxide film deposited on the front surface by dry etching, but leaves the thickness about 200 to 500 Å and removes the oxide film. By removing the rest, the surface of the semiconductor substrate is not damaged such as dislocations, and the oxide film can be uniformly removed regardless of the position of the wafer.

Therefore, the present invention can stabilize the bonding surface between the base and the emitter of the bipolar transistor to improve the linear characteristics of the hFE, and evenly remove the residual oxide film by the wet etching method, depending on the position of the wafer during the manufacturing process. There is an advantage to prevent the hFE from changing.

Claims (2)

A method of manufacturing a semiconductor device, comprising: a first process of forming first and second ion implantation regions for forming first and second buried layers of a second conductivity type in a predetermined portion of a semiconductor substrate of a first conductivity type; And a third ion implantation region for diffusing ions of the first and second ion implantation regions to form first and second buried layers, and forming a third buried layer of a first conductivity type in the semiconductor substrate therebetween. Forming a third buried layer by diffusing ions in the third ion implantation region and forming an epitaxial layer on the surfaces of the first, second and third buried layers; And a fourth process of forming first, second and third wells in the epitaxial layer by the same method as the first, second and third buried layers, and the first, second and third wells. Forming field oxide films on the surface and the predetermined portions between the wells, and A fifth step of forming a collector region of a second conductivity type in the second conductive layer, a sixth step of forming a gate over the first and third wells, and forming an oxide film on the entire surface thereof, and dry etching the oxide film by a dry etching method A seventh process of primary etching leaving only a predetermined thickness, an eighth process of secondary etching the remaining oxide film by a wet etching method to form spacers on sidewalls of the gates, and a first process in the first and third wells And a ninth step of forming a source and drain region of the second conductivity type and simultaneously forming a base region of the first conductivity type in the second well, and forming a first intermediate oxide film on the entire surface of the structure described above. A tenth step of exposing a predetermined portion of the base region to form an emitter connection region and forming an emitter region of a second conductivity type, and sequentially forming a second intermediate oxide film and a passivation layer on the entire surface of the structure described above. After forming method for manufacturing a semiconductor device consisting of the 11th step of forming a metal conductive layer through the contact hole. The method of claim 1, wherein in the seventh step, the first etching is performed until the oxide film is left at about 200 to 500 kV.