JPS56101778A - Preparation of insulated gate type semiconductor device - Google Patents

Preparation of insulated gate type semiconductor device

Info

Publication number
JPS56101778A
JPS56101778A JP488180A JP488180A JPS56101778A JP S56101778 A JPS56101778 A JP S56101778A JP 488180 A JP488180 A JP 488180A JP 488180 A JP488180 A JP 488180A JP S56101778 A JPS56101778 A JP S56101778A
Authority
JP
Japan
Prior art keywords
film layer
regions
insulating
resist
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP488180A
Other languages
Japanese (ja)
Inventor
Hideyoshi Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP488180A priority Critical patent/JPS56101778A/en
Publication of JPS56101778A publication Critical patent/JPS56101778A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

Abstract

PURPOSE:To match the positions of two regions automatically by forming source and drain regions after continuously etching an insulating film layer and a polycrystalline semiconductor film layer formed on a semiconductor substrate and implanting oxygen ions to form insulating and separating regions. CONSTITUTION:An insulating film layer 13 and a polycrystalline semiconductor film layer 14 formed on one conductive semiconductor substrate 12 are continuously etched using a resist 15 as a mask. Next, by implanting oxygen ions using the resist 15 as a mask, insulating and separating regions 17 are formed. Then removing the resist and using the polycrystalline semiconductor film layer 14 as a mask, a source region 18 and a drain region 19 are formed on the semiconductor substrate 12. By so doing, insulating and separating regions and source and drain regions can be formed self-matchingly without using LOCOS method and yet the number of masks can be reduced.
JP488180A 1980-01-18 1980-01-18 Preparation of insulated gate type semiconductor device Pending JPS56101778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP488180A JPS56101778A (en) 1980-01-18 1980-01-18 Preparation of insulated gate type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP488180A JPS56101778A (en) 1980-01-18 1980-01-18 Preparation of insulated gate type semiconductor device

Publications (1)

Publication Number Publication Date
JPS56101778A true JPS56101778A (en) 1981-08-14

Family

ID=11596011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP488180A Pending JPS56101778A (en) 1980-01-18 1980-01-18 Preparation of insulated gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56101778A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604370A (en) * 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604370A (en) * 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
US5789269A (en) * 1995-07-11 1998-08-04 Advanced Micro Devices, Inc. Field implant for semiconductor device

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