JPS5559775A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS5559775A
JPS5559775A JP13227478A JP13227478A JPS5559775A JP S5559775 A JPS5559775 A JP S5559775A JP 13227478 A JP13227478 A JP 13227478A JP 13227478 A JP13227478 A JP 13227478A JP S5559775 A JPS5559775 A JP S5559775A
Authority
JP
Japan
Prior art keywords
metallic layer
gate electrode
semiconductor device
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13227478A
Other languages
Japanese (ja)
Other versions
JPS6145868B2 (en
Inventor
Hiroshi Tokunaga
Koichi Nishiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13227478A priority Critical patent/JPS5559775A/en
Publication of JPS5559775A publication Critical patent/JPS5559775A/en
Publication of JPS6145868B2 publication Critical patent/JPS6145868B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To readily establish the boundaries among a source region, a drain region and a channel region by forming an off-set gate at a gate electrode and using a self- alignment type in a semiconductor device.
CONSTITUTION: A gate insulator film 2 is formed on a P-type silicon substrate 1 to thereby form an N-type channel region 11 therein. Then, a metallic layer 21 is coated on the film 2, and a resist 22 and a metallic layer 23 are sequentially deposited thereon. The, the metallic layer 33 corresponding to the portion except for a gate electrode 24 is removed by an etching process to thereby form a gate electrode 23 and a undercut metallic layer 21 thereon. Then, a source region and a drain region 13, 14 are formed by an ion implantation process therein.
COPYRIGHT: (C)1980,JPO&Japio
JP13227478A 1978-10-27 1978-10-27 Method of fabricating semiconductor device Granted JPS5559775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13227478A JPS5559775A (en) 1978-10-27 1978-10-27 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13227478A JPS5559775A (en) 1978-10-27 1978-10-27 Method of fabricating semiconductor device

Publications (2)

Publication Number Publication Date
JPS5559775A true JPS5559775A (en) 1980-05-06
JPS6145868B2 JPS6145868B2 (en) 1986-10-09

Family

ID=15077440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13227478A Granted JPS5559775A (en) 1978-10-27 1978-10-27 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS5559775A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366988B2 (en) 2015-08-14 2019-07-30 International Business Machines Corporation Selective contact etch for unmerged epitaxial source/drain regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366988B2 (en) 2015-08-14 2019-07-30 International Business Machines Corporation Selective contact etch for unmerged epitaxial source/drain regions

Also Published As

Publication number Publication date
JPS6145868B2 (en) 1986-10-09

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