JPH01134914A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01134914A
JPH01134914A JP29173587A JP29173587A JPH01134914A JP H01134914 A JPH01134914 A JP H01134914A JP 29173587 A JP29173587 A JP 29173587A JP 29173587 A JP29173587 A JP 29173587A JP H01134914 A JPH01134914 A JP H01134914A
Authority
JP
Japan
Prior art keywords
film
substrate
impurity
layer
containing film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29173587A
Other languages
Japanese (ja)
Inventor
Kiyoshi Irino
清 入野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29173587A priority Critical patent/JPH01134914A/en
Publication of JPH01134914A publication Critical patent/JPH01134914A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a buried collector layer by a method wherein a window is provided by conducting an anisotropic etching method on a two-layer film, the surface of a substrate is isotropically etched, impurities are diffused into the substrate and an oxide film is formed on the surface of the substrate with a mask used only once. CONSTITUTION:The second conductive type impurity containing film 12 and a film 13, which becomes a mask material, are deposited on the first conductive type semiconductor substrate 11. A window is provided by conducting anisotropical etching on a two-layer deposited film, isotropical etching is conducted on the surface of the substrate 11 through the window 15, and a recessed part 16 is formed on the substrate 11. The second conductive type diffusion layer 17 is formed by diffusing the impurities contained in the impurity- containing film 12 into the substrate 11, and an oxide film 18 is formed on the surface of the exposed substrate 11. The first conductive type impurities are diffused into the substrate 11 through the intermediary of the oxide film 18. The film 13 which becomes a mask material, the oxide film 18 and the impurity-containing film 12 are removed. An epitaxial layer 20 is grown. As a result, a buried collector layer is formed by using a mask only once.

Description

【発明の詳細な説明】 〔m要〕 半導体装置の埋込みコレクタの拡散と、埋込みコレクタ
層の認識のための段差を形成する方法に関し、 従来よりもマスク数を減らしより簡単な工程で埋込みコ
レクタ層とそれの認識のための段差を形成する方法を提
供することを目的とし、第1導電型半導体基板の上に第
2導電型不純物含有膜およびマスク材となる膜を堆積す
る工程、前記2層に堆積した膜を異方性エツチングして
これらの膜を通して窓を開口し、窓を通して半導体基板
の表面に等方性エツチングで行い、該基板に凹部を形成
する工程、前記不純物含有膜の含む不純物を基板へ拡散
し第2導電型拡散層を作り、露出した基板表面に酸化膜
を形成する工程、第1導電型不純物を酸化膜を通して基
板へ拡散する工程、マスク材となる膜と酸化膜および不
純物含有膜を除去する工程、およびエピタキシャル層を
成長する工程を含むことを特徴とする半導体装置の製造
方法を含み構成する。
[Detailed Description of the Invention] [Required] Regarding a method for diffusing a buried collector in a semiconductor device and forming a step for recognizing the buried collector layer, the buried collector layer can be formed using a simpler process with fewer masks than before. and a step of depositing a second conductivity type impurity-containing film and a film serving as a mask material on a first conductivity type semiconductor substrate; a process of anisotropically etching the films deposited on the substrate to open windows through these films, and isotropically etching the surface of the semiconductor substrate through the windows to form a recess in the substrate; impurities contained in the impurity-containing film; a step of diffusing impurities into the substrate to form a second conductivity type diffusion layer and forming an oxide film on the exposed surface of the substrate; a step of diffusing the first conductivity type impurity into the substrate through the oxide film; The present invention includes a method for manufacturing a semiconductor device characterized by including a step of removing an impurity-containing film and a step of growing an epitaxial layer.

〔産業上の利用分野) 本発明は、半導体装置の埋込みコレクタの拡散\ と、埋込みコレクタ層の認識のための段差を形成する方
法に関する。
[Industrial Application Field] The present invention relates to diffusion of a buried collector in a semiconductor device and a method of forming a step for recognition of a buried collector layer.

〔従来の技術〕[Conventional technology]

半導体装置の製造においては、半導体基板に埋込みコレ
クタ層と当該コレクタ層の認識のための段差を形成する
ことが行われる。それを第3図を参照して説明すると、
同図(a)に示される如く半導体基板31上に砒素、ア
ンチモンなどをドープしたガラスの如き不純物含有膜3
2、二酸化シリコン(5i02)膜33を順に成長する
In manufacturing a semiconductor device, a buried collector layer and a step for recognizing the collector layer are formed in a semiconductor substrate. To explain this with reference to Figure 3,
As shown in FIG. 3A, an impurity-containing film 3 such as glass doped with arsenic, antimony, etc. is formed on a semiconductor substrate 31.
2. Sequentially grow a silicon dioxide (5i02) film 33.

次に、これらの膜(31,33)を同図(blに示され
る如く形成されるべき埋込みコレクタ層の拡がりに対応
してパターニングし、不純物含有膜と5i02)模との
島34を作る。
Next, these films (31, 33) are patterned corresponding to the spread of the buried collector layer to be formed as shown in FIG.

次いで、熱酸化と不純物含有膜32中の不純物の拡散(
drive−in)を行うと、基板表面上にSiO2膜
35膜形5され、かつ、半導体基板中にN+型の不純物
拡散層36が作られる。
Next, thermal oxidation and diffusion of impurities in the impurity-containing film 32 (
When drive-in is performed, a SiO2 film 35 is formed on the surface of the substrate, and an N+ type impurity diffusion layer 36 is formed in the semiconductor substrate.

以下、島34、SiO+膜34全34し、再度全面に5
i02IQを形成し、形成されるコレクタ層の認識のた
めの位置合せ用5i02B’Aの島を前記5i02B’
Aのパターニングによって形成し、チャネルカット用の
P+型拡散層を形成するためにポロンイオン(B+)を
イオン注入し、全面に単結晶シリコンをエピタキシャル
成長すると、このエピタキシャル成長した層の下に埋込
みコレクタ層が形成される。
Below, the island 34, the SiO+ film 34 are all 34, and the entire surface is covered again with 5
i02IQ and the island 5i02B'A for alignment for recognition of the collector layer to be formed.
Formed by patterning A, implanted with boron ions (B+) to form a P+ type diffusion layer for channel cut, and epitaxially grown single crystal silicon on the entire surface, a buried collector layer is formed under this epitaxially grown layer. It is formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記した方法で埋込みコレクタの拡散を不純物含有膜か
ら選択的に拡散させ、しかも位置合せ用の5i02の段
差(島)を形成し、コレクタ層とチャネルカット層とを
離して形成することによりIs耐圧をある程度以上保と
うとすると、工程が長くなり、マスクも増える問題があ
る。
By selectively diffusing the buried collector from the impurity-containing film using the method described above, forming a 5i02 step (island) for alignment, and forming the collector layer and channel cut layer apart, the Is breakdown voltage If we try to maintain this above a certain level, the process becomes longer and the number of masks increases.

そこで本発明は、従来よりもマスク数を減らしより簡単
な工程で埋込みコレクタ層とそれの認識のための段差を
形成する方法を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of forming a buried collector layer and a step for recognizing the buried collector layer using a simpler process by reducing the number of masks than the conventional method.

C問題点を解決するための手段〕 上記問題点は、第1導電型半導体基板の上に第2導電型
不純物含有膜およびマスク材となる膜を堆積する工程、
前記2層に堆積した膜を異方性エツチングしてこれらの
膜を通して窓を開口し、窓を通して半導体基板の表面に
等方性エツチングで行い該基板に凹部を形成す名工程、
前記不純物含有膜の含む不純物を基板へ拡散し第2導電
型拡散層を作り、露出した基板表面に酸化膜を形成する
工程、第1導電型不純物を酸化膜を通して基板へ拡散す
る工程、マスク材となる膜と酸化膜および不純物含有膜
を除去する工程、およびエピタキシャル層を成長する工
程を含むことを特徴とする半導体装置の製造方法によっ
て解決される。
Means for Solving Problem C] The above problem is solved by the step of depositing a second conductivity type impurity-containing film and a film serving as a mask material on a first conductivity type semiconductor substrate;
a famous step of anisotropically etching the films deposited in the two layers to open a window through these films, and isotropically etching the surface of the semiconductor substrate through the window to form a recess in the substrate;
A step of diffusing the impurity contained in the impurity-containing film into the substrate to form a second conductivity type diffusion layer and forming an oxide film on the exposed surface of the substrate, a step of diffusing the first conductivity type impurity into the substrate through the oxide film, and a mask material. The present invention is solved by a method for manufacturing a semiconductor device characterized by including a step of removing a film, an oxide film, and an impurity-containing film, and a step of growing an epitaxial layer.

〔作用〕[Effect]

本発明においては、(1)半導体基板上に不純物含有膜
を堆積し、さらに前記膜の上にCVD法で5in2股を
成長し、(2)前記膜を異方性エツチングし、次いで半
導体基板を等方性エツチングし、(3)露出した半導体
基板表面を酸化し、同時に不純物を半導体基板の表面に
拡散させ、(4)チャネルカット用の不純物を薄く酸化
した領域のみにドープし、(5)酸化膜と不純物含有膜
を除去し、(6)シかる後にエピタキシャル成長するも
ので、マスクの使用は1回だけですみ、かつ、拡散層(
コレクタ層)認識のための位置合せマークはセルファラ
イン(自己整合)方式で形成される。
In the present invention, (1) an impurity-containing film is deposited on a semiconductor substrate, a 5-inch two-layer film is grown on the film by CVD, (2) the film is anisotropically etched, and then the semiconductor substrate is etched. (3) oxidize the exposed semiconductor substrate surface and at the same time diffuse impurities into the semiconductor substrate surface; (4) dope only the thinly oxidized region with impurities for channel cutting; (5) This method removes oxide films and impurity-containing films, and performs epitaxial growth after (6) oxidation, so a mask only needs to be used once, and the diffusion layer (
The alignment marks for recognition (collector layer) are formed by a self-alignment method.

〔実施例〕〔Example〕

以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

第1図に本発明実施例の工程を断面図で示す。FIG. 1 shows a cross-sectional view of the process of an embodiment of the present invention.

第1図(a)参照: P型の半導体(シリコン)基板11上に従来例と同様に
不純物含有膜12を1000人〜1500人の膜厚に堆
積し、その上にCVD法でマスク材となるSiO2膜1
3全1300人〜4000人の膜厚に成長する。レジス
ト膜14を5i02膜13上に形成し、それを図に点線
で示す如くにバターニングする。
Refer to FIG. 1(a): As in the conventional example, an impurity-containing film 12 is deposited on a P-type semiconductor (silicon) substrate 11 to a thickness of 1,000 to 1,500 wafers, and a mask material and a mask material are deposited thereon by CVD. SiO2 film 1
3 will grow to a total thickness of 1,300 to 4,000 people. A resist film 14 is formed on the 5i02 film 13 and patterned as shown by dotted lines in the figure.

第1図(bl参照: 異方性エツチングで5i02膜13、不純物含有膜12
をエツチングして窓15を窓開けする。レジスト膜14
はそのままに残して、例えばウェットエツチングで半導
体基板を等友釣にエツチングし、半導体基板に凹部15
を形成し、しかる後にレジスト膜14を除去する。この
等方性エツチングで不純物含有膜12の下方の基板の一
部がひさし状にえぐられて除去されるので、後の工程で
形成されるN”b層とP”b層とがぶつかることが防止
され、さらにはウェットエツチングを用いると、基板表
面がドライエツチングの場合の如くダメージを受けるこ
とがなく、後の工程で成長するエピタキシャル層にダメ
ージが入らない利点がある。
Figure 1 (see BL: 5i02 film 13, impurity-containing film 12 by anisotropic etching)
Etch and open window 15. Resist film 14
The semiconductor substrate is uniformly etched using wet etching, for example, to form recesses 15 in the semiconductor substrate.
is formed, and then the resist film 14 is removed. By this isotropic etching, a part of the substrate below the impurity-containing film 12 is hollowed out and removed, so that the N''b layer and the P''b layer, which will be formed in a later step, will not collide. Moreover, when wet etching is used, the substrate surface is not damaged as in the case of dry etching, and there is an advantage that the epitaxial layer grown in a later step is not damaged.

第1図(C1参照: 不純物含有膜中の不純物を基板表面にドライブインする
アニールを行うと、半導体基板11の表面層にN+型広
拡散層N” b層)17が形成される一方で、露出した
基板の表面に5i02膜18が形成される。次の工程で
5iOz膜18を通してイオン注入するので、それに対
し基板表面を保護する必要のあるときは、基板表面にS
iO2膜18全18形成し、しかる後にドライブインを
実施する。
FIG. 1 (See C1: When annealing is performed to drive-in the impurities in the impurity-containing film to the substrate surface, an N+ type wide diffusion layer N''b layer) 17 is formed on the surface layer of the semiconductor substrate 11, while A 5i02 film 18 is formed on the exposed surface of the substrate.In the next step, ions will be implanted through the 5iOz film 18, so if it is necessary to protect the substrate surface, S is added to the substrate surface.
A total of 18 iO2 films 18 are formed, and then drive-in is performed.

第1図(d)参照: 不純物含有膜12.5i02膜13をマスクにしてボロ
ンイオン(B1)をSiO2膜18全18てイオン注入
すると、SiO2膜18全18みに選択的にB+(図に
模式的に破線19で示す)が打ち込まれる。
Refer to FIG. 1(d): When boron ions (B1) are implanted into all 18 of the SiO2 films 18 using the impurity-containing film 12.5i02 film 13 as a mask, B+ (as shown in the figure) is selectively implanted into all 18 of the SiO2 films 18. (schematically indicated by a broken line 19) is inserted.

第1図(e)参照: 5i02膜13.1B、不純物含有膜12を除去し、エ
ピタキシャル層20を成長すると、エピタキシャル層2
0の表面には凹部16に対応した凹部21が形成され、
この凹部21がN+型広拡散層コレクタ層)17の認識
用の位置合せマークとなる。なお、B1がイオン注入さ
れた部分にはP型のチャネルカット層(P” b層)2
2がエピタキシャル成長の際の熱によって形成される。
Refer to FIG. 1(e): When the 5i02 film 13.1B and the impurity-containing film 12 are removed and the epitaxial layer 20 is grown, the epitaxial layer 2
A recess 21 corresponding to the recess 16 is formed on the surface of 0,
This recess 21 serves as an alignment mark for recognition of the N+ type wide diffusion layer (collector layer) 17. In addition, a P-type channel cut layer (P"b layer) 2 is formed in the part where B1 is ion-implanted.
2 is formed by heat during epitaxial growth.

上記した方法では、マスクはレジスト膜14のパターニ
ングのときにのみ使用されるもので、工程が従来例より
も簡単になり、半導体基板の凹部形\ 成にはウェットエツチングを用いるので基板へのダメー
ジは少な(なり、また安価な不純物をドープしたガラス
で不純物含有膜を作るのでコストが低減される利点があ
る。
In the above method, the mask is used only when patterning the resist film 14, making the process simpler than in the conventional method, and wet etching is used to form the recesses on the semiconductor substrate, so there is no damage to the substrate. Moreover, since the impurity-containing film is made of glass doped with inexpensive impurities, there is an advantage that the cost is reduced.

本発明の他の実施例においては、不純物含有膜を用いる
代りに、半導体基板表面に不純物をイオン注入するもの
で、その工程は、+1)基板に全面に埋込みコレクタ層
(N”b)形成のためのイオン注入をなし、800℃〜
900℃の低温酸化を行い、しかる後に酸化膜と基板の
エツチングを行い、(2)酸化とN”bアニールを行っ
てN”bの拡散を行い、チャネルカット用のP+bが必
要な場合にはp”bのイオン注入をなし、酸化膜を除去
した後にエピタキシャル成長を行う。この方法では、N
”bイオン注入の後に基板全面を酸化するので、酸化時
の結晶欠陥の発生がなく、N”b層とp”b層とが高濃
度で接触しないので、Is  耐圧が向上する。
In another embodiment of the present invention, instead of using an impurity-containing film, impurity ions are implanted into the surface of the semiconductor substrate, and the steps include: +1) forming a buried collector layer (N"b) on the entire surface of the substrate; 800℃~
Perform low-temperature oxidation at 900°C, then etch the oxide film and substrate, (2) perform oxidation and N"b annealing to diffuse N"b, and if P+b for channel cut is required. After ion implantation of p''b and removal of the oxide film, epitaxial growth is performed.
Since the entire surface of the substrate is oxidized after the ``b'' ion implantation, no crystal defects occur during oxidation, and the N''b layer and the p''b layer do not come into contact with each other at a high concentration, so that the Is breakdown voltage is improved.

第2図にこの実施例の工程を断面で示す。FIG. 2 shows the steps of this embodiment in cross section.

第2図fa)参照: P型シリコン基板11の表面にN型不純物(砒素。See Figure 2 fa): N-type impurities (arsenic) are added to the surface of the P-type silicon substrate 11.

アンチモンなど)を高濃度にイオン注入する。イオン注
入されたN++不純物は同図に模式的に破線23で示す
Antimony, etc.) is ion-implanted at a high concentration. The ion-implanted N++ impurity is schematically indicated by a broken line 23 in the figure.

第2図(b)参照: 基板表面を酸化し5i02膜24を形成し、注入したN
+型の不純物を5iO211Q24中に取り込む。
See Figure 2(b): The substrate surface is oxidized to form a 5i02 film 24, and the injected N
Incorporate + type impurities into 5iO211Q24.

SiO+膜24は第2図(elを参照して説明するイオ
ン注入においてマスク材として働く。
The SiO+ film 24 serves as a mask material in the ion implantation described with reference to FIG. 2 (el).

第2図(C)参照: 図示しないレジスト膜を用いて5iOz膜24をパター
ニングし、等方性エツチングで基板11をエツチングし
て基板に凹部16を形成する。なお、マスクはここで1
度使用されるだけである。この凹部は、位置合せマーク
の形成と、N”b層とP+6層とを離す(シフトさせる
)効果がある。
Refer to FIG. 2(C): The 5iOz film 24 is patterned using a resist film (not shown), and the substrate 11 is etched by isotropic etching to form a recess 16 in the substrate. In addition, the mask is 1 here.
It is only used once. This recess has the effect of forming alignment marks and separating (shifting) the N''b layer and the P+6 layer.

第2図(dl参照: 酸化によって基板表面に5iOz膜18を形成し、ドラ
イブインのためのアニールによって5i02膜24に含
まれるN型不純物を基板表面に拡散させてN”b層17
を形成する。
FIG. 2 (see dl) A 5iOz film 18 is formed on the substrate surface by oxidation, and an N-type impurity contained in the 5i02 film 24 is diffused into the substrate surface by drive-in annealing to form an N''b layer 17.
form.

第2図(el参照: SiO2膜18を通してP型不純物をイオン注入する。Figure 2 (see el: P-type impurity ions are implanted through the SiO2 film 18.

このとき、 SiO2膜24はマスクとして働く。At this time, the SiO2 film 24 acts as a mask.

注入されたP型不純物は図に模式的に破線19で示す。The implanted P-type impurity is schematically indicated by a broken line 19 in the figure.

第2図(f)参照: SiO2膜(24,18)を除去し、エピタキシャル層
20を成長すると、凹部16に対応する凹部21がエピ
タキシャル層の表面に形成され、それは第1図の実施例
の場合と同じく位置合せマークとなり、基板中にはチャ
ネルカット層(P” b層)22が形成される。
See FIG. 2(f): When the SiO2 film (24, 18) is removed and the epitaxial layer 20 is grown, a recess 21 corresponding to the recess 16 is formed on the surface of the epitaxial layer, which is the same as in the embodiment of FIG. As in the case, the channel cut layer (P"b layer) 22 is formed in the substrate as an alignment mark.

この実施例では、第1実施例の不純物含有膜に代るもの
をN+型不純物のイオン注入によって形成するので、制
御性、再現性が良くなる利点がある。
In this embodiment, since the impurity-containing film of the first embodiment is formed by ion implantation of N+ type impurities, there is an advantage that controllability and reproducibility are improved.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、マスクの使用が1回です
み、N”b層とP+6層の高濃度領域がぶつからないの
で耐圧が向上し、位置合せマークが結晶欠陥を誘起する
ことなく形成される効果がある。
As described above, according to the present invention, the mask only needs to be used once, the high concentration regions of the N''b layer and the P+6 layer do not collide, so the withstand voltage is improved, and the alignment marks do not induce crystal defects. It has the effect of being formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(clは本発明実施例断面図、第2図+
a)〜(f)は本発明の他の実施例の断面図、第3図(
al〜(0)は従来例断面図である。 第1図と第2図において、 11はシリコン基板、 12は不純物含有膜、 13は 5iOz膜、 14はレジスト膜、 15は窓、 16は凹部、 17はN”b層、 18は 5i02膜、 19はB+イオン、 −20はエピタキシャル層、 21は凹部、 22はp”b層、 23はN+型不純物、 24は 5i02膜 を示す。 特許出願人   富士通株式会社 代理人弁理士  久木元   彰 1トヌ−1,蛸りにツヤi4夕°1断C1】口≧1第1
11 (廃8R侵5セ例斬動目 ト滌唄のA亡め賀鞄JJ’lの昭品囚 牟廃明の硬の笑抛伊1肖断山凪 12図 イーヒJ4!’II片ff1ε区】 第3図
Figures 1(a) to (cl are sectional views of embodiments of the present invention, Figure 2+
a) to (f) are sectional views of other embodiments of the present invention, and FIG.
al~(0) is a sectional view of a conventional example. 1 and 2, 11 is a silicon substrate, 12 is an impurity-containing film, 13 is a 5iOz film, 14 is a resist film, 15 is a window, 16 is a recess, 17 is an N''b layer, 18 is a 5i02 film, 19 is a B+ ion, -20 is an epitaxial layer, 21 is a recess, 22 is a p''b layer, 23 is an N+ type impurity, and 24 is a 5i02 film. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Kukimoto 1 Tonu - 1, Takori ni Tsuya i4 E° 1 Cut C1] Mouth ≧ 1 1st
11 (Abandoned 8R invasion 5th example Zandome to 滌uta's A death bag JJ'l's Akishina prisoner Aimei's hard laugh 抛い 1 减切山耪 12 fig. Ehi J4! 'II piece ff 1 ε District] Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)第1導電型半導体基板(11)の上に第2導電型
不純物含有膜(12)およびマスク材となる膜(13)
を堆積する工程、 前記2層に堆積した膜を異方性エッチングしてこれらの
膜を通して窓(15)を開口し、窓(15)を通して半
導体基板(11)の表面に等方性エッチングを行い該基
板に凹部(16)を形成する工程、前記不純物含有膜(
12)の含む不純物を基板へ拡散し第2導電型拡散層(
17)を作り、露出した基板表面に酸化膜(18)を形
成する工程、第1導電型不純物を酸化膜(18)を通し
て基板へ拡散する工程、 マスク材となる膜(13)と酸化膜(18)および不純
物含有膜(12)を除去する工程、およびエピタキシャ
ル層(20)を成長する工程を含むことを特徴とする半
導体装置の製造方法。
(1) A second conductivity type impurity-containing film (12) and a film serving as a mask material (13) on the first conductivity type semiconductor substrate (11)
a step of anisotropically etching the films deposited in the two layers to open a window (15) through these films, and isotropically etching the surface of the semiconductor substrate (11) through the window (15); The step of forming a recess (16) in the substrate, the step of forming the impurity-containing film (
12) is diffused into the substrate to form a second conductivity type diffusion layer (
17) and forming an oxide film (18) on the exposed surface of the substrate; a step of diffusing the first conductivity type impurity into the substrate through the oxide film (18); 18) A method for manufacturing a semiconductor device, comprising the steps of: removing the impurity-containing film (12); and growing an epitaxial layer (20).
(2)前記した不純物含有膜(12)とマスク材となる
膜(13)に代えて半導体基板(11)表面に設けられ
た導電型不純物(23)を含有するマスク材を利用する
ことからなる特許請求の範囲第1項記載の方法。
(2) Instead of the impurity-containing film (12) and the film (13) serving as a mask material, a mask material containing conductive impurities (23) provided on the surface of the semiconductor substrate (11) is used. A method according to claim 1.
JP29173587A 1987-11-20 1987-11-20 Manufacture of semiconductor device Pending JPH01134914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29173587A JPH01134914A (en) 1987-11-20 1987-11-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29173587A JPH01134914A (en) 1987-11-20 1987-11-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01134914A true JPH01134914A (en) 1989-05-26

Family

ID=17772721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29173587A Pending JPH01134914A (en) 1987-11-20 1987-11-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01134914A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5456357A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor device
JPS5456381A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor device
JPS58196017A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Manufacture of semiconductor device
JPS5939042A (en) * 1982-08-27 1984-03-03 Fujitsu Ltd Manufacture of semiconductor device
JPS61115336A (en) * 1984-11-05 1986-06-02 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Improved method of making trench in integrated circuit construction
JPS62118529A (en) * 1985-11-19 1987-05-29 Sanyo Electric Co Ltd Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5456357A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor device
JPS5456381A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor device
JPS58196017A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Manufacture of semiconductor device
JPS5939042A (en) * 1982-08-27 1984-03-03 Fujitsu Ltd Manufacture of semiconductor device
JPS61115336A (en) * 1984-11-05 1986-06-02 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Improved method of making trench in integrated circuit construction
JPS62118529A (en) * 1985-11-19 1987-05-29 Sanyo Electric Co Ltd Manufacture of semiconductor device

Similar Documents

Publication Publication Date Title
US4600445A (en) Process for making self aligned field isolation regions in a semiconductor substrate
JPS6252950B2 (en)
JPH01134914A (en) Manufacture of semiconductor device
JP2833500B2 (en) Method for manufacturing surface tunnel transistor
JPH0231468A (en) Manufacture of floating gate type semiconductor memory device
JP2581548B2 (en) Method for manufacturing semiconductor device
GB1595548A (en) Method for preparing a substrate surface of and a method of making a semiconductor device
JPS61208271A (en) Manufacture of mis type semiconductor device
KR100233264B1 (en) Manufacturing method of analog semiconductor device
JPS6037614B2 (en) Manufacturing method of semiconductor device
JPH0335528A (en) Manufacture of semiconductor device
JPH06188259A (en) Manufacture of semiconductor device
JP2722829B2 (en) Method for manufacturing semiconductor device
JP3232161B2 (en) Method for manufacturing semiconductor device
JPH04278586A (en) Manufacture of semiconductor device
JPH0191433A (en) Semiconductor device and manufacture thereof
JPH06232154A (en) Manufacture of semiconductor device
JPH02148847A (en) Manufacture of semiconductor device
JPS61269375A (en) Manufacture of semiconductor device
JPS59217337A (en) Manufacture of semiconductor device
JPH07135256A (en) Manufacture of semiconductor device
JPS61147575A (en) Manufacture of semiconductor device
JPH09181189A (en) Manufacture of semiconductor device
JPS6195542A (en) Manufacture of semiconductor device
JPH02338A (en) Manufacture of semiconductor integrated circuit device