JPS57113249A - Manufacutre of semiconductor device - Google Patents

Manufacutre of semiconductor device

Info

Publication number
JPS57113249A
JPS57113249A JP18797080A JP18797080A JPS57113249A JP S57113249 A JPS57113249 A JP S57113249A JP 18797080 A JP18797080 A JP 18797080A JP 18797080 A JP18797080 A JP 18797080A JP S57113249 A JPS57113249 A JP S57113249A
Authority
JP
Japan
Prior art keywords
film
mask
shaped
si3n4
photo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18797080A
Other languages
Japanese (ja)
Inventor
Yoshinobu Monma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18797080A priority Critical patent/JPS57113249A/en
Publication of JPS57113249A publication Critical patent/JPS57113249A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the formation of a bird-beak by shaping an oxide film through selective oxidation in a groove, introducing one conduction type impurity into a substrate while using the oxide film as a mask and forming a channel cut region near a groove bottom section. CONSTITUTION:The V-shaped groove 14 is shaped through the etching of a semicondictor layer 12 and the substrate 11 while employing a Si3N4 film 13 patterned as a mask. The SiO2 insulating film 152 is formed through selective thermal oxidation while using the Si3N4 film 13 as a mask. A Si3N4 film 16 is shaped onto the surface, and an upper surface is coated with a photo-resist 17. The Si3N4 film 16 is removed selectively through a dry etching method, etc. while employing the photo-resist film 17 as a mask. The inside of the V-shaped groove 14 is oxidized selectively while using the Si3N4 film 16 as a mask. The photo-resist film 17 is removed through etching. Boron ions are implanted, the P<+> type channel cut region 19 is shaped through a hole section 18, the surface is oxidized, and the boron ions are activated.
JP18797080A 1980-12-29 1980-12-29 Manufacutre of semiconductor device Pending JPS57113249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18797080A JPS57113249A (en) 1980-12-29 1980-12-29 Manufacutre of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18797080A JPS57113249A (en) 1980-12-29 1980-12-29 Manufacutre of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57113249A true JPS57113249A (en) 1982-07-14

Family

ID=16215327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18797080A Pending JPS57113249A (en) 1980-12-29 1980-12-29 Manufacutre of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57113249A (en)

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