JPS57149750A - Element isolating method - Google Patents

Element isolating method

Info

Publication number
JPS57149750A
JPS57149750A JP3462381A JP3462381A JPS57149750A JP S57149750 A JPS57149750 A JP S57149750A JP 3462381 A JP3462381 A JP 3462381A JP 3462381 A JP3462381 A JP 3462381A JP S57149750 A JPS57149750 A JP S57149750A
Authority
JP
Japan
Prior art keywords
films
sio2
convex sections
ions
concave section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3462381A
Other languages
Japanese (ja)
Other versions
JPS6217865B2 (en
Inventor
Toshiaki Taniuchi
Tadashi Serikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3462381A priority Critical patent/JPS57149750A/en
Publication of JPS57149750A publication Critical patent/JPS57149750A/en
Publication of JPS6217865B2 publication Critical patent/JPS6217865B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain flat structure by coating a substrate with the resist film of a predetermined pattern at first, forming a concave section trailing the skirt under the resist film through the oblique irradiation of ions, shaping an isolation region to the side wall and bottom of the concave section through ion implantation and burying the concave section with a SiO2 film when isolating a section between the elements of IC. CONSTITUTION:The patterned resist films 10 for a lift-off are formed to the surface 2 of the semiconductor substrate 1, Ar ions are irradiated obliquely while turning the substrate 1, the grooves trailing the skirts are shaped under the films 10, and convex sections 1a, 1b are formed under the films 10. Impurity ions are implanted vertically in the whole surface, the element isolating regions 7 are shaped extending over the bottoms from the side walls of the convex sections 1a, 1b, SiO2 is formed to the whole surface containing the regions, and the SiO2 films 11b are shaped surrounding the convex sections 1a, 1b and the SiO2 films 11c onto the films 10. The films 10 are removed together with the films 11c coated onto the films 10, and an element region in which the surface insulated and isolated by the films 11b is flattened is obtained.
JP3462381A 1981-03-12 1981-03-12 Element isolating method Granted JPS57149750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3462381A JPS57149750A (en) 1981-03-12 1981-03-12 Element isolating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3462381A JPS57149750A (en) 1981-03-12 1981-03-12 Element isolating method

Publications (2)

Publication Number Publication Date
JPS57149750A true JPS57149750A (en) 1982-09-16
JPS6217865B2 JPS6217865B2 (en) 1987-04-20

Family

ID=12419510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3462381A Granted JPS57149750A (en) 1981-03-12 1981-03-12 Element isolating method

Country Status (1)

Country Link
JP (1) JPS57149750A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121848A (en) * 1982-12-28 1984-07-14 Toshiba Corp Semiconductor device and manufacture thereof
US6452246B1 (en) * 1999-07-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134078A (en) * 1975-05-16 1976-11-20 Hitachi Ltd Method to manufacture semiconductor unit
JPS52127074A (en) * 1976-04-16 1977-10-25 Matsushita Electric Ind Co Ltd Pattern formation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134078A (en) * 1975-05-16 1976-11-20 Hitachi Ltd Method to manufacture semiconductor unit
JPS52127074A (en) * 1976-04-16 1977-10-25 Matsushita Electric Ind Co Ltd Pattern formation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121848A (en) * 1982-12-28 1984-07-14 Toshiba Corp Semiconductor device and manufacture thereof
JPH0451978B2 (en) * 1982-12-28 1992-08-20 Tokyo Shibaura Electric Co
US6452246B1 (en) * 1999-07-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device
US6855615B2 (en) 1999-07-16 2005-02-15 Renesas Technology Corp. Method of manufacturing semiconductor device having an improved isolation structure

Also Published As

Publication number Publication date
JPS6217865B2 (en) 1987-04-20

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