JPH0451978B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, in order to electrically isolate each element on a semiconductor substrate, an insulating film is formed in a field region. The present invention relates to a method of manufacturing an embedded semiconductor device.

[Prior art and its problems] In semiconductor devices using silicon as a semiconductor, especially MOS type semiconductor devices, in order to eliminate insulation defects caused by parasitic channels and reduce parasitic capacitance, so-called field regions (element isolation In some cases, a thick oxide film is formed in the area.

Conventionally, as a method for isolation between elements using such an oxide film, the silicon substrate in the field area is partially etched to form a groove, and the field oxide film is buried in the groove so as to be flat using CVD technology. be. This device isolation method is extremely useful for manufacturing highly integrated circuits because the substrate surface becomes almost flat after the devices are separated, and the dimensions of the isolation region are determined by the precisely formed trench dimensions. This is an effective element isolation technology.

FIG. 1 shows a cross-sectional view of a MOS transistor formed by a conventional method, taken along the transistor width W direction. That is, a field oxide film 12, a field inversion prevention layer 13, a gate insulating film 14, and a gate electrode 15 are formed on the semiconductor substrate 11, and the interval between the field oxide films 12 in the element isolation region on the substrate 11 is equal to the transistor width W. It represents. In this figure, since ions are not implanted on the side surface 16, parasitic channels are likely to be formed.
That is, due to the gate electrode 15, a parasitic channel is formed in the upper part of the side surface 16 with a gate voltage lower than the original threshold voltage of the MOS transistor. Figure 2 shows this situation. Figure 2 shows the sub-threshold characteristics (10g I _D - V _G characteristics) of the prototype MOS transistor.The solid line A characteristic with a kink as shown in appears. As described above, the parasitic transistor formed on the side surface of the trench by the conventional method causes leakage current in the OFF state and deteriorates the device characteristics.

In order to prevent this parasitic transistor, it is sufficient to reduce the electric field concentration on the side surface 16. That is, ions of an impurity of the same conductivity type as the substrate are implanted into the side surface 16 to prevent inversion, the gate oxide film around the diffusion layer is made thicker, and the substrate is tapered.

The circuit board shown in FIG. 3 is shown when tapered. In this example, the substrate 21 is etched using an alkaline etching solution (KoH or the like) using SiO ₂ 22 as a mask. At this time, if the narrow part of the field area (dimension S) is smaller than the desired etching depth H, etching can only be performed shallower than the desired etching depth, resulting in variations in manufacturing and electrical characteristics. This also limits the miniaturization of element isolation regions.

On the other hand, if the etching depth is too shallow, the field oxide film will become thinner and the capacitance of the wiring and substrate will increase, which will slow down the operating speed of the semiconductor device and make it impossible to achieve high speed.

[Objective of the Invention] The present invention provides a semiconductor device that prevents the generation of parasitic transistors, reduces the area of the element isolation region, and reduces the stray capacitance between the wiring and the substrate, and increases the operating speed of the semiconductor device, and its manufacture. The present invention provides a method.

[Summary of the Invention] In the present invention, when forming a groove in a device isolation region on a substrate using a mask material, etching is performed so that the side surface of the groove becomes a slope having a predetermined inclination angle with respect to the substrate surface. After forming the grooves, the area of the mask material was increased to widen the area that would serve as a mask, and using this expanded mask material as a mask, a second groove was formed inside the first groove almost perpendicular to the substrate surface. After that, an insulating film is buried in the first and second trenches and planarized in the same process as in the conventional method. The inclination angle of the first groove side surface is determined to prevent the formation of cavities in the buried insulating film, and to simultaneously implant ions into the groove side surface at the required dose when implanting ions into the trench. In order to prevent the generation of parasitic channels, it is necessary to set the angle to 85 degrees or less, and to achieve high integration through microfabrication, it is necessary to set the angle to at least 40 degrees or more.

[Effects of the Invention] By implementing the present invention, it is possible to prevent the generation of parasitic channels on the side surfaces of the groove, improve device characteristics, and improve reliability. In addition, since the depth of the groove can be made constant regardless of the size of the field area, variations in device characteristics such as leakage current between n ⁺ - n ⁺ are eliminated, and the embedding process is simple and uniform. Since it can be miniaturized, it can be highly integrated. Furthermore, since the field insulating film can be formed thickly, the capacitance between the substrate and the gate electrode and between the substrate and the wiring can be reduced, so that the operating speed of the element or circuit can be increased.

[Embodiment of the Invention] An embodiment of the present invention will be described in detail with reference to FIG. 4. First, for example, specific resistance 5~10Ω-
A P(100) Si substrate 31 with a thickness of about cm is prepared, and on the entire surface thereof, for example, a thermal oxide film 32 of about 200 Å and a poly-Si layer 33 containing phosphorus of about 5000 Å are laminated. Thereafter, a selective photoresist is placed in areas other than the field area by photolithography, and using this photoresist as a mask, RIE (reactive ion etching) is used to perform the above-mentioned
After etching the poly-Si 33 and thermal oxide film 32, the photoresist is removed. Then, for example
Perform steam oxidation at 800-900°C. At this time, the oxidation rate of the Poly-Si containing phosphorus becomes about 2 to 4 times faster than that of the exposed Si substrate surface. That is, the oxide film formed on the Poly-Si containing phosphorus is thicker than the Si substrate. After steam oxidation, the oxide film formed on the Si substrate is removed by etching, and the poly-Si
A SiO ₂ film 34 of about 200 Å is left around the SiO 2 film 33. Thereafter, using the thermal oxide film 32 and the SiO ₂ film 34 as a mask, the Si substrate 31 is taper-etched at an angle of about 57° using, for example, an etching solution containing KOH, thereby etching the Si substrate 31 by about 0.4 μm. after that
Using the poly-Si film 33 as a mask, boron ions are implanted to prevent field inversion to form field inversion layers 35a and 35b. The boron ion implantation conditions 35a are 25 KeV and 1×10 ¹³ ion/cm ² , and the acceleration voltage 35b is determined so that the bottom of the second groove becomes R _P in etching the second Si substrate. For example, 100 KeV, 1×10 ¹³ /cm ² . (Figure 4a
(Reference) Next, for example, by performing steam oxidation at 800 to 900°C, an oxide film that is thicker than the Si substrate is formed around the Poly-Si 33, and then the oxide film on the Si substrate is removed by etching to remove the oxide film around the Poly-Si 33. For example, a SiO ₂ film 36 of about 3000 Å is formed thereon. Thereafter, using the SiO ₂ film 36 as a mask, for example, 50% of CF ₄ gas is applied.
By flowing a gas containing cc/min and performing RIE at a pressure of about 30 mmTorr, the Si substrate 31 is vertically etched to form a second groove of about 0.3 μm (FIG. 4b). The angle of inclination of the second groove with respect to the substrate surface is 70 degrees or more, preferably 90 degrees.

Next, SiO ₂ 36, Poly-Si 33, thermal oxide film 32
After removing the SiO ₂ film 37, for example, by CVD method.
After forming about 7000 Å, the surface is made substantially flat using, for example, a low-viscosity photoresist 38.
(FIG. 4c) Thereafter, for example, by using RIE using CF ₄ gas, the SiO ₂ film 37 and the photoresist 38 are etched under etching conditions where the etching speed is almost equal, so that the Si substrate 31 is exposed and the first The grooves 35a and 35b are filled with SiO ₂ 37 so that the surface thereof is approximately at the same height as the convex portion of the Si substrate. After that, heat treatment is performed to connect 35a and 35b and form the field inversion prevention layer 35. form. (FIG. 4d) Thereafter, a semiconductor device is formed on a portion including the surface of the convex portion of the Si substrate using a conventional technique.

When this method is used, the second groove can be formed in self-alignment with the first groove, so miniaturization is easy. Moreover, since the poly-Si oxide film is used as a mask, the dimensions of the second trench can be precisely controlled in the lateral direction. That is, since the dimensions of the second groove can be formed with an accuracy of 10 Å or less, there is no problem of variations in processing dimensions.

[Other Examples of the Invention] In the above method, Poly-Si containing phosphorus was used,
Poly-Si containing phosphorus and other impurities may also be used. For example, boron, arsenic, etc.
Like Poly-Si, any material can be used as long as the area of the mask increases due to chemical changes (oxidation, etc.). For example, in the case of Al, it may be changed to Al ₂ O ₃ by anodic oxidation.

Furthermore, when forming the first groove, Si may be etched using RIE, which allows the angle to be freely determined, instead of KOH. Also, as shown in Figure 5,
The insulating film in the field region may be formed higher than the surface of the Si substrate. In this case, it is further effective in preventing the generation of parasitic channels. Also Poly
-Depending on the conditions of oxidation of Si33, the surface of the convex portion of the Si substrate may not be flat but curved. In addition, although n-MOS was described in the example, p-ch
Needless to say, it can be used for MOS, CMOS, bipolar, etc.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view in the W direction of an element formed using the conventional method, Figure 2 is a characteristic diagram showing the I _D -V _g characteristics of the element in Figure 1, and Figure 3 is a cross-sectional view of the element formed using the conventional method. FIGS. 4a to 4d are sectional views showing steps of one embodiment of the present invention, and FIG. 5 is a sectional view showing another embodiment. In the figure, 11, 21, 31...Si substrate, 1
2, 14, 32, 34, 36, 37...SiO ₂ film,
13, 35a, 35b, 35... Field inversion prevention layer, 15, 33... Poly-Si, 38... Photoresist.

Claims (1)

[Claims] 1. A step of forming a mask material on a semiconductor substrate,
Using this mask material as a mask, the element isolation region of the semiconductor substrate is etched using an anisotropic etching method in which only the surface of the semiconductor substrate that is exposed from the mask with the sides of the mask as boundaries is etched, so that the inclination angle with respect to the substrate surface is adjusted. A step of forming a first groove with side surfaces in the range of 40 to 85 degrees, a step of implanting ions of the same conductivity type as the substrate into the inclined side surfaces and bottom of the first groove, and a step of implanting ions at high acceleration. forming an ion-implanted layer with a bowl-shaped cross section of the same conductivity type as the substrate and having a similar shape to the surface of the first groove in a deep part of the substrate away from the first groove; and oxidizing the mask material. a step of enlarging the area of a mask material, using the enlarged mask material as a mask to reach the bowl-shaped ion implantation layer within the first groove;
and a step of forming a second groove having side surfaces whose angle of inclination to the substrate surface is almost perpendicular, and an ion implantation layer formed on the surface of the first groove by heat treatment and a bowl-shaped ion implantation formed deep in the substrate. A semiconductor device comprising: a step of connecting layers; a step of forming an insulating film to fill the first trench and the second trench; and a step of forming an element on a substrate in an element region. Production method.