JPH03157972A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce characteristics change and disconnection by forming silicon oxide before a trench is filled, and filling the trench at the same time as the formation of a side wall. CONSTITUTION:Silicon oxide 4 and a conductive film 5 are formed on the surface of a semiconductor substrate 1; the film 5, the silicon 4 and the substrate 1 are etched in order, thereby forming a trench 2 in a first region of the surface. Silicon oxide 11 is formed on the surface of the film 5 and inside the trench 2; the film 5 is left only in a second region, and a gate electrode 5A is formed. Impurity is ion-implanted in a third region, and a low concentration impurity diffusion layer 7 is formed on the surface of the substrate 1; silicon oxide 8 is deposited on the whole surface; a side wall 9 is formed on the side wall of the film 5 by etching; and a high concentration diffusion layer 10 is formed by ion implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an MO8 type semiconductor device with trench type element isolation.

[Conventional technology]

As the density of MOS memory integrated circuits has increased, memory cells have become smaller and adjacent cells have come closer to each other, making it necessary to completely insulate and separate the cells from each other. For this reason, a method is used in which a trench is dug in the semiconductor substrate and the trench is filled with an insulating material to insulate and isolate the cells from each other. A conventional method for forming a semiconductor device using this groove separation will be explained with reference to FIGS. 3(a) to 3(f).

First, as shown in FIG. 3(a), a groove 2 is formed in a predetermined region of a semiconductor substrate 1 made of P-type silicon or the like.

Next, silicon oxide 1 is placed on the surface of the semiconductor substrate 1 and inside the groove 2.
form 2. Next, using lithography technology, groove 2
For example, silicon oxide 3 containing a P-type impurity such as phosphorus is embedded in the area.

Next, as shown in FIG. 3(b), a first silicon oxide 4 is formed on the surface of the semiconductor substrate 1 by thermal oxidation, and then a low-resistance film such as polycrystalline silicon is formed on the surface of the first silicon oxide 40. A conductive film 5 of a certain value is formed.

Next, a photoresist 6 is formed in a predetermined area, and the conductive film 5 is etched using the photoresist as a mask, leaving only the predetermined area.

Next, as shown in FIG. 3C, a predetermined region of the surface of the semiconductor substrate 1 is coated with acceleration energy sufficient to penetrate the silicon oxide 4 using lithography technology.
A low concentration impurity diffusion layer 7 is formed on the surface of the semiconductor substrate 1 by ion-implanting impurities of the opposite conductivity type.

Next, as shown in FIG. 3(d), silicon oxide 8 containing impurities is deposited over the entire surface of the semiconductor substrate 1 by CVD technology or the like.

Next, as shown in FIG. 3(e), the entire surface of the silicon oxide 8 is etched by the thickness of the silicon oxide 8 containing impurities by anisotropic etching such as the RIE method (hereinafter referred to as etch-back). . As a result, the conductive film 5
A sidewall 9, which is a part of silicon oxide 8 containing impurities, is formed only on the sidewall.

Next, as shown in FIG. 3(f), impurity ions of a conductivity type opposite to that of the semiconductor substrate 1 are implanted into a predetermined region to form a highly doped diffusion layer 10, thereby completing a transistor with an LDD structure.

[Problem to be solved by the invention]

However, in the conventional method for manufacturing a MOS memory integrated circuit with trench type element isolation described above, the trench is filled with silicon oxide 3 containing a large amount of impurities, and then the first silicon oxide 4 is formed. Due to the high-temperature heat treatment, impurities such as phosphorus and poron evaporate or diffuse from the impurity-containing silicon oxide 3 and enter the first silicon oxide 4, becoming surface charges and causing fluctuations in transistor characteristics. It has the disadvantage of Furthermore, since the sidewalls 9 are formed after filling the grooves, there is a drawback that the tops of the grooves are gouged out during etchback as shown in FIG. 4, creating unevenness on the surface and causing interconnections to break in subsequent steps.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for manufacturing a semiconductor device equipped with groove-type element isolation that causes less variation in characteristics and less disconnection.

In the conventional method for manufacturing an MO8 type semiconductor device described above, trenches for element isolation are filled with silicon oxide containing impurities, first silicon oxide is formed, and then sidewalls are formed. , the difference is that the first silicon oxide is formed before filling the trench, and then the trench filling and sidewall formation are performed simultaneously.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes: - forming a first silicon oxide on the surface of a conductive type semiconductor substrate; forming a conductive thin film on the first silicon oxide; etching the first silicon oxide and the conductive thin film to form a groove in the first region; selectively etching the conductive thin film to form a gate electrode in the second region; Using the electrode as a mask, 5- ion-implanting impurities of opposite conductivity type to form a low concentration diffusion layer on the surface of the semiconductor substrate; and after covering the entire surface including the groove and the surface of the gate electrode with an insulating material, anisotropic etching is performed. The method includes the steps of filling the trench and simultaneously forming a sidewall on the side surface of the gate electrode.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1H are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a first silicon oxide 4 and a conductive film 5 such as low resistance polycrystalline silicon for a gate electrode are formed on the surface of a semiconductor substrate 1 made of P silicon or the like. .

Next, as shown in FIG. 1(b), through a lithography process, the conductive film 5, the first silicon oxide 4, and the semiconductor substrate 1 are sequentially etched, and grooves are formed in the first region of the surface of the semiconductor substrate 10. form.

Next, as shown in FIG. 1(c), a second silicon oxide 11 is formed on the surface of the conductive film 50 and inside the groove 2 by, for example, a thermal oxidation method.

Next, as shown in FIG. 1(d), a lithography process is performed again to leave the conductive film 5 only in the second region and remove unnecessary conductive film 5 to form a gate electrode 5A.

Next, as shown in FIG. 1(e), using the gate electrode 5A as a mask, a third region of the surface of the semiconductor substrate 1 is placed on the semiconductor substrate 1.
A low concentration impurity diffusion layer 7 is formed on the surface of the semiconductor substrate 1 by ion-implanting an impurity of the opposite conductivity type (N type).

Next, as shown in FIG. 1(f), silicon oxide 8 containing impurities such as phosphorus and poron is deposited on the entire surface.

Next, as shown in FIG. 1(g), the entire surface of the impurity-containing silicon oxide 8 is etched by anisotropic etching such as RIE to a thickness equivalent to the thickness of the impurity-containing silicon oxide 8. As a result, a sidewall 9 is formed on the sidewall of the conductive film 5.

Next, as shown in FIG. 1(h), using the gate electrode 5A and sidewall 9 as a mask, impurity ions of the opposite conductivity type to the semiconductor substrate 1 are implanted to form a highly concentrated diffusion layer 10. A transistor having an LDD structure with type element isolation is completed.

In this way, in the first embodiment, the trench 2 is filled with impurity-containing silicon oxide 8 and the entire surface is covered at the same time, and then the sidewall 9 is formed by etching back, so the trench 2 is not filled as in the conventional method. The silicon oxide surface will no longer be gouged.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), steps similar to those of the first embodiment up to FIG. 1(e) are performed up to the point where a low concentration impurity diffusion layer 7 is formed on the surface of the semiconductor substrate 1. Following this step, polycrystalline silicon 13 is deposited on the entire surface.

Next, as shown in FIG. 2(b), the entire surface of the polycrystalline silicon 13 is etched by the thickness of the polycrystalline silicon 13.

Next, as shown in FIG. 2(c), silicon oxide 8 containing impurities such as phosphorus and poron is deposited over the entire surface.

Next, as shown in FIG. 2(d), the entire surface of the impurity-containing silicon oxide 8 is etched by anisotropic etching such as the RIE method to the thickness of the impurity-containing silicon oxide 8 to form a sidewall. Form. At this time, the depression in groove 2 is filled at the same time. Next, an impurity of a conductivity type opposite to that of the semiconductor substrate 1 is ion-implanted into the fourth region to form a highly doped diffusion layer 10, thereby forming a transistor with an LDD structure.

In this second embodiment, since the groove is first filled with polycrystalline silicon, there is an advantage that the stress applied to the edge of the groove is alleviated.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the conductive film for the gate electrode is formed after filling the trench for device isolation with silicon oxide containing impurities. By oxidizing the substrate 9-, diffusion of impurities into the first silicon oxide can be prevented, and the characteristics of the first silicon oxide can be improved. As a result, there is an effect of improving the performance of the MO8 type semiconductor device. Additionally, instead of filling the trench and then depositing silicon oxide and etching back to form the sidewall, we can now flatten the top of the trench by filling the trench and forming the sidewall at the same time. As a result, there is no disconnection due to surface irregularities in the wiring in the subsequent process, and it is possible to significantly improve the reliability of the wiring.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a semiconductor chip for explaining the first and second embodiments of the present invention, and FIGS. 3 and 4 are cross-sectional views of a semiconductor chip for explaining a conventional manufacturing method. FIG. 1... Semiconductor substrate, 2... Groove, 3...
... Silicon oxide containing impurities, 4 ... First silicon oxide, 5 ... Conductive film, 5A ...
...Gate electrode, 6...lO- photoresist, 7...Low concentration diffusion layer, 8. Old...Silicon oxide containing impurities, 9...Side Wall, 10... High concentration diffusion layer, 11... Mark, second silicon oxide, 12... Silicon oxide, 13... Group, polycrystalline silicon.

Claims (1)

[Claims] a step of forming a first silicon oxide on a surface of a semiconductor substrate of one conductivity type; a step of forming a conductive thin film on the first silicon oxide; and a step of forming a conductive thin film on the semiconductor substrate, the first silicon oxide, and the conductive thin film. a step of selectively etching the conductive thin film to form a groove in the first region; a step of selectively etching the conductive thin film to form a gate electrode in the second region; and ionizing impurities of opposite conductivity using the gate electrode as a mask. A process of implanting and forming a low concentration diffusion layer on the surface of the semiconductor substrate, and after covering the entire surface including the groove and the surface of the gate electrode with an insulating material, anisotropic etching is performed to fill the groove and at the same time form a low concentration diffusion layer on the side of the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the step of forming a wall.