JPH0837230A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve element isolation characteristics and the scale of integration of a semiconductor integrated circuit device. CONSTITUTION:Element isolation trenches 21 are formed on a semiconductor substrate 1. The openings of the trenches 21 are sealed with an insulating film 20 of an organic solution of silanol or polyimide resin. Enclosed spaces 31 are thereby formed to electrically isolate a plurality of elements with reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as an LSI and its manufacturing method, and more particularly to a semiconductor integrated circuit device having an improved element isolation structure and its manufacturing method.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device such as an LSI, a LOCOS (Local Oxidation) method is generally used as a method for electrically separating semiconductor elements.
f Silicon) method is known.

FIG. 24 shows a main part of a conventional MOS type semiconductor integrated circuit device in which elements are isolated by using the LOCOS method. In the figure, 1 is a semiconductor substrate made of a P type silicon substrate. 2 and 2 are n-channel type MOSs formed on one main surface of the semiconductor substrate, respectively.
Transistors 3, 3 are one source / drain region of each MOS transistor, and are formed by ion-implanting N-type impurities such as phosphorus (P) and arsenic (As) into one main surface of the semiconductor substrate 1. N-type low-concentration impurity region 3a formed and N-type high-concentration impurity region 3 formed by ion-implanting N-type impurities such as phosphorus (P) and arsenic (As).
b. Reference numerals 4 and 4 denote the other source / drain of each MOS transistor formed by sandwiching the one source / drain region 3 and the channel region 5 respectively.
In the drain region, an N-type low-concentration impurity region 4a formed by ion-implanting an N-type impurity such as phosphorus (P) or arsenic (As) into one main surface of the semiconductor substrate 1 and phosphorus (P) or And an N-type high-concentration impurity region 4b formed by ion-implanting N-type impurities such as arsenic (As).

Reference numerals 7 and 7 denote gate electrodes of each MOS transistor formed on the channel region 5 with a gate insulating film 6 interposed therebetween. The gate electrodes 7 and 7 are made of polycrystalline silicon in which impurities such as phosphorus (P) are diffused. There is something. Reference numeral 8 is an element isolation oxide film made of a silicon oxide film for surrounding each MOS transistor 2 and 2 and electrically and surely separating each MOS transistor 2 and 2, and 9 and 9 are each of the MO transistors.
Side walls 10 made of silicon oxide films formed on both side surfaces of the gate electrodes 7 of the S transistors 2 and 2 are formed on the MOS transistors 2 and 2, the side walls 9 and the element isolation oxide film 8. It is an interlayer insulating film formed of a silicon oxide film.

Reference numerals 11 and 11 respectively denote the interlayer insulating film 10 described above.
Source / drain electrodes 12 and 12 electrically connected to the one source / drain region 3 via the contact holes of the other source / drain regions 12 and 12 respectively via the contact holes of the interlayer insulating film 10. The other source / drain electrode electrically connected to the region 3,
Reference numerals 13 and 13 denote power supplies for supplying currents to the source / drain electrodes 11 and 12 of the corresponding MOS transistors 2, and not only indicate power supply nodes to which external power is supplied, but also currents including circuits. It is expressed generically as a supply source.

Next, a method of manufacturing the semiconductor integrated circuit device thus configured will be described with reference to FIGS. First, as shown in FIG. 25, the semiconductor substrate 1
An underlying silicon oxide film 14, a silicon nitride film 15, and a resist film 16 are sequentially formed on one main surface of the substrate, and the resist film 16 is patterned by using a normal exposure technique and a development technique. Is used to etch the silicon nitride film 15 by a normal etching technique to obtain a patterned silicon nitride film as a mask for selectively oxidizing the semiconductor substrate 1. That is, the silicon nitride film 15 is present on the formation region where the MOS transistor is formed, and the silicon oxide film 14 is exposed on the element isolation region surrounding the MOS transistor.

Next, when the resist film 16 is removed and a thermal oxidation process is performed using the patterned silicon nitride film 15 as a mask, as shown in FIG. 26, the portion where the silicon oxide film was exposed, that is, the semiconductor An element isolation oxide film 8 made of a silicon oxide film is formed in the element isolation region of the substrate 1. Next, as shown in FIG. 27, the silicon nitride film 1
5 and the underlying silicon oxide film 14 are removed.

Next, as shown in FIG. 28, the gate oxide film 6, N (phosphorus (P), arsenic (As), etc., which becomes the gate electrode) is formed.
A polycrystalline silicon film 7 and a resist film 17 in which the type impurities are diffused are sequentially formed, the polycrystalline silicon film 7 is etched using the resist film 17 as a mask to obtain a gate electrode, and the resist film 17 and the gate electrode are used as a mask. , N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted in a self-aligned manner to form a pair of sources / sources of a MOS transistor.
N type low concentration impurity regions 3a and 4a of the drain region are formed.

Next, as shown in FIG. 29, the resist film 1
7 is removed, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1 by the CVD method, etc., and highly anisotropic etching is performed.
The sidewall 9 is formed. Using the side wall 9 and the gate electrode 6 as a part of a mask, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into one main surface of the semiconductor substrate 1 in a self-aligned manner to form a MOS transistor. The pair of source / drain regions of N-type high concentration impurity regions 3b and 4b are formed.

Next, as shown in FIG. 30, after forming a silicon oxide film 10 to be an interlayer insulating film by a CVD method or the like,
A resist film 18 is formed. Next, the interlayer insulating film 10 is etched by using the resist film 18 as a mask to form contact holes for connecting the source / drain electrodes to the source / drain regions of the MOS transistor as shown in FIG.

Next, the resist film 18 is removed, and the source / source
Conductive film 25 for forming the drain electrode and its wiring
Is laminated on the entire main surface of the semiconductor substrate 1 by the CVD method or the like. Next, a resist film 19 is formed as shown in FIG. When the conductive film 25 is etched using the resist film 19 as a mask, one of the source / drain electrodes 11,
And the other source / drain electrode 12 is formed, and the semiconductor integrated circuit device shown in FIG. 24 is obtained.

On the other hand, apart from the element isolation using the LOCOS method described above, a BOX (Buried O
It is known that element isolation is performed by a method called xide), which is generally called trench isolation. FIG.
2 shows a main part of a conventional MOS type semiconductor integrated circuit device in which elements are isolated by using this trench isolation. In FIG. 32, the conventional semiconductor integrated circuit shown in FIG. The same reference numerals indicate the same or corresponding portions, and the difference from the semiconductor integrated circuit device shown in FIG. 24 is that the element isolation groove 35 is provided in the element isolation region of the semiconductor substrate 1 as the element isolation. This element separating groove 3
5 is an oxide film 37 for element isolation embedded in FIG.

Next, a method of manufacturing the semiconductor integrated circuit device thus configured will be described with reference to FIGS. 33 to 36. First, as shown in FIG. 33, the semiconductor substrate 1
A resist pattern 22 is formed on one main surface of the substrate, and ordinary etching is performed using the resist pattern 22 as a mask to form the element isolation trench 21.

Next, as shown in FIG. 34, the resist pattern 22 is removed and a thick oxide film 36 is formed on the entire one main surface of the semiconductor substrate 1 by the CVD method or the like. Next, FIG.
As shown in FIG. 1, the silicon oxide film 36 is formed on one main surface of the semiconductor substrate 1 by dry etching or chemical mechanical polishing.
Is etched off, and an element isolation oxide film 37 is formed only in the element isolation trench 35.

Next, a gate oxide film 6 and a polycrystalline silicon film 7 in which N-type impurities such as phosphorus (P) and arsenic (As) to be a gate electrode are diffused are sequentially formed on one main surface of the semiconductor substrate 1. Then, the polycrystalline silicon film 6 is etched to form the gate electrode of the MOS transistor. Using this gate electrode as a mask, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted to form N-type low-concentration impurity regions 3a and 4a of a pair of source / drain regions of a MOS transistor. To do. After that, C is formed on one main surface of the semiconductor substrate 1.
A silicon oxide film is formed by the VD method or the like, and highly anisotropic etching is performed to form sidewalls 9 on the sidewalls of the gate electrode 7.

Next, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the one main surface of the semiconductor substrate 1 in a self-aligned manner by using the gate electrode 7 and the sidewall 9 as a part of a mask. As a result, the N-type high-concentration impurity regions 3b and 4 of the pair of source / drain regions of the MOS transistor are formed.
b is formed. This state is shown in FIG.

After that, the semiconductor integrated circuit device shown in FIG. 32 is obtained by the same method as that shown in FIG. That is, after forming the silicon oxide film 10 serving as an interlayer insulating film by the CVD method or the like, a resist pattern is formed, and the silicon oxide film 10 is etched using the resist pattern as a mask to form a contact hole,
A conductive film of polycrystalline silicon is formed by diffusing a metal such as aluminum to be the source / drain electrodes and the wiring thereof, or phosphorus (P) or arsenic (As), and the conductive film is selectively etched to form a pair of conductive films. The semiconductor integrated circuit device is obtained by forming the source / drain electrodes 11 and 12.

[0018]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In a semiconductor integrated circuit device using the COS method, an element isolation oxide film 8 made of a silicon oxide film having a film thickness of about several hundreds nm has to be formed for element isolation. When formed, there was always a portion called bird's beak 30 shown in FIG. In this way, the bird's beak 3 is formed on the one main surface of the semiconductor substrate 1 based on the element isolation oxide film 8.
Since 0 is formed, stress is applied to the vicinity of the one main surface of the semiconductor substrate 1, causing crystal defects in the semiconductor substrate 1 and causing a leak current. In addition, the bird's beak 30 on one main surface of the semiconductor substrate 1 extends in the horizontal direction, which has been an obstacle to miniaturization when an ultra-large scale integrated circuit device is manufactured. Further, an interface state was generated in the vicinity of the interface between the silicon constituting the semiconductor substrate 1 and the element isolation oxide film 8.
The interface states and crystal defects as described above induce a leakage current 32 shown by a dotted arrow in FIG. 24 when a reverse voltage is applied to the PN junction between the source / drain region 3 and the semiconductor substrate, and the junction characteristics However, various problems have occurred, such as causing deterioration of the element isolation characteristics.

In the semiconductor integrated circuit device using the trench isolation, the isolation size is determined by the width of the element isolation groove 35 formed in the semiconductor substrate 1, which is higher than that using the LOCOS method. Suitable for integration,
There is theoretically no bird's beak which is a problem in the LOCOS method. However, even in the semiconductor integrated circuit device using this trench isolation, the LO
As in the case of using the COS method, the generation of an interface state is unavoidable due to the existence of the interface between the silicon of the semiconductor substrate 1 and the silicon oxide film 36 in the element isolation trench 35, and unbonded hands such as silicon atoms. The generation of free silicon, free oxygen atoms, and impurity elements is unavoidable, and causes a leak current at the PN junction between the source / drain region 3 and the semiconductor substrate 1 near the sidewall of the isolation trench 35. Was there.

As described above, the conventional LOCOS described above is used.
In the method using the method and the method using the trench isolation structure, the semiconductor substrate 1 resulting from the method for forming the element isolation is used.
Stress and the existence of the interface between the silicon constituting the semiconductor substrate 1 and the silicon oxide film 36 for separating the elements from each other cause defects and interface states to induce current leakage through them. It was Then, this causes deterioration of the PN junction characteristics and element isolation characteristics, which causes a problem such as an increase in power consumption of a semiconductor device such as an LSI, a decrease in normal operation margin, and a malfunction.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device in which an element isolation groove is formed on one main surface of a semiconductor substrate, and the element isolation groove is used to form a sealed space. Is provided with an insulating film.

According to a second aspect of the present invention, in a semiconductor integrated circuit device, an element isolation groove is formed on one main surface of a semiconductor substrate, and a wall-like body is formed in the element isolation groove to form an element isolation element. An insulating film that forms a closed space with the use groove and the wall-shaped body is provided.

A semiconductor integrated circuit device according to a third aspect of the present invention is formed of polycrystalline silicon in which an element isolation groove is formed in one main surface of a semiconductor substrate and an impurity diffusion region is included in the element isolation groove. An insulating film is formed to form a wall-shaped body, an impurity diffusion region is formed on one main surface of the semiconductor substrate located on the bottom surface of the element isolation groove, and an enclosed space is formed with the element isolation groove and the wall-shaped body. It is a thing.

A semiconductor integrated circuit device according to a fourth aspect of the present invention further uses a silicon oxide film or a polyimide resin film as an insulating film.

In the semiconductor integrated circuit device according to the fifth aspect of the present invention, an inert gas is further enclosed in the sealed space.

According to the sixth aspect of the present invention, in the method for manufacturing a semiconductor integrated circuit, the element isolation groove is formed on one main surface of the semiconductor substrate, and thereafter the element isolation groove and the element isolation groove are formed. An insulating film is formed.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, which comprises forming an element isolation groove on one main surface of a semiconductor substrate and forming sidewalls on both side surfaces of the element isolation groove. A step of forming a wall-shaped body in contact with the bottom surface of the element isolation groove of the semiconductor substrate sandwiched by the sidewall and in contact with the side surface of the sidewall, and removing the sidewall to form the wall of the element isolation groove of the semiconductor substrate. Forming a space between the side surface and the wall-shaped body, and sealing the side surface of the element separation groove and the wall-shaped body on one main surface of the semiconductor substrate in which the element-isolation groove and the wall-shaped body are formed. It has a step of forming an insulating film forming a space.

In the method of manufacturing a semiconductor integrated circuit according to the eighth aspect of the present invention, the element isolation groove is formed on one main surface of the semiconductor substrate, and the sidewalls are formed on both side surfaces of the element isolation groove. A step of forming a wall-like body made of a polycrystalline silicon body containing impurities in contact with the bottom surface of the element isolation groove of the semiconductor substrate sandwiched by the side wall and in contact with the side surface of the side wall; A step of removing and forming a space between the side surface of the element isolation groove of the semiconductor substrate and the wall-shaped body; and the element isolation on the main surface of the semiconductor substrate on which the element isolation groove and the wall-shaped body are formed. A step of forming an insulating film that forms a closed space between the side surface of the trench and the wall-like body; and heat-treating the semiconductor substrate having the trench for element isolation and the wall-like body, Impurities on the bottom of the isolation trench Diffuse into one main surface of the body substrate and a step of forming an impurity diffusion region.

Further, in the method for manufacturing a semiconductor integrated circuit according to the invention of claim 9 of the present invention, the main component of the semiconductor substrate in which the organic solution of silanol is formed as the element isolation groove is formed as the step of forming the insulating film. It includes a step of coating the surface and a step of heating the semiconductor substrate coated with the silanol organic solution to form the silanol organic solution into an insulating film made of a silicon oxide film.

Further, in the method for manufacturing a semiconductor integrated circuit device according to a tenth aspect of the present invention, further, as a step of forming an insulating film, a polyimide resin is formed on one main surface of the semiconductor substrate on which the element isolation groove is formed. It includes a step of applying and a step of heat-treating a semiconductor substrate coated with a polyimide resin to form a polyimide resin film as an insulating film.

[0031]

According to the first aspect of the present invention, the sealed space formed by the element isolation groove and the insulating film reduces defects on the semiconductor substrate in the element isolation region and does not cause an interface state. Current leakage from the elements to the semiconductor substrate is suppressed to ensure electrical isolation between the elements.

According to the second aspect of the present invention, the side surface of the element isolation groove and the closed space formed by the wall-like body and the insulating film cause defects and interface states in the semiconductor substrate in the element isolation region. The current leakage from the elements to the semiconductor substrate is suppressed and electrical isolation between the elements is ensured.

According to the third aspect of the present invention, the side surface of the element isolation groove, the closed space formed by the wall-like body and the insulating film, and the impurity diffusion region alleviate defects in the semiconductor substrate in the element isolation region. And reduce the occurrence of interface states,
Current leakage from the elements to the semiconductor substrate is suppressed to ensure electrical isolation between the elements.

In the invention of claim 4 of the present invention, the insulating film made of a silicon oxide film or a polyimide resin film controls the film thickness with high accuracy.

According to the fifth aspect of the present invention, the inert gas in the closed space can prevent moisture and active gas from entering the closed space.

According to the sixth aspect of the present invention, the sealed space formed by the element isolation groove and the insulating film reduces defects on the semiconductor substrate in the element isolation region and reduces the occurrence of interface states. , Current leakage from the elements to the semiconductor substrate is suppressed to ensure electrical isolation between the elements.

According to a seventh aspect of the present invention, the closed space formed by the side surface of the element isolation groove and the wall-like body and the insulating film reduces defects on the semiconductor substrate in the element isolation region and also reduces the interface level. Formation is facilitated by reducing the occurrence of locality, suppressing current leakage from the element to the semiconductor substrate, and ensuring electrical isolation between elements, and removing the sealed space by forming a sidewall. Excuse me.

According to the eighth aspect of the present invention, the side wall of the element isolation groove and the closed space formed by the wall-like body and the insulating film can be easily formed by removing the side wall. In addition, the impurity diffusion region can be easily formed by diffusing the impurities from the wall-shaped body to form the closed space.

According to the ninth aspect of the present invention, since the insulating film is formed by using the organic solution of silanol, the insulating film for forming the closed space is
A flat and easily controlled film thickness can be easily formed.

According to the tenth aspect of the present invention,
Since the insulating film is formed using polyimide resin,
As the insulating film for forming the closed space, it is possible to easily form a flat and precisely controlled film thickness.

[0041]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to FIGS.
It will be described based on 1. 1 and 2 are a sectional view and a plan view of a main part of the first embodiment. In the drawings, the same reference numerals as those of the conventional example shown in FIG. 23 indicate the same or corresponding portions, and 21 is An element isolation groove formed on one main surface of the semiconductor substrate 1 so as to surround an element formation region in which a semiconductor element (N-channel MOS transistor in the first embodiment) is formed. 3 μm,
The depth is 0.5 μm. 20 is this element isolation groove 2
1 and the element isolation groove 21 forms a closed space 3
1 is an insulating film formed of a silicon oxide film or a polyimide resin film, and has a thickness of 0.1 μm in the first embodiment.

An inert gas such as nitrogen (N ₂ ) is enclosed in the closed space 31 formed by the element isolation groove 21 and the insulating film 20. In the first embodiment, the width of the gate electrode 7 of the MOS transistor is 0.8
μm, the gate electrode 7 of the adjacent MOS transistor
And the source / drain electrodes 11,
The diameter of the contact hole of the interlayer insulating film 10 through which 11 penetrates is 0.8 μm, and the thickness of the interlayer insulating film 10 is 0.5 μm.

Next, a method of manufacturing the semiconductor integrated circuit device thus constructed will be described with reference to FIGS. The steps will be described below. First, as shown in FIG. 3, the gate oxide film 6 is formed on the P-type semiconductor substrate 1.
Then, a polycrystalline silicon film 7 to be a gate electrode is formed. Next, as shown in FIG. 4, after forming a resist film 17 on the polycrystalline silicon film 7 and patterning it, the polycrystalline silicon film is etched by using the patterned resist film 17 as a mask to form the gate electrode 7. Form. After that, N-type impurities are ion-implanted in a self-aligning manner using the gate electrode 7 as a mask to form the low-concentration diffusion layers 3a and 4a to be a pair of source / drain regions of the N-channel MOS transistor. At this time, the low-concentration diffusion layer 3a serving as one of the source / drain regions of the adjacent MOS transistors is commonly formed.

Then, after removing the resist film 17, the same processing as that of FIG. 29 described in the conventional example is performed to form sidewalls 9 on both side surfaces of the gate electrode 7, and the sidewall 9 and the gate electrode 7 are masked. As a self-aligned MO
High-concentration diffusion layers 3b and 4b to be a pair of source / drain regions of the S transistor are formed. This state is shown in FIG.

Next, after forming a resist pattern 22 as shown in FIG. 6, the semiconductor substrate 1 is RI using this as a mask.
Etching is performed by using E or the like to form the element isolation trench 21 deeper than the PN junction formed by the pair of source / drain regions 3 and 4 of the MOS transistor and the semiconductor substrate 1. The source / drain region 3 of the MOS transistor is electrically and physically separated by the element isolation groove.
Next, as shown in FIG. 7, after removing the resist pattern 22, heat treatment is performed in an H ₂ atmosphere 23.

Next, a silanol organic solution (having a viscosity of 5 in this embodiment) is prepared in an inert gas such as N ₂ or Ar.
0 cp) is spin-coated, and then heat treatment (350 ° C. for 1 hour in this embodiment) is performed to form the insulating film 20 for sealing the isolation trenches 21 on the semiconductor substrate 1, as shown in FIG. become. By this process, a closed space 31 formed by the element isolation groove 21 and the insulating film 20 is formed at the position of the element isolation region, and an inert gas is sealed in this space. Further, in FIG. 8, the silanol organic solution used to seal the opening of the element isolation trench 21 is conventionally used in a process called SOG (Spin On Grass), and is aimed at leveling the surface step. It is a kind of commonly used interlayer insulating film material, and can form a silicon oxide film by heat treatment after spin coating.

By optimizing the viscosity of the solution and the number of revolutions at the time of application in accordance with the opening diameter of the element isolation groove 21, the solution does not penetrate into the element isolation groove and the element isolation groove 21 The insulating film can be formed only in the opening.
As a matter of course, the smaller the opening diameter of the element isolation groove 21, the easier the setting of the conditions for the same process. By this process, the element isolation groove 21 is sealed, and the fine closed space 31 can be formed. The insulating film can also be formed by using a polyimide resin instead of the organic solution of silanol.

Next, as shown in FIG. 9, an interlayer insulating film 10 is formed on the insulating film 20 which seals the element isolation trench 21. This is formed as a protective film because an insulating film formed from an organic solution of silanol is easily damaged by etching or the like in a later process.

Next, the same process as that of FIG. 30 described in the conventional example is performed to form a resist film 18 for forming source / drain contact holes as shown in FIG.
Next, after performing normal etching to form a contact hole, as shown in FIG. 11, by performing the same process as in FIG. 31 described in the conventional example, the conductive film 25 and the same electrode for forming the source / drain electrodes. Resist film for formation 1
9 is formed. Next, by performing an etching process, source / drain electrodes are formed as shown in FIG. 1, and the formation of the transistor structure is completed.

In this embodiment, in the semiconductor integrated circuit device configured as described above, the elements are separated by using the closed space 31. Therefore, unlike the conventional LOCOS separation and trench separation, semiconductors are separated. Since the silicon oxide film for element isolation is not formed in the substrate 1, the stress on the semiconductor substrate 1 is greatly reduced, and the crystal defects 33 and the like due to the stress shown in FIG. 24 are reduced. Further, unlike the conventional one, since there is no interface with the silicon oxide film which is the semiconductor substrate, no interface level is generated. Also, N ₂ , A
Since the element isolation groove 21 is sealed in an inert gas such as r, an inert gas is filled in the closed space 31. In FIG. 7, the process is performed in an H ₂ atmosphere in order to reduce defects caused by damages on the sidewalls and bottom surface of the element isolation trench 21 in the etching process in FIG. This is because H is bonded to the dangling bonds of silicon atoms on the sidewall of the trench 21 for stabilizing the active atoms, and this treatment reduces the surface level on the surface of the sidewall of the trench 21 for element isolation. As a result, the inside of the element separating groove 21 is in a stable state. As a result, effects such as reduction of power consumption of the semiconductor integrated circuit such as LSI and reduction of normal operation margin can be obtained.

Example 2. 12 to 22 show Embodiment 2
12 and 13 are a cross-sectional view and a plan view of a main part of the second embodiment. In the second embodiment, one closed space 31 is formed for element isolation in the above-described first embodiment, but two closed spaces 26 are formed. As shown in FIGS. 12 and 13, in contact with the bottom surface of the element isolation groove 21 formed in the semiconductor substrate 1,
In addition, a wall-like body 27 made of polycrystalline silicon is formed at a predetermined distance from the side surface, and the insulating film 20 for sealing the space formed by the wall-like body 27 and the element isolation groove is used.
It has a closed space 26 to be closed, and the other structure is similar to that of the first embodiment, and it is provided in contact with the N-channel type MOS transistor and the source / drain regions of the transistor on the left and right of the element isolation groove. A source / drain electrode and an interlayer insulating film laminated on the insulating film that seals the element isolation groove are provided.

Next, a method of manufacturing the semiconductor integrated circuit device configured as described above will be described with reference to FIGS. First, the gate electrode 6, the pair of source / drain regions 3 and 4 and the sidewall 9 of the N-channel MOS transistor are formed in the same manner as in FIGS. 3 to 5 described in the first embodiment. Next, as shown in FIG.
The interlayer insulating film 24 is formed.

Next, as shown in FIG. 15, by performing the same processing as that of FIG. 6 described in the first embodiment, etching is performed using the resist pattern 22 as a mask, and the element isolation groove 21 is formed in the semiconductor substrate 1. To form. After that, FIG.
As shown in, the insulating film 28 made of a silicon oxide film is formed by the CVD method or the like.

Next, as shown in FIG. 16, the insulating film 28 is etched off by a highly anisotropic etching process such as RIE, and a sidewall 29 of a silicon oxide film is formed on the sidewall of the isolation trench 21. To do. Thereafter, as shown in FIG. 18, similarly, a polycrystalline silicon film 34 is formed inside the element isolation trench 21 and on one main surface of the semiconductor substrate 1 by the CVD method or the like.

Next, as shown in FIG. 19, the polycrystalline silicon film 34 is etched off up to about the surface of the semiconductor substrate 1,
Further, by wet etching with hydrofluoric acid or the like to remove the side wall 9 of the silicon oxide film, a wall-shaped body formed in the element isolation groove 21 at a predetermined distance from the side surface of the element isolation groove 21. 27 is formed. At this time, the side surface of the element isolation groove 21 and the wall-shaped body 2 are provided in the element isolation groove 21.
There will be two spaces between 7 and. The width of the two spaces 26 in the element isolation groove 21 is equal to the width of the sidewall 29, that is, is controlled by the thickness of the insulating film 28 shown in FIG.

Then, as in FIGS. 7 and 8 described in the first embodiment, heat treatment is performed in the H ₂ atmosphere shown in FIG. 20 to form the insulating film 20 for sealing the isolation trench 21 shown in FIG. Form. As a result, the openings of the two spaces provided in the element isolation groove 21 are sealed and the two sealed spaces 26 are formed.

Next, as shown in FIG. 22, an interlayer insulating film 10 is formed as in the case of FIG. 7 described in the first embodiment. Further, when the source / drain electrodes 11 and 12 of the transistors are formed by performing the same processing as that of FIGS. 10 and 11 described in the first embodiment, the formation of the semiconductor integrated circuit device shown in FIG. 12 is completed.

In the semiconductor integrated circuit device configured as described above, in addition to the same effect as that of the above-described first embodiment, the closed space 26 is formed by using the sidewall 29, so that miniaturization is achieved. Thus, the semiconductor integrated circuit device can be highly integrated. Further, since the opening of the space formed by the side surface of the element isolation groove 21 and the wall-like body 27 is also miniaturized, sealing with the insulating film 20 for forming the closed space 26 becomes easy.

Example 3. FIG. 23 shows a third embodiment of the present invention, which is different from the second embodiment described above in that the wall 27 is made of polycrystalline silicon containing P-type impurities such as boron. The impurity diffusion region 38 in which a P-type impurity such as boron is injected is formed on one main surface of the semiconductor substrate 1 located on the bottom surface of the element isolation groove 21 of the substrate 1, and is otherwise the same. is there.

Next, a method of manufacturing the semiconductor integrated circuit device thus configured will be described. The third embodiment is also manufactured in the same manner as the second embodiment, and is different from the second embodiment only in the following points. That is, although the polycrystalline silicon film 34 is formed in the step of FIG. 18 shown in the second embodiment, the doped polysilicon containing P-type impurities such as boron is deposited by CVD.
After laminating on the one main surface of the semiconductor substrate 1 by the method or the like, or after laminating the polycrystalline silicon 34 on the one principal surface of the semiconductor substrate 1, P of boron or the like is formed on the laminated polycrystalline silicon 34.
P-type impurities contained in the polycrystalline silicon are diffused into one main surface of the semiconductor substrate 1 by ion-implanting type impurities and performing heat treatment.

Even in the semiconductor integrated circuit device configured as described above, in addition to the same effect as the second embodiment, the impurity diffusion region 38 further improves the electrical insulation between the elements, and It has the advantage that the separation characteristics are improved.

In the above-mentioned Examples 1 to 3,
As the insulating film 20 forming the closed spaces 26 and 31, the one using an organic solution of silanol is shown, but the insulating film 20 is not limited to this, and it is a film that has an appropriate viscosity and can be formed by spin coating and heat treatment. Anything is good. For example, a polyimide resin film generally used as a protective film or an interlayer insulating film may be used.

[0063]

According to the first aspect of the present invention, since the element isolation groove is formed in the semiconductor substrate and the insulating film which forms a closed space with the element isolation groove is provided, the semiconductor in the element isolation region is provided. This has the effects of reducing defects in the substrate, preventing the occurrence of interface states, suppressing current leakage from the device to the semiconductor substrate, and ensuring electrical isolation between the devices.

According to a second aspect of the present invention, an element isolation groove is formed in a semiconductor substrate, a wall-shaped body is provided in the element isolation groove, and the side surface and the wall-shaped body of the element isolation groove are formed. Since the insulating film that forms the closed space is provided, defects in the semiconductor substrate in the element isolation region are reduced, interface states are not generated, current leakage from the element to the semiconductor substrate can be suppressed, and electrical isolation between elements is achieved. This has the effect of ensuring that

According to a third aspect of the present invention, an element isolation groove is formed in a semiconductor substrate, and a wall-shaped body made of polycrystalline silicon containing impurities of the same conductivity type as that of the semiconductor substrate is formed in the element isolation groove. An insulating film that forms a closed space between the side surface of the element isolation groove and the wall-like body is provided, and the same conductivity type as the semiconductor substrate is provided on one main surface of the semiconductor substrate located at the bottom surface of the element isolation groove. Since the impurity diffusion region is provided, the current leakage from the element to the semiconductor substrate can be suppressed, and the electrical isolation between the elements can be ensured.

Since the insulating film is a silicon oxide film or a polyimide resin film, the invention of claim 4 has the effect that the film thickness of the insulating film can be accurately controlled.

The invention of claim 5 of the present invention further has an effect that it is possible to prevent intrusion of water and active gas because the inert gas is enclosed in the closed space.

According to the sixth aspect of the present invention, the element isolation groove is formed on one main surface of the semiconductor substrate, and the insulating film which forms a closed space with the element isolation groove is formed. It has the effects of reducing defects in the semiconductor substrate in (1) and preventing interface states from occurring, suppressing current leakage from the element to the semiconductor substrate, and ensuring electrical isolation between the elements.

According to a seventh aspect of the present invention, the element isolation groove is formed on one main surface of the semiconductor substrate, the sidewall is formed on the side surface of the element isolation groove, and the wall shape is in contact with the side surface of the sidewall. Since the body is formed, the sidewalls are removed, and the insulating film that forms a closed space is formed by the side surface of the element isolation groove and the wall-shaped body, current leakage from the element to the semiconductor substrate can be suppressed, The effect is that electrical separation can be ensured and a closed space can be easily formed.

According to an eighth aspect of the present invention, an element isolation groove is formed on one main surface of a semiconductor substrate, a sidewall is formed on a side surface of the element isolation groove, and the semiconductor element is in contact with the side surface of the side wall. A wall-shaped body made of polycrystalline silicon containing impurities of the same conductivity type as the substrate is formed, sidewalls are removed, and an insulating film that forms a closed space is formed between the side surface of the element isolation groove and the wall-shaped body. Since the impurity diffusion region is formed on the one main surface of the semiconductor substrate by heat-treating the semiconductor substrate on which the wall-shaped body is formed, defects in the semiconductor substrate in the element isolation region are reduced and an interface state is not generated, The present invention has effects that current leakage from the element to the semiconductor substrate can be suppressed, electrical isolation between the elements can be ensured, a sealed space can be easily formed, and an impurity diffusion region can be easily formed.

According to a ninth aspect of the present invention, further, an organic solution of silanol is applied to one main surface of a semiconductor substrate having a groove for element isolation, and heat treatment is performed to add the organic solution of silanol to a silicon oxide film. Since the insulating film is made of, it has the effect that the insulating film for forming the closed space can be easily laid flat and accurately controlled in thickness.

The invention of claim 10 of the present invention further includes
A polyimide resin is applied to the one main surface of a semiconductor substrate having a groove for element isolation and is heat treated to form an insulating film made of a polyimide resin film. It also has the effect of easily forming a film having a precisely controlled film thickness.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 2 is a plan view showing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 12 is a sectional view showing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 13 is a plan view showing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 21 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 23 is a sectional view showing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 24 is a cross-sectional view showing two adjacent N-channel type MOS transistors by conventional LOCOS isolation.

FIG. 25 is a cross-sectional view showing a flow of forming a N-channel transistor by LOCOS isolation according to the related art in the order of steps.

FIG. 26 is a cross-sectional view showing a flow of forming an N-channel transistor by conventional LOCOS isolation in process order.

FIG. 27 is a cross-sectional view showing the flow of forming an N-channel transistor by conventional LOCOS isolation in the order of steps.

28A and 28B are cross-sectional views showing a flow of forming an N-channel transistor by conventional LOCOS isolation in the order of steps.

FIG. 29 is a sectional view showing a flow of forming an N-channel transistor by conventional LOCOS isolation in process order.

FIG. 30 is a cross-sectional view showing a flow of forming an N-channel transistor by conventional LOCOS isolation in process order.

FIG. 31 is a cross-sectional view showing the flow of forming an N-channel transistor by conventional LOCOS isolation in the order of steps.

FIG. 32 is a cross-sectional view showing two adjacent N-channel transistors by conventional trench isolation.

FIG. 33 is a sectional view showing, in the order of steps, a flow of forming two adjacent N-channel type MOS transistors by conventional trench isolation.

FIG. 34 is a cross-sectional view showing, in the order of steps, a flow of forming two adjacent N-channel type MOS transistors by conventional trench isolation.

FIG. 35 is a sectional view showing, in the order of steps, a flow of forming two adjacent N-channel type MOS transistors by conventional trench isolation.

FIG. 36 is a cross-sectional view showing, in the order of steps, a flow of forming two adjacent N-channel type MOS transistors by conventional trench isolation.

[Explanation of symbols]

1 semiconductor substrate, 2 n-channel M
OS transistor, one source / drain region,
4 other source / drain region, 5 channel region, 6 gate insulating film, 7 gate electrode,
8 oxide film for element isolation, 9 sidewall, 10
Interlayer insulating film, 11 one source / drain electrode,
12 other source / drain electrode, 13 current supply source, 14 silicon oxide film, 15 silicon nitride film, 16, 17, 18, 19 resist film, 20 insulating film, 21 element isolation groove, 22 resist pattern, 23 H ₂ Atmosphere, 24 interlayer insulating film, 2
5 conductive film, 26 hermetically sealed space, 27 wall-like body, 28
Insulating film, 29 sidewall, 30 bird's beak, 31 closed space, 32 leak current, 33 crystal defect, 34 polycrystalline silicon film,
35 element isolation trench, 36 silicon oxide film, 37
Element isolation oxide film, 38 impurity diffusion region.

Claims (10)

[Claims] 1. A semiconductor substrate having an element isolation groove formed on one main surface so as to surround an element formation region in which a semiconductor element is formed, the element isolation groove being formed on the element isolation groove of the semiconductor substrate. A semiconductor integrated circuit device comprising an insulating film that forms a closed space with a groove. 2. A semiconductor substrate having, on one main surface, an element isolation groove formed so as to surround an element formation region in which a semiconductor element is formed, and in contact with a bottom surface of the element isolation groove of the semiconductor substrate and from a side surface. A semiconductor integrated circuit having a wall-shaped body formed at a predetermined interval, and an insulating film formed on the element isolation groove of the semiconductor substrate and forming a closed space between the side surface of the element isolation groove and the wall-shaped body. apparatus. 3. A semiconductor substrate having an element isolation groove formed on one main surface so as to surround an element isolation region in which a semiconductor element is formed, and in contact with a bottom surface of the element isolation groove of the semiconductor substrate and from a side surface. A wall-shaped body made of polycrystalline silicon in which impurities are diffused and formed at a predetermined interval, and an impurity diffusion region formed on one main surface of the semiconductor substrate located on the bottom surface of the element isolation groove of the semiconductor substrate. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a silicon oxide film or a polyimide resin film. 5. The semiconductor integrated circuit device according to claim 1, wherein an inert gas is enclosed in the closed space. 6. A step of forming an element isolation groove on a main surface of a semiconductor substrate so as to surround an element formation region in which a semiconductor element is formed, the semiconductor substrate having the element isolation groove formed on the main surface. ,
A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming an insulating film that forms a closed space with the element isolation groove. 7. A step of forming an element isolation groove on a main surface of a semiconductor substrate so as to surround an element formation region in which a semiconductor element is formed, and sidewalls are formed on both side surfaces of the element isolation groove of the semiconductor substrate. The step of forming a wall-shaped body in contact with the bottom surface of the element isolation groove of the semiconductor substrate sandwiched by the sidewalls and in contact with the side surfaces of the sidewalls, and removing the sidewalls of the semiconductor substrate. A step of forming a space between the side surface of the element isolation groove and the wall-shaped body, the side surface of the element isolation groove and the side surface of the semiconductor substrate having the element isolation groove and the wall-shaped body formed thereon. A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming an insulating film that forms a closed space with a wall-shaped body. 8. A step of forming an element isolation groove in a main surface of a semiconductor substrate so as to surround an element formation region in which a semiconductor element is formed, and sidewalls are formed on both side surfaces of the element isolation groove of the semiconductor substrate. The step of forming a wall-shaped body in contact with the bottom surface of the element isolation groove of the semiconductor substrate sandwiched by the sidewalls and in contact with the side surfaces of the sidewalls, and removing the sidewalls of the semiconductor substrate. A step of forming a space between the side surface of the element isolation groove and the wall-shaped body, the side surface of the element isolation groove and the side surface of the semiconductor substrate having the element isolation groove and the wall-shaped body formed thereon. A step of forming an insulating film that forms a closed space together with the wall-like body; heat-treating the semiconductor substrate on which the element isolation groove and the wall-like body are formed to remove impurities contained in the wall-like body from the element; The above half located on the bottom of the separation groove The method of manufacturing a semiconductor integrated circuit device having a step of diffusing the one main surface of the body substrate to form an impurity diffusion region. 9. The step of forming an insulating film comprises the steps of applying an organic solution of silanol to one main surface of a semiconductor substrate having a groove for element isolation, and a step of applying the organic solution of silanol to the semiconductor substrate. 9. A method for manufacturing a semiconductor integrated circuit device according to claim 6, further comprising the step of performing heat treatment to form an organic solution of silanol into an insulating film made of a silicon oxide film. . 10. The step of forming an insulating film comprises the steps of applying a polyimide resin to one main surface of a semiconductor substrate having a groove for element isolation, and heat-treating the semiconductor substrate coated with the polyimide resin to obtain a polyimide. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising a step of forming an insulating film made of a resin film.