JPS57207349A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57207349A JPS57207349A JP9245481A JP9245481A JPS57207349A JP S57207349 A JPS57207349 A JP S57207349A JP 9245481 A JP9245481 A JP 9245481A JP 9245481 A JP9245481 A JP 9245481A JP S57207349 A JPS57207349 A JP S57207349A
- Authority
- JP
- Japan
- Prior art keywords
- poly
- oxidation
- substrate
- groove
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Abstract
PURPOSE:To contrive high integration, by a method wherein after the oxidation of a V groove on an Si substrate, Si3N4 and poly Si are laminated to leave poly Si on the groove bottom by the control of oxidation amount, and after selective oxidation, impurities are introduced except for the Si3N4 by utilizing the difference of oxidation film thicknesses or a hole on the groove bottom. CONSTITUTION:An N epitaxial layer 21 is grown on a P type Si substrate 11 with SiO222 and Si3N423 superposed to open for the etching of a groove reaching the substrate 11 laminating SiO224, Si3N425 and poly Si26. A thick poly Si layer is thermal-oxidized to form SiO2 27 and remaining poly Si 26' with good controllability. The film 27 is removed to eliminate the Si3N425 by a mask 26'. Successively, the mask 26' is removed to form a P<+> channel cut 29 by B ion implantation via the remaining SiO224'. Or the removal of the film 24' for B diffusion to cover with SiO232 is also available. Subsequently, the poly Si30 is formed for thermal oxidation of the surface to form SiO231. This constitution prevents a bird beak formation on the surface of the substrate of the V groove to form an active region to a small scale and in accuracy for obtaining IC high density.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9245481A JPS57207349A (en) | 1981-06-16 | 1981-06-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9245481A JPS57207349A (en) | 1981-06-16 | 1981-06-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57207349A true JPS57207349A (en) | 1982-12-20 |
Family
ID=14054832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9245481A Pending JPS57207349A (en) | 1981-06-16 | 1981-06-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57207349A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4499651A (en) * | 1982-08-20 | 1985-02-19 | Telefunken Electronic Gmbh | Method of manufacturing a field-effect transistor |
| KR100458767B1 (en) * | 2002-07-04 | 2004-12-03 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
-
1981
- 1981-06-16 JP JP9245481A patent/JPS57207349A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4499651A (en) * | 1982-08-20 | 1985-02-19 | Telefunken Electronic Gmbh | Method of manufacturing a field-effect transistor |
| KR100458767B1 (en) * | 2002-07-04 | 2004-12-03 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
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