JPS5799752A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS5799752A
JPS5799752A JP17469180A JP17469180A JPS5799752A JP S5799752 A JPS5799752 A JP S5799752A JP 17469180 A JP17469180 A JP 17469180A JP 17469180 A JP17469180 A JP 17469180A JP S5799752 A JPS5799752 A JP S5799752A
Authority
JP
Japan
Prior art keywords
substrate
type
layer
groove
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17469180A
Other languages
Japanese (ja)
Other versions
JPS5851417B2 (en
Inventor
Tetsuya Takayashiki
Taiji Usui
Tetsutada Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17469180A priority Critical patent/JPS5851417B2/en
Priority to US06/326,751 priority patent/US4408386A/en
Publication of JPS5799752A publication Critical patent/JPS5799752A/en
Publication of JPS5851417B2 publication Critical patent/JPS5851417B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent a warp, and to obtain the isolation separation type IC by a method wherein a groove section is formed to a p type Si substrate and coated with a p<+> layer, an n type island is shaped to the groove and coated with an n<+> layer, poly Si is deposited through an oxide film and a substrate is removed through etching. CONSTITUTION:The <100> of the p type Si substrate 11 is etched in an anisotropic shape and the groove is formed, the p<+> layer 13 and an n epitaxial layer 14 are stacked, and SiO2 mask 15 are shaped to concave sections 19a. The surface is patterned with high accuracy because there are the concave sections. V-shaped groove 20 are formed through anisotropic etching, the masks 15 are removed, and As is diffused with low concentration from the layer 13 and the n type islands 14a are coated selectively with the n<+> layers 16. SiO2 17 and poly Si 18 are laminated, the back of the substrate 11 is mirror-ground to expose the SiO2 17, and the insulating separation type substrate with p and n layers on the same plane is completed. According to this constitution, a warp of the substrate at the time when forming poly Si in an epitaxial shape is prevented, the crystalline strain of island regions is decreased, and the IC device having excellent characteristics is obtained.
JP17469180A 1980-12-12 1980-12-12 Method for manufacturing semiconductor integrated circuit device Expired JPS5851417B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP17469180A JPS5851417B2 (en) 1980-12-12 1980-12-12 Method for manufacturing semiconductor integrated circuit device
US06/326,751 US4408386A (en) 1980-12-12 1981-12-02 Method of manufacturing semiconductor integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17469180A JPS5851417B2 (en) 1980-12-12 1980-12-12 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5799752A true JPS5799752A (en) 1982-06-21
JPS5851417B2 JPS5851417B2 (en) 1983-11-16

Family

ID=15982989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17469180A Expired JPS5851417B2 (en) 1980-12-12 1980-12-12 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5851417B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6134954A (en) * 1984-07-25 1986-02-19 Matsushita Electric Works Ltd Manufacture of material for semiconductor device
US5952679A (en) * 1996-10-17 1999-09-14 Denso Corporation Semiconductor substrate and method for straightening warp of semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6134954A (en) * 1984-07-25 1986-02-19 Matsushita Electric Works Ltd Manufacture of material for semiconductor device
US5952679A (en) * 1996-10-17 1999-09-14 Denso Corporation Semiconductor substrate and method for straightening warp of semiconductor substrate

Also Published As

Publication number Publication date
JPS5851417B2 (en) 1983-11-16

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