JPS5799753A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS5799753A
JPS5799753A JP17529280A JP17529280A JPS5799753A JP S5799753 A JPS5799753 A JP S5799753A JP 17529280 A JP17529280 A JP 17529280A JP 17529280 A JP17529280 A JP 17529280A JP S5799753 A JPS5799753 A JP S5799753A
Authority
JP
Japan
Prior art keywords
layer
sio2
poly
grooves
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17529280A
Other languages
Japanese (ja)
Other versions
JPS628024B2 (en
Inventor
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17529280A priority Critical patent/JPS5799753A/en
Priority to DE19813129558 priority patent/DE3129558A1/en
Publication of JPS5799753A publication Critical patent/JPS5799753A/en
Priority to US06/507,557 priority patent/US4507849A/en
Publication of JPS628024B2 publication Critical patent/JPS628024B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To leave a separation layer in a V-shaped groove, to form an IC in an island region and to integrate the region by a method wherein an n<+> layer is stacked in an n epitaxial layer on a p type Si substrate with a buried layer, the n<+> layer is separated by the V-shaped groove, a poly Si layer is deposited to bury the groove, n type impurities are diffused from the inside and the outside, and the surface is etched. CONSTITUTION:An n<+> buried layer 2 is formed to a (911) surface of the p type Si substrate 11, the n epitaxial layer 3 is stacked, and SiO2 4, Si3N4 5 and PSG6 are deposited. The films 6-4 are opened, and the V-shaped grooves 7a, 7b reaching the substrate 1 are shaped through etching to form the island 7c. SiO2 8 is molded on the surfaces of the grooves at a high temperature under high pressure, and poly Si 9 is deposited to bury the grooves completely. P is diffused from the surface and diffused outward from the film 6 of the layer 7c, and an n<+> layer 11 is formed and overlapped on a layer 10. The n<+> poly Si 10, 11 are removed preferentially through plasma etching, etc., and poly Si 9a, 9b are left only in the grooves. The PSG6 is removed through etching, the surface is coated with SiO2 12, the Si3N4 5 and the SiO2 12 are removed through etching, the surface is coated with SiO2 13, and the desired device is manufactured in the island 7c. According to this constitution, the minute separation layer is simply obtained.
JP17529280A 1980-07-28 1980-12-12 Manufacture of semiconductor integrated circuit Granted JPS5799753A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP17529280A JPS5799753A (en) 1980-12-12 1980-12-12 Manufacture of semiconductor integrated circuit
DE19813129558 DE3129558A1 (en) 1980-07-28 1981-07-27 METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT
US06/507,557 US4507849A (en) 1980-07-28 1983-06-24 Method of making isolation grooves by over-filling with polycrystalline silicon having a difference in impurity concentration inside the grooves followed by etching off the overfill based upon this difference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17529280A JPS5799753A (en) 1980-12-12 1980-12-12 Manufacture of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS5799753A true JPS5799753A (en) 1982-06-21
JPS628024B2 JPS628024B2 (en) 1987-02-20

Family

ID=15993558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17529280A Granted JPS5799753A (en) 1980-07-28 1980-12-12 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5799753A (en)

Also Published As

Publication number Publication date
JPS628024B2 (en) 1987-02-20

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