JPS5737849A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5737849A
JPS5737849A JP11421080A JP11421080A JPS5737849A JP S5737849 A JPS5737849 A JP S5737849A JP 11421080 A JP11421080 A JP 11421080A JP 11421080 A JP11421080 A JP 11421080A JP S5737849 A JPS5737849 A JP S5737849A
Authority
JP
Japan
Prior art keywords
substrate
oxidation
layer
etching
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11421080A
Other languages
Japanese (ja)
Inventor
Masatoshi Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11421080A priority Critical patent/JPS5737849A/en
Publication of JPS5737849A publication Critical patent/JPS5737849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To remove the spread section of an oxidation layer due to a bird-beak, and to integrate the device to a high degree by oxidizing a substrate by using an oxidation-resisting mask and etching a surface section of the selective oxidation layer after removing the mask. CONSTITUTION:An insulating film 14 consisting of a thin oxide film 12 and a nitride film 13 is formed on the P type Si substrate 11, openings 15 are shaped in separation regions between elements, and the substrate 11 is etched up to the predetermined depth. Opening regions are oxidized using the insulating film 14 as the oxidation-resisting mask layer, and the field oxide films 16 are formed. The mask layer 14 is removed, and a part of the surface layer is removed by employing an etchant, the speed of etching thereof to the oxide film is equal to the speed of etching to Si or is faster than that to Si. An element preparing process is executed in such a manner that wiring layers 17 are shaped by diffusing N type impurities while using the exposed sections of the substrate as element forming regions. Ac cordingly, since the surface layer sections of the selective oxidation layers 16 remarkably spreading in the lateral direction are removed, the width of the separation regions between the elements can be shaped narrowly, and the device can be integrated to a high degree.
JP11421080A 1980-08-20 1980-08-20 Manufacture of semiconductor device Pending JPS5737849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11421080A JPS5737849A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11421080A JPS5737849A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5737849A true JPS5737849A (en) 1982-03-02

Family

ID=14631960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11421080A Pending JPS5737849A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5737849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057451A (en) * 1990-04-12 1991-10-15 Actel Corporation Method of forming an antifuse element with substantially reduced capacitance using the locos technique

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139263A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Method of selective oxidation of silicon substrate
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139263A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Method of selective oxidation of silicon substrate
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057451A (en) * 1990-04-12 1991-10-15 Actel Corporation Method of forming an antifuse element with substantially reduced capacitance using the locos technique

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