JPS56137648A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56137648A
JPS56137648A JP4049780A JP4049780A JPS56137648A JP S56137648 A JPS56137648 A JP S56137648A JP 4049780 A JP4049780 A JP 4049780A JP 4049780 A JP4049780 A JP 4049780A JP S56137648 A JPS56137648 A JP S56137648A
Authority
JP
Japan
Prior art keywords
silicon dioxide
substrate
silicon
mask
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4049780A
Other languages
Japanese (ja)
Inventor
Shunji Sasabe
Kensuke Nakada
Yasushi Hatta
Takehisa Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4049780A priority Critical patent/JPS56137648A/en
Publication of JPS56137648A publication Critical patent/JPS56137648A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a stepless surface of a substrate and prevent wire cuts by building up a silicon dioxide of sufficient thickness on a silicon dioxide film of a silicon substrate using a bias sputtering and causing the substrate surface to be exposed through the etching of a flattened surface. CONSTITUTION:A silicon tetranitride mask 11 is applied on n<-> type silicon substrate to provide a wet oxidation so tha a silicon dioxide 12 is created, and then the mask is removed. A silicon dioxide 13 with a smooth flat surface is formed by means of bias sputtering. Next, bird head parts of silicon dioxide 13 and silicon dioxide 12 are etched simultaneously with the help of HF+NH4F solution. If the silicon dioxide is treated at approximately 1,000 deg.C after sputtering, an etching velocity ratio represents almost 1. If the silicon dioxide is etched until the substrate surface is exposed, a silicon dioxide surface 14b and a substrate surface 14a form a common plane. After this process, an isoplaner structure can be formed on a stepless surface, so that wiring in a region surrounded by a silicon dioxide does not have any breakdown in the stepped part, thus enabling free layout and high integration to be realized.
JP4049780A 1980-03-31 1980-03-31 Manufacture of semiconductor device Pending JPS56137648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4049780A JPS56137648A (en) 1980-03-31 1980-03-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4049780A JPS56137648A (en) 1980-03-31 1980-03-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56137648A true JPS56137648A (en) 1981-10-27

Family

ID=12582196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4049780A Pending JPS56137648A (en) 1980-03-31 1980-03-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56137648A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234850A (en) * 1984-05-08 1985-11-21 Canon Inc Liquid jet recording head
US4853344A (en) * 1988-08-12 1989-08-01 Advanced Micro Devices, Inc. Method of integrated circuit isolation oxidizing walls of isolation slot, growing expitaxial layer over isolation slot, and oxidizing epitaxial layer over isolation slot
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate
US5019526A (en) * 1988-09-26 1991-05-28 Nippondenso Co., Ltd. Method of manufacturing a semiconductor device having a plurality of elements

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234850A (en) * 1984-05-08 1985-11-21 Canon Inc Liquid jet recording head
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate
US4853344A (en) * 1988-08-12 1989-08-01 Advanced Micro Devices, Inc. Method of integrated circuit isolation oxidizing walls of isolation slot, growing expitaxial layer over isolation slot, and oxidizing epitaxial layer over isolation slot
US5019526A (en) * 1988-09-26 1991-05-28 Nippondenso Co., Ltd. Method of manufacturing a semiconductor device having a plurality of elements

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