JPS5518003A - Manufacturing semiconductor device - Google Patents

Manufacturing semiconductor device

Info

Publication number
JPS5518003A
JPS5518003A JP8992778A JP8992778A JPS5518003A JP S5518003 A JPS5518003 A JP S5518003A JP 8992778 A JP8992778 A JP 8992778A JP 8992778 A JP8992778 A JP 8992778A JP S5518003 A JPS5518003 A JP S5518003A
Authority
JP
Japan
Prior art keywords
poly
gate
layer
width
density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8992778A
Other languages
Japanese (ja)
Inventor
Sumio Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8992778A priority Critical patent/JPS5518003A/en
Publication of JPS5518003A publication Critical patent/JPS5518003A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE: To obtain a double-aligned-type MOSFET by narrowing a diffused layer and providing a low-resistance second-gate poly Si, with the first-gate width being assuredly shorter than the second-poly-Si width.
CONSTITUTION: A high-density P+poly-Si layer 3, a second oxidized-film 4, and a P poly-Si layer 5 whose density is lower than that of the layer 3 are laminated on a gate-oxidized film 2 of a P-type substrate 1. Then, a high-density PSG or doped- oxidized film 8 is deposited thereon. When the grid-hatched portion of the layers 3 and 4 in the Figure are etched out by utilizing the etching speed of the poly-Si layers 3 and 5, with a resist 6 being a mask, the first-gate-poly-Si width becomes shorter than the second-poly-Si width. Thereafter, the resist 6 is removed and a second doped-oxidized film 9 is applied as shown in the Figure. In this constitution, a short channel is formed with a shallow diffused layer, whereby large-scale integration can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP8992778A 1978-07-25 1978-07-25 Manufacturing semiconductor device Pending JPS5518003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8992778A JPS5518003A (en) 1978-07-25 1978-07-25 Manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8992778A JPS5518003A (en) 1978-07-25 1978-07-25 Manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5518003A true JPS5518003A (en) 1980-02-07

Family

ID=13984324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8992778A Pending JPS5518003A (en) 1978-07-25 1978-07-25 Manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5518003A (en)

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