JPS5529106A - Manufacturing of semiconductor device - Google Patents
Manufacturing of semiconductor deviceInfo
- Publication number
- JPS5529106A JPS5529106A JP10176278A JP10176278A JPS5529106A JP S5529106 A JPS5529106 A JP S5529106A JP 10176278 A JP10176278 A JP 10176278A JP 10176278 A JP10176278 A JP 10176278A JP S5529106 A JPS5529106 A JP S5529106A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- poly
- zero
- difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
PURPOSE: To reduce the difference in pattern exchange to almost zero by making use of selective oxidation without spoiling the masking effect against the field ion injection.
CONSTITUTION: A heat-oxide film 2, a Si3N4 film 3 and a poly Si film 8 are placed on a p-type Si crystal 1, and the film 8 is etched with a resist mask 5. Next, the remaining Si is completely oxidized by means of wet oxidation to form a glass layer 9, and the films 3 and 2 are removed by a mask 9. Then B ions are injected to form a p+-type inversion-preventive layer 6, and a thick field oxide film 7 is built up by means of wet oxidation while removing the mask 9. Finally, an element area 10 is made by removing Si3N43. By so doing, the side etching amount at the time of patterning is reduced because of the utilization of the poly Si film 8, and the following oxidizing process will increase the thickness of the film laterally and reduce the difference in pattern exchange to almost zero.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10176278A JPS5529106A (en) | 1978-08-23 | 1978-08-23 | Manufacturing of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10176278A JPS5529106A (en) | 1978-08-23 | 1978-08-23 | Manufacturing of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5529106A true JPS5529106A (en) | 1980-03-01 |
JPS616542B2 JPS616542B2 (en) | 1986-02-27 |
Family
ID=14309234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10176278A Granted JPS5529106A (en) | 1978-08-23 | 1978-08-23 | Manufacturing of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5529106A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58501448A (en) * | 1981-09-08 | 1983-08-25 | エヌ・シ−・ア−ル・コ−ポレ−シヨン | Method of manufacturing integrated circuit structures |
US5208181A (en) * | 1992-08-17 | 1993-05-04 | Chartered Semiconductor Manufacturing Pte Ltd. | Locos isolation scheme for small geometry or high voltage circuit |
-
1978
- 1978-08-23 JP JP10176278A patent/JPS5529106A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58501448A (en) * | 1981-09-08 | 1983-08-25 | エヌ・シ−・ア−ル・コ−ポレ−シヨン | Method of manufacturing integrated circuit structures |
JPH0519308B2 (en) * | 1981-09-08 | 1993-03-16 | Ncr Co | |
US5208181A (en) * | 1992-08-17 | 1993-05-04 | Chartered Semiconductor Manufacturing Pte Ltd. | Locos isolation scheme for small geometry or high voltage circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS616542B2 (en) | 1986-02-27 |
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