JPS5776856A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5776856A JPS5776856A JP15266980A JP15266980A JPS5776856A JP S5776856 A JPS5776856 A JP S5776856A JP 15266980 A JP15266980 A JP 15266980A JP 15266980 A JP15266980 A JP 15266980A JP S5776856 A JPS5776856 A JP S5776856A
- Authority
- JP
- Japan
- Prior art keywords
- film
- si3n4
- layer
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
Abstract
PURPOSE:To form an element separating film having the small difference of dimensional conversion by selectively oxidizing a material layer, the speed of oxidation thereof is faster than the semiconductor substrate, formed onto the substrate while using Si3N4 as a mask and removing the Si3N4 film and an oxynitride film. CONSTITUTION:A phosphorus doped polycrystal Si layer 13' is shaped onto the P type Si substrate 11 through a terminal oxide film 12, the Si3N4 layer 15 is formed selectively on the surface through a thin oxide film 14, a field oxide film 16 is molded by selectively oxidizing the whole while using the Si3N4 layer 15 as a mask, and the Si3N4 film 15 is removed while the oxynitride layers 16, 17 formed at the end sections of the layer 13' are taken off, and succeeding processes are conducted. Accordingly, the element separating film having few defectes can be shaped while the difference of dimensional conversion can be decreased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15266980A JPS5776856A (en) | 1980-10-30 | 1980-10-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15266980A JPS5776856A (en) | 1980-10-30 | 1980-10-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5776856A true JPS5776856A (en) | 1982-05-14 |
Family
ID=15545502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15266980A Pending JPS5776856A (en) | 1980-10-30 | 1980-10-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5776856A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0075875A2 (en) * | 1981-09-28 | 1983-04-06 | General Electric Company | Method of making integrated circuits comprising dielectric isolation regions |
JPS58194382A (en) * | 1982-05-08 | 1983-11-12 | Matsushita Electric Ind Co Ltd | Electrode structure for semiconductor device |
US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
US5002898A (en) * | 1989-10-19 | 1991-03-26 | At&T Bell Laboratories | Integrated-circuit device isolation |
US5338750A (en) * | 1992-11-27 | 1994-08-16 | Industrial Technology Research Institute | Fabrication method to produce pit-free polysilicon buffer local oxidation isolation |
US5432113A (en) * | 1992-08-04 | 1995-07-11 | Nippon Steel Corporation | Method of making a semiconductor memory device |
-
1980
- 1980-10-30 JP JP15266980A patent/JPS5776856A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0075875A2 (en) * | 1981-09-28 | 1983-04-06 | General Electric Company | Method of making integrated circuits comprising dielectric isolation regions |
JPS58194382A (en) * | 1982-05-08 | 1983-11-12 | Matsushita Electric Ind Co Ltd | Electrode structure for semiconductor device |
JPH0451991B2 (en) * | 1982-05-08 | 1992-08-20 | Matsushita Electric Ind Co Ltd | |
US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
US5002898A (en) * | 1989-10-19 | 1991-03-26 | At&T Bell Laboratories | Integrated-circuit device isolation |
JPH03145730A (en) * | 1989-10-19 | 1991-06-20 | American Teleph & Telegr Co <Att> | Manufacture of ic semiconductor device |
US5432113A (en) * | 1992-08-04 | 1995-07-11 | Nippon Steel Corporation | Method of making a semiconductor memory device |
US5338750A (en) * | 1992-11-27 | 1994-08-16 | Industrial Technology Research Institute | Fabrication method to produce pit-free polysilicon buffer local oxidation isolation |
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