JPS628024B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit that improves the method of forming semiconductor element isolation regions.

Semiconductor integrated circuits are becoming larger and larger due to increased integration capacity and diversification of logic functions.
Along with this, there is a growing demand for miniaturization of semiconductor elements down to the submicron level. Therefore, there is a strong demand for improvements in element isolation technology suitable for such miniaturization.

Conventionally, various methods of separating semiconductor elements using dielectric materials have been proposed as techniques suitable for this miniaturization. For example, (1) selective oxidation isolation technology (LOCOS method, Isoplaner method) that isolates elements by selectively changing a part of the silicon substrate to thick SiO ₂ ;
(2) A method of isolating elements by making a part of the silicon substrate porous and further oxidizing it (IPOS
method) (3), a method in which the area to be separated is anisotropically etched into a V-shape, the surface is oxidized, polycrystalline silicon is embedded, and then mechanically polished and flattened (VIP method, V-ATE method) It has been known.

Each of these element isolation techniques has its advantages and disadvantages, and it is necessary to apply them in a manner that takes advantage of their characteristics depending on the type of semiconductor device. For example, (1) above
selective oxidation isolation technology is MOS-LSI, bipolar
It is applied to LSI, etc., and is considered the most effective technology for achieving high integration. However, this method requires high-temperature oxidation for a long time, so
- In LSI, the width of the channel region that determines the characteristics changes due to pattern deformation due to side oxidation, resulting in variations in characteristics, and in the selective oxidation separation method in which the silicon substrate is etched and then oxidized, so-called bird's beaks and bird's heads occur. Problems include that there is a risk that the Al wiring may break, and in bipolar LSIs, outward diffusion from the buried layer may occur, resulting in a reduction in junction breakdown voltage.

The porous isolation method described in (2) above also causes volume changes due to subsequent oxidation, which causes problems such as distortion of the silicon substrate, substrate destruction, and junction leakage, so it has not yet been put into practical use. Not yet. Furthermore, the problems with the separation technology (3) above are concentrated in the surface polishing technology, there are problems with processing accuracy, high costs due to lower yields, negative effects on device characteristics due to mechanical polishing, etc. It has not been put into practical use except in some cases.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a device isolation method capable of forming flat and fine device isolation regions through simple steps.

That is, the present invention includes a step of epitaxially growing a semiconductor layer of a first conductivity type on a semiconductor substrate; and forming a plurality of deposited layers having different characteristics on the surface of the semiconductor layer, including a top layer containing a high concentration of impurities. a step of selectively removing the deposited layer at a location to become an isolation region; using the deposited layer as a mask, forming a groove penetrating the semiconductor layer of the first conductivity type; a step of forming an island region; a step of depositing a semiconductor layer for element isolation to such an extent that the groove is completely filled over the entire upper surface; and a step of diffusing impurities at a high concentration from the surface of the semiconductor layer for element isolation. At the same time, a step of outwardly diffusing the impurity in the uppermost layer and continuing the diffusion until the diffusion regions from both regions overlap each other; etching to leave the semiconductor layer for element isolation only in the groove, forming an element isolation region between the island regions; forming at least one pn junction for configuring a semiconductor element in the island region; The present invention provides a method for manufacturing a semiconductor integrated circuit comprising the above steps.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a bipolar integrated circuit using a silicon substrate will be described with reference to the drawings.

First, as shown in FIG. 1a, a buried layer 2 having a high concentration of n-type impurities is formed on one main surface of a p-type silicon semiconductor substrate 1 having, for example, a (911) plane.
Subsequently, an n-type epitaxial layer 3 is formed on the surface using a normal epitaxial growth method. Next, as shown in FIG. 1b, a SiO ₂ film 4 of approximately 500 Å is deposited on the surface of this epitaxial layer 3 in an oxidizing atmosphere.
After the growth, a Si ₃ N ₄ film 5 of approximately 3000 Å is deposited thereon by CVD and sintered at 1000° C. in an N ₂ atmosphere. Subsequently, a PSG film 6 containing a high concentration of n-type impurities, such as phosphorus, is deposited thereon to a thickness of approximately 3000 Å by CVD. Next, as shown in Figure 1c, the areas to be separated are created using photolithography.
The PSG film 6, Si ₃ N ₄ film 5 and SiO ₂ film 4 are removed by etching, and then anisotropic etching is performed in a V-shape to a depth penetrating the epitaxial layer 3 using a KOH-based etching agent to form a V-shaped groove 7a. , 7b and an island region 7c therebetween. Next, 900℃, 9
These V grooves 7a and 7b are formed in a high pressure oxygen atmosphere.
After growing a SiO ₂ film 8 of about 2000 Å on the surface, a polycrystalline silicon film 9 is grown by CVD as shown in Figure 1d.
It is deposited on the entire surface of the substrate 1, including the grooves 7a and 7b, by a method, and grown to a thickness that completely fills the grooves 7a and 7b.

Then, as shown in Figure 1 d, the temperature was increased to 1000°C.
In a POCl ₃ atmosphere, phosphorus is removed from the polycrystalline silicon layer 9.
It is diffused from the surface to form an n ⁺ type impurity layer 10. In this phosphorus diffusion process, phosphorus is diffused from the surface of the polycrystalline silicon layer 9 and at the same time, the island region 7c
Also from the PSG film 6, phosphorus diffuses outward into the polycrystalline silicon layer 9, and an n ⁺ type impurity layer 11 is formed. Then, these n ⁺ type impurity layers 10 and 11 are sufficiently diffused until they overlap each other. For example, heat treatment is performed at 1000° C. for 30 minutes in a POCl ₃ atmosphere. Through this heat treatment, the entire polycrystalline silicon on the island region 7c changes into an n ⁺ type impurity layer, but the groove 7
It is possible to leave a polycrystalline silicon layer that does not become n ⁺ type in a and 7b.

Next, the n ⁺ type polycrystalline silicon layer is etched more quickly than polycrystalline silicon containing no impurities, such as a method using an appropriate etching agent such as a mixture of I ₂ + HF + CH ₃ COOH, a plasma etching method, or a reaction method. The n ⁺ -type polycrystalline silicon layers 10 and 11 are preferentially etched away using an ion etching method or the like, and the polycrystalline silicon layers 9a and 9b are formed only in the grooves 7a and 7b as shown in FIG. 1e.
leave. Next, as shown in FIG. 1f, after removing the PSG film 6 by etching,
Using the Si ₃ N ₄ film 5 as a mask, the groove 7 is formed at a high temperature of
Polycrystalline silicon layer 9 remaining in a, 7b
The surfaces a and 9b are selectively oxidized to form a SiO ₂ film 12 of about 4000 Å. Then, as shown in Figure 1g,
After removing the Si ₃ N ₄ 5 and the SiO ₂ film 12,
An oxide film 13 is grown on the entire surface, and then at least one
A number of pn junctions are formed in the island region 7c, and the process proceeds to a process for forming a desired semiconductor device. For example, FIG. 1h shows an embodiment of a bipolar integrated circuit, in which 14 is an emitter, 15 is a collector contact, and 16 is a base.

As is clear from the example in Fig. 1 h, the island area 7
The end of the pn junction formed in c is the concave groove 7.
It has reached the sides of a and 7b. Therefore, this method makes it possible to reduce junction capacitance and the like.

The advantages of the isolation method between semiconductor elements according to the present invention are as follows.

(b) Planarization is achieved by a simple chemical etching method without using mechanical polishing techniques such as the conventional V-shaped etching separation method, which improves yield and reduces manufacturing costs, as well as improves device characteristics. There are no negative effects.

(b) Since it does not require long-term heat treatment at high temperatures like selective oxidation separation technology, redistribution of impurity diffusion layers before the element isolation process can be almost ignored.

(c) Unlike selective oxidation separation technology, there is no need to selectively grow a thick oxide film, so pattern deformation does not occur, and since anisotropic etching is used, island regions can be formed almost at the mask dimensions. stipulated,
Isolation of devices having epitaxial layers, such as bipolar integrated circuits or SOS, can be achieved as designed.

(d) Reduction of junction capacitance, which is a feature of dielectric separation method,
It is also possible to improve the degree of integration, reduce stray capacitance of wiring, etc. as in the conventional case.

In addition, in the above embodiment, a case was explained in which a PSG film was used as the top layer of the island region in order to outward diffuse n-type impurities, but in addition, a polycrystalline silicon film doped with phosphorus or arsenic at a high concentration, Alternatively, an amorphous silicon film may be used.
Furthermore, when selectively removing the n ⁺ type polycrystalline silicon layers 18 and 19, the fact that the oxidation rate of the highly impurity-concentrated polycrystalline silicon film is much faster than that of the non-doped polycrystalline silicon film is utilized. However, it is also possible to flatten the surface by repeatedly oxidizing and removing polycrystalline silicon with a high impurity concentration at low temperature and high pressure.

[Brief explanation of the drawing]

FIGS. 1A to 1H are cross-sectional views of a semiconductor device showing the device isolation method according to the present invention in the order of steps. In the figure, 1...substrate, 2...buried layer, 3...n
Type epitaxial layer, 4... SiO ₂ film, 5...
Si ₃ N ₄ film, 6...PSG film, 7a, 7b...V groove,
7c... Island region, 8... SiO ₂ film, 9, 9a, 9
b... Polycrystalline silicon film, 10, 11... n ⁺ type impurity layer, 12, 13... SiO ₂ film, 14... Emitter, 15... Collector contact, 16...
base.

Claims (1)

[Claims] 1. A step of epitaxially growing a semiconductor layer of a first conductivity type on a semiconductor substrate; and a plurality of deposited layers having different characteristics, including a top layer containing a high concentration of impurities on the surface of the semiconductor layer. selectively removing the deposited layer at a location to become an isolation region; using the deposited layer as a mask, forming a groove penetrating the semiconductor layer of the first conductivity type; a step of forming an island region in between; a step of depositing a semiconductor layer for element isolation to such an extent that the groove is completely filled over the entire upper surface; and a step of removing impurities from the surface of the semiconductor layer for element isolation at a high concentration. At the same time as the diffusion, the impurity in the uppermost layer is diffused outward, and the diffusion is continued until the diffusion regions from both overlap with each other; and a semiconductor layer for element isolation in which this impurity is diffused at a high concentration is selected. etching to form a device isolation region between the island regions by leaving the device isolation semiconductor layer only in the groove;
A method for manufacturing a semiconductor integrated circuit, comprising the step of forming at least one pn junction. 2. The manufacturing method according to claim 1, wherein the substrate is a second conductivity type semiconductor substrate having one or more buried layers of the first conductivity type on its main surface. 3. The manufacturing method according to claim 2, wherein at least a part of the pn junction terminates on the side surface of the groove. 4. The manufacturing method according to claim 1, wherein the uppermost layer is one selected from a SiO ₂ film containing phosphorus or arsenic, a polycrystalline silicon film, and a silicon amorphous film. 5. The manufacturing method according to claim 1, wherein the impurity diffused from the surface of the semiconductor layer is one selected from phosphorus and arsenic. 6 The semiconductor substrate is a p-type silicon semiconductor,
The first conductivity type is n-type, and the top layer of the deposited layer is n-type.
The step of depositing a semiconductor layer for element isolation in the groove includes a step of previously forming an oxide layer on the inner surface of the groove, and the semiconductor layer for element isolation contains polycrystalline silicon at a high concentration. The impurity diffused from the surface of the semiconductor layer for element isolation is phosphorus, and following the step of leaving the semiconductor layer for element isolation only in the groove, the surface of the semiconductor layer is oxidized. The manufacturing method according to claim 1, characterized in that the manufacturing method includes the steps of: