JPS57199234A - Semiconductor integrated circuit device and manufacture thereof - Google Patents
Semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPS57199234A JPS57199234A JP8522781A JP8522781A JPS57199234A JP S57199234 A JPS57199234 A JP S57199234A JP 8522781 A JP8522781 A JP 8522781A JP 8522781 A JP8522781 A JP 8522781A JP S57199234 A JPS57199234 A JP S57199234A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- stage
- mask
- collector buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To improve high voltage resisting of element, by a method wherein first stage in an oxide film to isolate between elements is formed to attain collector buried layer and second stage thereof is formed in epitaxial layer. CONSTITUTION:Collector buried layer 2 is formed on P type Si substrate 1, and then N type epitaxial layer 3 is grown. The layer 3 is etched using a photo resist film 6 as a mask and a resist film 19 is formed. The layer 3 is etched using the resist film as a mask and boron ion is implanted thereby a channel preventing layer 7 is formed. After removing the resist films 6, 19, selective oxidation is performed using an oxide film 4 as a mask thereby an isolation oxide film 8 is formed. The isolation oxide film 8 is formed in two-stage structure contacting with collector buried layers 9a, 9b, thereby surface stage difference can be reduced and high voltage resisting is improved by making the epitaxial layer thick.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8522781A JPS57199234A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8522781A JPS57199234A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device and manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57199234A true JPS57199234A (en) | 1982-12-07 |
JPS6217868B2 JPS6217868B2 (en) | 1987-04-20 |
Family
ID=13852674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8522781A Granted JPS57199234A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57199234A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4888301A (en) * | 1987-09-30 | 1989-12-19 | Siemens Aktiengesellschaft | Method for generating a sunken oxide |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5661140A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1981
- 1981-06-01 JP JP8522781A patent/JPS57199234A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5661140A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4888301A (en) * | 1987-09-30 | 1989-12-19 | Siemens Aktiengesellschaft | Method for generating a sunken oxide |
Also Published As
Publication number | Publication date |
---|---|
JPS6217868B2 (en) | 1987-04-20 |
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