JPH0595043A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacture of element isolating structure which does not cause a kink and is excellent in micronization. CONSTITUTION:Polycrystalline silicon 9 is charged inside the groove in an element isolating area by the selective growth using the polycrystalline silicon film 7 at the bottom of the groove as a growth nucleus, and the periphery of the polycrystalline silicon 7 is covered with an insulating film 6 and is made a semiconductor substrate. Furthermore, a field insulating film 11 is made at the surface of the polycrystalline silicon 9 by selective oxidation. Hereby, without forming a cavity inside the groove, selective growth is possible even if the semiconductor substrate is not exposed from the bottom of the groove, and the polycrystalline silicon 9 can be charged equally. Furthermore, since the polycrystalline silicon 9 charged in the groove has shield effect, the occurrence of the kinks are prevented in the adjacent element, and the stabilization can be materialized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of filling a conductive film in a groove in a fine groove type element isolation structure which enables high integration.

[0002]

2. Description of the Related Art When attempting to embed polycrystalline silicon in a groove, a technique called etch back has been conventionally used. The details will be described with reference to FIG.

First, as shown in FIG. 19A, a thermal oxide film 2 is formed on a semiconductor substrate 1, a nitride film 3 and an oxide film 4 are further deposited, and then these are patterned by lithography and dry etching to form an element. Leave it in the area. In the other region, that is, in the element isolation region, the semiconductor substrate 1 is further cut to form the groove 5. Then, an oxide film 6 is formed in the groove by thermal oxidation in order to insulate the polycrystalline silicon embedded in the groove.

Next, as shown in FIG. 19B, polycrystalline silicon 20 is deposited on the entire surface until the groove is filled. Its thickness is about the depth of the groove. At this time, in a region where the depth of the groove is more than twice the width of the groove, a cavity 22 may occur inside the groove as shown on the left side of FIG. A boundary line 21 is formed on the upper part of the groove because the polycrystalline silicon 20 grown from both sides of the groove collides with it. This cavity 22 is always generated when the size of the opening of the groove is smaller than the internal size of the groove.

As shown in FIG. 19C, a resist film 8 is applied and the surface is flattened, and then etching without a selection ratio such as sputter etching is performed. Evenly until it becomes. At this point, the oxide film 4, polycrystalline silicon and resist 8 are exposed from the surface. Next, after removing the oxide film 4 in the element region with an aqueous solution of hydrogen fluoride or the like, using the nitride film 3 and the resist 8 as a mask, the polycrystalline silicon 20 is selectively removed until the surface becomes the surface of the substrate 1 in the element region. Perform anisotropic etching. After that, the remaining resist 8 is removed by oxygen ashing, and then selective oxidation is performed using the nitride film 3 as a mask as in the conventional case to form a field oxide film on the polycrystalline silicon 20 in the element isolation region. As a method of burying the silicon film in the groove, there is a selective growth using the bottom surface of the groove as a growth nucleus. This method is described in JP-A-2-205340. The outline of this method will be described with reference to FIG.

First, as shown in FIG. 20A, similarly to the above, an oxide film 2 is formed on a semiconductor substrate 1 by thermal oxidation, and then a nitride film 3 is deposited, and these are deposited in an element region by lithography and dry etching. Remain, other areas
A groove is further formed in the (element isolation region). After that, in order to prevent a short circuit between the same electric film embedded in the groove and a diffusion layer to be formed later, an insulating film 5 is formed in the groove by oxidation or deposition.

Next, the insulating film 5 on the bottom surface of the groove is removed by anisotropic whole surface etching to expose the semiconductor substrate 1 from the bottom surface of the groove. This exposed semiconductor substrate is used as a growth nucleus, and FIG.
By performing selective growth as shown in (b), the groove is filled with single crystal silicon or polycrystalline silicon 9. Since this technique uses selective growth, the silicon film does not grow on the nitride film 3 and the sidewall of the groove does not grow from the insulating film 5, so that even in a deep groove. The cavity shown in 19 is not generated. The rest is nitride film 3
By using this as a mask to perform selective oxidation, a field oxide film is formed on the silicon film 9 in the element isolation region.

[0008]

First, regarding the conventional manufacturing method shown in FIG. 19, as a first problem, the cavity 22 formed in the groove may be exposed after the completion of the etch back in some cases. There is no problem if the cavity 22 is closed during the subsequent field oxidation, but if it remains, problems such as etching residue when forming the gate electrode will occur, causing fatal damage such as short circuit of the gate electrode. There are cases like this.

Further, in the conventional manufacturing method shown in FIG. 20, it is possible to fill the groove with a silicon film without forming a cavity in the groove. However, as a second problem, in order to prevent a kink that occurs in an adjacent MOS transistor due to an increase in potential in the silicon film 9 filled in the groove, the silicon film 9 filled in the groove is formed.
It is necessary to add a high concentration of impurities. However, since the silicon film 9 filled in the groove is in contact with the substrate at the bottom surface of the groove, it is necessary to use ion implantation to add impurities, and it is necessary to separately implant ion species in the n-channel and p-channel. There is a problem that the number of processes increases.

[0010]

As a means for solving the problems described above, the first problem can be solved by using the selective growth with the groove bottom as the growth nucleus as described above.

Regarding the second problem, it suffices that the silicon film filled in the groove does not come into contact with the semiconductor substrate, and selection can be made using the groove bottom as a growth nucleus. Therefore, growth nuclei are formed on the bottom surface of the groove while leaving the insulating film on the sidewall and bottom surface of the groove. As a means for achieving this, first, a groove is formed in the element isolation region, an insulating film is formed in the groove, and then a thin polycrystalline silicon film is deposited. Then, by ion implantation of boron and concentration difference etching using a hydrazine solution, the p-type polycrystalline silicon film can be selectively left on the bottom surface of the trench in the element isolation region and the top surface of the element region. Then, a resist is embedded in the groove and the p-type polycrystalline silicon film in the element region is removed, so that the polycrystalline silicon film that serves as a nucleus for selective growth can be left only on the bottom surface of the groove.

[0012]

By the above means, selective growth can be performed with the bottom surface of the groove as a growth nucleus, so that the silicon film is filled without forming a cavity in the groove. Furthermore, even if impurities are added to the silicon film by vapor phase diffusion, the impurities do not diffuse to the substrate side because the silicon film is covered with the insulating film.

[0013]

Embodiments of the present invention will be described in detail with reference to the drawings.

A first embodiment of the present invention will be described in the order of forming steps with reference to FIGS.

First, as shown in FIG. 1, an oxide film 2 having a thickness of about 20 nm is formed by thermal oxidation on the main surface of a p-type semiconductor substrate 1 having an acceptor concentration of about 10 ¹⁷ / cm ³ .
After this, the silicon nitride films 3 and 100 having a thickness of about 200 nm are formed.
The oxide film 4 having a thickness of about nm is deposited by the chemical vapor deposition method. After that, these films are patterned by known lithography and dry etching to be left in the element region. Further, in the element isolation region where these films are removed and the semiconductor substrate 1 is exposed, anisotropic etching is further performed to form a groove 5 having a depth of about 0.4 μm.

Next, as shown in FIG. 2, the silicon substrate 1
Then, thermal oxidation is performed to form a thermal oxide film 6 having a thickness of about 50 nm in the groove. The thermal oxide film can be replaced with an insulating film deposited by chemical vapor deposition. However, in order to reduce the recombination current at the interface between the semiconductor substrate 1 and the oxide film 6, it is necessary to perform thermal oxidation of at least several nm in advance. After this, a polycrystalline silicon film 7 having a thickness of about 30 nm is deposited on the entire surface by chemical vapor deposition. There is no problem with the film thickness of the deposited polycrystalline silicon film 7 as long as the upper part of the groove is not blocked.

Next, as shown in FIG. 3, a resist film having a thickness of about 2 μm is applied, and the whole is shaved by oxygen plasma to leave the resist film 8 only inside the groove. At this time, the resist film 8 only needs to remain in the groove, and the thickness of the residual film does not matter. After this, using the resist film 8 as a mask, the polycrystalline silicon film 7 is removed by isotropic dry etching to leave the polycrystalline silicon film 7 on the side wall and the bottom surface of the groove. At this time, the other regions are covered with the oxide films 4 and 6 and the nitride film 3 and are not scraped.

Next, after the resist film 8 is removed by oxygen ashing, the polycrystalline silicon film 7 left in the groove is used as a growth nucleus to selectively grow polycrystalline silicon as shown in FIG. The inside is filled with polycrystalline silicon 9. At this time, the grown polycrystalline silicon 9 may project at the end of the element region. Therefore, in order to remove this, the surface is flattened with the resist film 10. At this time, the thickness of the resist film 10 may be about 1 μm, although it depends on the height of the protruding polycrystalline silicon 9.

Here, the conditions for selective growth of the polycrystalline silicon 9 are, for example, pressure: normal pressure (atmospheric pressure) reaction temperature: about 800 ° C. reaction gas: SiH ₂ Cl ₂ + HCl + H ₂ (flow rate ratio of about 1: 1: 1).

As shown in FIG. 5, the entire surface is etched back by etching without selection ratio (eg, Ar sputtering), and the surface is ground until the oxide film 4 is formed. At this time, the oxide film 4 and the polycrystalline silicon 9 are exposed on the surface. Subsequently, the oxide film 4 is selectively removed by dry etching or an aqueous solution of hydrofluoric acid, and then the surface of the polycrystalline silicon 9 exposed on the surface is selectively etched until the surface of the substrate 1 is about the surface of the substrate 1. As shown in FIG. 6, selective oxidation is performed using the nitride film 3 as a mask to form a field oxide film 11 on the polycrystalline silicon 9. As a result, polycrystalline silicon 9 in the trench is insulated from the surroundings by field oxide film 11 and trench oxide film 6. After that, the nitride film 3 in the element region is removed by dry etching or boiling phosphoric acid, and then a gate insulating film having a thickness of, for example, about 10 nm is formed in the element region according to the conventional method for manufacturing a MOS transistor as shown in FIG. 12
And the gate electrode 13 on the upper part thereof, and the source / drain diffusion layer 14 on both sides thereof by ion implantation and heat treatment.
To form. Furthermore, after forming the interlayer insulating film 15 with phosphorus glass or the like as these electrodes, a connection hole is opened in a desired region, and the wiring electrode 16 is formed with aluminum or the like.

According to this embodiment, the polycrystalline silicon 9 can be filled in the groove without forming a cavity even in the narrow groove.

Next, a second embodiment of the present invention will be described in order of manufacturing steps with reference to FIGS.

First, as shown in FIG. 8, an oxide film 2 having a thickness of about 20 nm is formed on a p-type semiconductor substrate 1 having an acceptor concentration of about 10 ¹⁷ / cm ³ by thermal oxidation. Thereafter, a silicon nitride film 3 having a thickness of about 200 nm is deposited by the chemical vapor deposition method. After that, these films are patterned by known lithography and dry etching to be left in the element region. Further, in the element isolation region where these films are removed and the semiconductor substrate 1 is exposed, anisotropic etching is further performed to form a groove 5 having a depth of about 0.4 μm for element isolation.

Next, as shown in FIG. 9, the semiconductor substrate 1 is subjected to thermal oxidation in the same manner as in the first embodiment, and the groove 5 is filled with 50 nm.
A thermal oxide film 6 of a certain degree is formed in the groove. Then, a polycrystalline silicon film 7 having a thickness of about 30 nm is deposited on the entire surface by chemical vapor deposition.

Next, as shown in FIG. 10, a thick resist film is once applied and flattened, and this resist is partially etched by oxygen plasma to leave the resist 8 only in the groove. At this time, the height of the surface of the resist 8 is controlled so as to remain within the film thickness of the nitride film 3. By using the resist 8 as a mask, the exposed polycrystalline silicon film 7 on the element region is etched to leave the polycrystalline silicon film 7 only in the trench 5 in the element isolation region. At this time, the nitride film 3 serves as an etching stopper layer in the element region.

After that, the resist 8 is removed by oxygen ashing, and as shown in FIG. 11, a sidewall spacer 17 of an oxide film is formed on the sidewall of the groove. The sidewall spacer is formed by 50 nm on the entire surface.
This is achieved by depositing an oxide film of a certain degree and then performing anisotropic dry etching so that the oxide film 17 remains only on the sidewall of the groove. Next, boron is 10 ¹⁴ / cm on the entire surface.
^By implanting about ² ions, the polycrystalline silicon film 7 on the bottom of the groove is made to be p-type silicon having a boron concentration of 10 ¹⁹ / cm ³ or more. Further, since the side wall of the groove is covered with the oxide film 17, the polycrystalline silicon 7 on the side wall of the groove is not ion-implanted. Therefore, if the oxide film 17 on the side wall of the groove is selectively removed with an aqueous solution of hydrofluoric acid or the like, and then the polycrystalline silicon film on which the impurity is not added on the side wall of the groove is removed with a hydrazine solution, nuclei for selective growth are formed only on the bottom of the groove. A boron-doped polycrystalline silicon film can be left. This is about 10
^The p-type region added at ¹⁹ / cm ³ or more has a feature that it cannot be removed by a hydrazine solution. As a result, selective growth is performed as shown in FIG. 12 using the remaining polycrystalline silicon film 7 as a nucleus. Further, since the element region is covered with the nitride film 3, the polycrystalline silicon 9 by selective growth does not grow. As a result, the polycrystalline silicon 9 can be uniformly filled in the groove, so that the etching back of the polycrystalline silicon 9 as shown in the first embodiment (FIG. 5) is unnecessary. Thereafter, as shown in FIG. 13, the polycrystalline silicon 9 in the element isolation region 9 is formed by performing selective oxidation using the nitride film 3 as a mask.
A field oxide film 11 having a thickness of about 200 nm is formed thereon. As a result, the upper surface of the polycrystalline silicon 9 in the element isolation region is covered with the field oxide film 11 and the side surfaces and the bottom surface thereof are covered with the insulating film 6, so that the surroundings can be insulated.
After that, by the method as described in FIG. 7 of the first embodiment, M
Elements such as OS transistors are formed on the main surface of the semiconductor substrate 1.

According to the present invention, the thin-film polycrystalline silicon film 7 that serves as a nucleus for selective growth is left only on the bottom surface of the groove, so that the polycrystalline silicon is uniformly formed in the groove of the element isolation region regardless of the shape of the groove. Because it can be filled inside
The etching back of the polycrystalline silicon 9 described in FIG. 5 of the first embodiment is unnecessary. However, in this embodiment, FIG.
When removing the oxide film 17 on the side wall of the groove formed in
In order to prevent the oxide film 6 inside the groove from being scraped, the upper portion of the thin film polycrystalline silicon film 7 on the sidewall of the groove shown in FIG. 10 needs to be next to the nitride film 3. Figure 1
Since boron is injected in No. 1, it is not removed by the hydrazine solution and becomes a nucleus for selective growth. In the case of the bottom, when the oxide film 17 on the side wall of the groove shown in FIG. 11 is removed, the oxide film 6 in the groove is also partially removed, and the substrate 1 is exposed from the oxide film 6. It causes problems such as becoming.

Next, a third embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 14A, the oxide film 2 and the nitride film 3 are left in the element region of the substrate 1 and the trench 5 is formed in the element isolation region until the trench 5 is formed. This is similar to the second embodiment. Next, as shown in FIG. 14B, the inside of the groove is oxidized by thermal oxidation or the like to form an oxide film 6 having a thickness of about 50 nm, and then a polycrystalline silicon film having a thickness of about 30 nm is deposited 7 and then oxidized. By depositing a film and etching the entire surface, the oxide film 17 is left only on the side wall of the groove. After that, when boron is ion-implanted at about 10 ¹⁴ / cm ² , the element region, which is a region of the polycrystalline silicon film 7 excluding the sidewall of the trench, and the trench bottom surface become p-type. Next, oxide film 1 on the side wall of the groove
7 is removed by a hydrofluoric acid aqueous solution, and as shown in FIG. 14C, the resist 8 is once embedded in the groove and then isotropic etching is performed to remove at least the polycrystalline silicon film 7 in the element region. After that, the polycrystalline silicon film 7 on the side wall of the groove is etched with a hydrazine solution, so that
As shown in FIG. 4D, the polycrystalline silicon film 7 with boron added is left only on the bottom surface of the groove. At this time, the nitride film 3 in the element region and the oxide film 6 in the groove are left as they are without being etched. After that, as shown in FIG. 12 of the second embodiment,
Selective growth is performed using the polycrystalline silicon thin film 7 left only on the bottom surface of the groove as a growth nucleus, and the inside of the groove is filled with polycrystalline silicon 9. In this example, in FIG. 14C, the polycrystalline silicon thin film 7 in the element region was removed and then hydrazine etching was performed. However, after the hydrazine etching was performed to remove the polycrystalline silicon thin film 7 only on the sidewalls of the groove, Even if the polycrystalline silicon thin film 7 in the element region is removed by the same method as described above, the same effect can be obtained.

According to the present embodiment, before removing the polycrystalline silicon film 7 in the element region, an ion implantation mask of the oxide film 17 is formed on the side wall, and boron ion implantation is performed to remove the oxide film 17. At this time, since the entire surface is covered with polycrystalline silicon, it is possible to prevent the oxide film 6 in the groove from being scraped and the substrate 1 being exposed. Furthermore, FIG.
When the polycrystalline silicon film shown in (c) is etched, the height of the groove is not limited as long as it is in the groove, and the process margin is increased.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 15A, as described above, the same steps are performed until the groove 5 is formed in the silicon substrate 1. However, in the present embodiment, the groove 5 is further subjected to isotropic etching so that the groove 5 on the substrate 1 side is formed.
Is made wider than the size of the opening of the nitride film 3. The size of this expansion will be described later. After this
As shown in (b), an oxide film 6 having a thickness of about 50 nm is formed in the groove by thermal oxidation or the like, and further, a thickness of 30 is formed by chemical vapor deposition.
A polycrystalline silicon thin film 7 of about nm is deposited. At this time, the polycrystalline silicon thin film 7 on the side wall inside the groove is at least inside the pattern of the nitride film 3.
Therefore, the lateral etching in the groove in FIG. 15A needs to be performed on one side by about 80 nm or more. However, if the thickness of the oxide film 6 and the thickness of the polycrystalline silicon film 7 in the groove are reduced, the etching amount on the side surface of the groove can be further reduced. Thus, when boron is ion-implanted on the entire surface, the polycrystalline silicon thin film 7 on the side wall of the groove is not ion-implanted because the nitride film 3 forms a shadow. Here, the ion implantation amount of boron is about 10 ¹⁴ / cm ² .

After this, as in the third embodiment, the polycrystalline silicon film 7 is etched using the resist 8 as a mask to leave it in the groove, and then is etched by a hydrazine solution, so that FIG. As shown in FIG. 5, the polycrystalline silicon film 7 that serves as a nucleus for selective growth is left only on the bottom of the groove.

According to the present embodiment, it is not necessary to form a mask for ion implantation on the side wall of the trench with respect to the polycrystalline silicon film 7, and it is possible to simplify the steps for forming and removing a mask material therefor.

The fifth embodiment of the present invention will be described with reference to FIG.

This embodiment is different from the second embodiment in that an oxide film 6 is formed in the groove and then a thin nitride film 18 having a thickness of about 20 nm is deposited on the entire surface by chemical vapor deposition. As a result, the etch back height of the polycrystalline silicon film 6 which is a problem in the second embodiment is not restricted. That is, as shown in FIG. 16, even if the upper portion of the etched-back polycrystalline silicon film is below the surface of the substrate 1, the nitride film 18 serves as a stopper when the oxide film 17 on the sidewall of the groove is removed, and It is possible to prevent the oxide film 6 from being scraped.

According to the present embodiment, even when the polycrystalline silicon film 7 in the element region is etched before the boron ion implantation, if the upper portion of the polycrystalline silicon film 7 is in the groove, the etch back amount is defined. do not do. This provides process latitude. The present embodiment can be applied to the other embodiments described above without any problem.

Next, a sixth embodiment of the present invention will be described with reference to FIG. This embodiment is an example of application to a complementary MOS. Therefore, although the surface of the NMOS region is p-type as described in the above embodiments, PM
The surface of the OS region is n-type. First, as shown in FIG. 17A, an oxide film 6 having a thickness of about 50 nm is formed in the groove as in the above embodiment, and then a nitride film 18 having a thickness of about 20 nm is deposited. After that, the PMOS region is covered with a resist 10 and anisotropic etching is applied to the NMOS region to remove the insulating film on the bottom surface of the groove in the element isolation region of the NMOS region. Therefore, as shown in FIG.
A polycrystalline silicon film 7 having a thickness of about 30 nm is deposited, and then only the side walls of the polycrystalline silicon film 7 are covered with an oxide film 17. Then, ion implantation of boron is carried out. In the NMOS region, the polycrystalline silicon film 7 is in contact with the substrate 1 at the bottom surface of the groove. Therefore, the p layer 19 is formed on the substrate 1 side in that region. After this, as described in the previous embodiments, the polycrystalline silicon film 7 in the element region is removed by dry etching, and the polycrystalline silicon film on the side wall of the groove is removed by a hydrazine solution. As a result, the polycrystalline silicon film 7 to which boron is added remains only on the bottom surface of the groove.

After that, as shown in FIG. 17 (c), the polycrystalline silicon film 7 left previously is selectively grown by using the polycrystalline silicon film 7 as a growth nucleus to fill the trench with polycrystalline silicon 9.
Since the other regions are covered with the nitride film 18 as described in the above embodiments, the polycrystalline silicon 9
Does not grow. After that, the field oxide film is formed in the element isolation region and the MO is formed in the element region by the same method as in the other embodiments.
An S transistor and the like are formed.

According to this embodiment, since the substrate 1 and the polycrystalline silicon 9 in the trench are connected via the p-type layer in the NMOS region, the potential of the polycrystalline silicon 9 can be fixed. However, in the PMOS region, since the surface of the substrate 1 is n-type, a pn junction is formed and the polycrystalline silicon 9 becomes floating. Therefore PM
In the OS region, it is not necessary to bring the bottom surface of the groove into contact with the substrate 1 polycrystalline silicon 9. On the contrary, in the PMOS region, when the p-layer 19 is formed at the bottom of the groove by contacting the polycrystalline silicon 9 in the groove with the substrate 1, the p-type diffusion of the source / drain is required unless the groove is deep enough. It is not preferable to connect the polycrystalline silicon 9 and the substrate 1 which may come into contact with the layer and cause a problem such as poor withstand voltage.

Next, a seventh embodiment of the present invention will be described with reference to FIG.

In this embodiment, as shown in FIG. 18A, the insulating film 6 is formed in the trench of the element isolation region, the polycrystalline silicon film 7 is formed inside the insulating film 6, and the insulating film 17 is formed on the side surface thereof. The process up to the step of forming is almost the same as that of FIG. 11 in the second embodiment. As a difference from the second embodiment, the upper part of the polycrystalline silicon film 7 left inside the trench of the element isolation region is limited to the side surface of the silicon nitride film 3 left in the element region, but this embodiment is different from the second embodiment. In the example, the position may be within the groove. Another difference is that the bottom of the groove is not ion-implanted with boron. In this state, the region that can serve as a nucleus for selective growth is only the polycrystalline silicon film 7 exposed from the groove bottom surface. Therefore, as shown in FIG. 18B, the polycrystalline silicon film 7 exposed from the bottom surface of the groove is used as a nucleus for selective growth, so that the polycrystalline silicon film 9 can be uniformly filled in the groove. After that, as in the other embodiments, selective oxidation is performed using the silicon nitride film 3 as a mask to form a field oxide film on the polycrystalline silicon 9 in the element isolation region.

According to this embodiment, the steps of ion implantation of boron and etching with a hydrazine solution, which have been described in the previous embodiments, can be omitted,
The process can be simplified.

Although the embodiments described above have been discussed with respect to element isolation, they can also be applied to trench filling such as trench capacitors. Further, in the embodiments described above, the polycrystalline silicon filled in the trench of the element isolation region is supposed to finally fix the potential by the wiring electrode or the like. It is assumed that some impurities are added to the polycrystalline silicon embedded in the trench.

[0045]

According to the present invention, polycrystalline silicon can be uniformly filled into the groove without forming a cavity in the groove and even if the substrate is not exposed from the bottom surface of the groove. As a result, high integration of the device can be achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of a forming process according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a forming process according to the first embodiment of the present invention.

FIG. 8 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 9 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 10 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 11 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 12 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 13 is a sectional view of a forming process according to the second embodiment of the present invention.

FIG. 14 is a sectional view of a forming process according to the third embodiment of the present invention.

FIG. 15 is a sectional view of a forming process according to the fourth embodiment of the present invention.

FIG. 16 is a sectional view showing a fifth embodiment of the present invention.

FIG. 17 is a sectional view of a forming process according to the sixth embodiment of the present invention.

FIG. 18 is a sectional view of a forming process according to the seventh embodiment of the present invention.

FIG. 19 is a sectional view of a forming process of a conventional method (etchback method).

FIG. 20 is a sectional view of a forming process of a conventional method (selective growth method).

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Thermal oxide film, 3 ... Silicon nitride film,
4 ... Silicon oxide film, 5 ... Groove, 6 ... Insulating film, 7 ... Thin polycrystalline silicon film, 8 ... Resist, 9 ... Selective growth film, 10
... Resist, 11 ... Field oxide film, 12 ... Gate insulating film, 13 ... Gate electrode, 14 ... Diffusion layer, 15 ... Interlayer insulating film, 16 ... Wiring electrode, 17 ... Silicon oxide film, 18 ...
Thin silicon nitride film, 19 ... P-type layer, 20 ... Thick polycrystalline silicon film, 21 ... Interface, 22 ... Cavity, 23 ... Surface before etch back, 24 ... Surface after etch back.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Yamanaka 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Koji Hashimoto 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Shinpei Iijima 1-280 Higashi Koikeku, Kokubunji City, Tokyo Hitachi Co., Ltd. Central Research Laboratory (72) Inventor Akihiro Shimizu 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo・ SII Engineering Co., Ltd.

Claims (6)

[Claims] 1. A semiconductor device having a groove type element isolation having a surface substantially perpendicular to a main surface of a semiconductor substrate, wherein an insulating film is provided on at least an inner sidewall of a groove of an element isolation region,
Further, a step of providing a thin polycrystalline silicon film only on the inner side thereof,
A semiconductor device comprising at least a step of filling a groove with polycrystalline silicon by selective growth using the thin polycrystalline silicon film as a nucleus, and a step of providing a field insulating film on the polycrystalline silicon. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thin polycrystalline silicon film is formed inside the groove except the element region, and an oxide film is further provided on a side surface thereof.
After ion-implanting boron and then removing the oxide film, the hydrazine solution is used to selectively remove the polycrystalline silicon film on the side wall of the trench which is not ion-implanted with boron.
A method of manufacturing a semiconductor device, characterized in that a thin polycrystalline silicon film, which serves as a nucleus for selective growth, is left only on the bottom surface of a groove. 3. The method for manufacturing a semiconductor device according to claim 1, wherein an insulating film is provided on the inner wall inside the groove formed in the element isolation region, a thin polycrystalline silicon film is deposited, and then an oxide film is formed on the side wall of the groove. After the step of forming the protective film and the ion implantation of boron and then removing the oxide film, the polycrystalline silicon film on the side wall of the groove is selectively removed by a hydrazine solution to form a surface substantially parallel to the main surface of the semiconductor substrate. There is a step of leaving the thin polycrystalline silicon film, and then a step of burying an organic film in the groove of the element isolation region and using the mask as a mask to remove the thin polycrystalline silicon film of the element region, and only on the bottom surface of the groove. A method of manufacturing a semiconductor device, characterized in that a thin polycrystalline silicon film, which is a nucleus of selective growth, is left. 4. The method for manufacturing a semiconductor device according to the above claim, in the case of a complementary semiconductor device, an element isolation region of an n-channel MOS is selectively formed after forming an insulating film in a groove provided in the element isolation region. A step of removing the insulating film on the bottom surface of the groove and a step of depositing a thin polycrystalline silicon film next, and contacting the thin polycrystalline silicon film and the semiconductor substrate on the bottom surface of the groove. Of manufacturing a completed semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film under the thin polycrystalline silicon film is a multilayer film including at least a silicon nitride film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein when a field insulating film is formed on the polycrystalline silicon filled in the groove, the upper surface of the field insulating film is a semiconductor substrate of an adjacent element region. A method of manufacturing a semiconductor device, characterized in that it is arranged so as not to be lower than the main surface of the semiconductor device.