KR0124642B1 - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- KR0124642B1 KR0124642B1 KR1019940011305A KR19940011305A KR0124642B1 KR 0124642 B1 KR0124642 B1 KR 0124642B1 KR 1019940011305 A KR1019940011305 A KR 1019940011305A KR 19940011305 A KR19940011305 A KR 19940011305A KR 0124642 B1 KR0124642 B1 KR 0124642B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- isolation region
- nitride film
- semiconductor layer
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims description 2
- 230000008025 crystallization Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
제1도(a) 내지 (e)는 종래의 반도체 소자의 공정단면도.1 (a) to (e) are process cross-sectional views of a conventional semiconductor device.
제2도(a) 내지 (e)는 본 발명의 반도체 소자의 공정단면도.2 (a) to (e) are process cross-sectional views of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체기판 22 : 제1소자격리영역21 semiconductor substrate 22 first device isolation region
23 : 제1도전형 반도체층 24 : 산화막23: first conductive semiconductor layer 24: oxide film
25 : 질화막 26 : 제2소자격리영역25 nitride film 26 second device isolation region
27 : 질화막측벽 28 : 게이트절연막27: nitride film side wall 28: gate insulating film
29 : 게이트전극 30 : 절연막측벽29 gate electrode 30 insulating film side wall
31 : 소스영역 32 : 드레인영역31: source region 32: drain region
본 발명은 반도체 소자에 관한 것으로, 특히 소자의 격리영역을 최소화하여 고집적화에 적당하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the isolation region of the device is minimized and suitable for high integration.
일반적으로 고집적회로에서는 실리콘 기판면에 형성된 각 소자를 전기적으로 분리해야 한다.In general, in a highly integrated circuit, each element formed on the silicon substrate surface must be electrically separated.
MOS 소자에서도 인접한 소자사이에서 바람직하지 않은 관계가 생기지 않도록 필드산화막을 두껍게 하건, 채널 형성방지용 확산을 하여 실질적인 격리(Isolation)를 하고 있다.In the MOS device, the field oxide film is thickened or diffusion is prevented to form a channel so as to prevent undesirable relationship between adjacent devices.
디바이스의 직접도를 높이기 위해서는 각각의 소자의 디멘션을 축소하는 것도 필요하지만, 동시에 격리영역의 폭, 면적을 축소하는 것이 극히 중요하다. 이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 제조방법을 설명하면 다음과 같다.In order to increase the directness of the device, it is also necessary to reduce the dimensions of each element, but at the same time, it is extremely important to reduce the width and area of the isolation region. Hereinafter, a manufacturing method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
제1도(a) 내지 (e)는 종래의 반도체 소자의 공정 단면도이다. 먼저 제1도(a)에서와 같이 p형 반도체 기판(1)의 전면에 후공정에서의 기판에 대한 스트레스를 줄이기 위한 버퍼산화막(buffer oxide)(2)을 일정한 두께로 형성하고 상기 버퍼 산화막(2)상에 질화막(Nitride)(3)을 증착하고 제1도(b)에서와 같이 필드영역을 정의하여 질화막(3)을 선택적으로 식각한다.1A to 1E are cross-sectional views of a conventional semiconductor device. First, as shown in FIG. 1 (a), a buffer oxide film 2 is formed on the entire surface of the p-type semiconductor substrate 1 to reduce the stress on the substrate in a later process, and the buffer oxide film ( The nitride film 3 is deposited on 2), and the nitride film 3 is selectively etched by defining a field region as shown in FIG.
이어, 제1도(c)에서와 같이 액티브영역(Active area)상에만 남아있는 질화막(3)을 마스크로하여 필드영역에 산화 공정(Oxidation)을 실시하여 소자간의 격리를 위한 필드 산화막(Field Oxide)(4)을 형성한다.Subsequently, as shown in FIG. 1C, an oxide process is performed on the field region using the nitride film 3 remaining only in the active area as a mask, thereby performing field oxidation for isolation between devices. (4).
그리고 제1도(d)에서와 같이 질화막(3)과 초기의 버퍼 산화막(2)을 제거한후, 게이트 산화막(5)을 형성하고 상기의 게이트 산화막(5)상에 폴리실리콘을 증착하고 사진 식각공정으로 채널영역상에만 남도록 선택적으로 제거하여 게이트전극(6)을 형성한다.After removing the nitride film 3 and the initial buffer oxide film 2, as shown in FIG. 1 (d), a gate oxide film 5 is formed, polysilicon is deposited on the gate oxide film 5, and photoetched. In the process, the gate electrode 6 is selectively formed so as to remain only on the channel region.
이어, 제1도의 (e)에서와 같이 상기의 게이트전극(6)을 마스크로 하여 n형의 불순물을 이온 주입하고, 게이트전극(6)의 측면에 산화막측벽(7)을 형성한다. 그리고 상기의 게이트전극(6)과 산화막 측벽(7)을 마스크로하여 고농도의 n형 불순물 이온주입을 실시하는 소스영역()과 드레인영역(9)을 형성한다.Next, as shown in FIG. 1E, n-type impurities are ion-implanted using the gate electrode 6 as a mask, and an oxide film side wall 7 is formed on the side of the gate electrode 6. Then, the gate electrode 6 and the oxide film sidewall 7 are used as a mask to form a source region (D) and a drain region (9) for implanting a high concentration of n-type impurity ions.
그러나 상기와 같은 공정으로 제조된 종래의 반도체 소자는 소자간의 격리를 위한 필드 산화막을 형성하기 위한 선택 산화시에 필드영역의 산화막이 액티브영역으로 확대되어 발생하는 버즈 빅(Birds beak)현상을 줄이기 위하여 필드 산화막의 박막화를 고려해야 한다.However, the conventional semiconductor device manufactured by the above process is to reduce the Birds beak phenomenon caused by the oxide film of the field region is expanded to the active region at the time of selective oxidation to form a field oxide film for isolation between the devices The thinning of the field oxide film should be considered.
그러므로 서브 미크론영역에서의 반도체 소자의 미세화에는 한계가 있다. 또한 소자의 격리를 위한 필드산화막의 기저부에 누설 전류에 의한 필드 반전등의 방지를 목적으로 안티-도핑(Anti-doping)과 같은 공정을 추가로 실시해야 하는 문제점이 있었다.Therefore, there is a limit to the miniaturization of semiconductor devices in the submicron region. In addition, there is a problem in that a process such as anti-doping should be additionally performed at the base of the field oxide film for isolating the device to prevent field inversion due to leakage current.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로써, 소자의 격리영역을 최소화하여 고집적화에 적당하도록 한 반도체 소자의 격리방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a method for isolating a semiconductor device that is suitable for high integration by minimizing the isolation area of the device to solve the above problems.
상기의 목적을 달성하기 위한 본 발명은 반도체 소자의 제조방법을 첨부된 도면을 참고하여 설명하면 다음과 같다.The present invention for achieving the above object will be described with reference to the accompanying drawings, a method for manufacturing a semiconductor device.
제2도(a) 내지 (e)는 본 발명의 반도체 소자의 공정단면도이다. 먼저, 제2도(a)에서와 같이 반도체 기판(21)의 전면에 산화막과 질화막(도면에 도시하지 않음)을 차례로 형성하고 필드영역상의 질화막을 선택적으로 제거하여 상기의 질화막을 마스크로 하여 선택산화공정(Selective Oxidation Process : SOP)을 실시하여 제1소자격리영역(22)을 형성한다.2 (a) to (e) are process cross-sectional views of the semiconductor device of the present invention. First, as shown in FIG. 2A, an oxide film and a nitride film (not shown) are sequentially formed on the entire surface of the semiconductor substrate 21, and the nitride film on the field region is selectively removed to select the nitride film as a mask. A first device isolation region 22 is formed by performing an oxidation process (SOP).
이어, 상기의 산화막과 질화막을 제거한후 제2도(b)에서와 같이 제1소자격리영역(22)이 형성된 반도체기판(21)의 전면에 비정질실리콘(Amorphous-Si)또는 폴리실리콘(Poly-Si)을 일정 두께로 증착하여 제1도전층 반도체층(23)을 형성한다.Subsequently, after removing the oxide film and the nitride film, amorphous silicon (Si) or polysilicon (Poly-) is formed on the entire surface of the semiconductor substrate 21 on which the first device isolation region 22 is formed, as shown in FIG. Si) is deposited to a predetermined thickness to form the first conductive layer semiconductor layer 23.
이어, 상기의 제1도전형 반도체층(23)상에 열산화공정(Thermal Oxidation) 또는 화학 기상증착공정(Chemical Vapor Deposition)으로 산화막(24)을 형성하고 상기의 산화막(24)상에 질화막(25)을 증착한다.Subsequently, an oxide film 24 is formed on the first conductive semiconductor layer 23 by a thermal oxidation process or a chemical vapor deposition process, and a nitride film on the oxide film 24 is formed. 25).
그리고 제2도(c)에서와 같이, 제1소자격리영역(22)을 중심으로 제1소자격리영역(22)보다 작은 폭의 질화막(25)을 제거하고, 제2도(d)에서와 같이 상기의 질화막(25)상에 다시 질화막을 증착하고 에치백 공정을 하여 제2소자격리영역(26)의 넓이가 제1소자격리영역(22)보다 작게 형성되도록 하기 위한 질화막 측벽(27)을 상기의 질화막(25)의 측면에 형성한다.As shown in FIG. 2C, the nitride film 25 having a width smaller than that of the first device isolation region 22 is removed around the first device isolation region 22, and as shown in FIG. A nitride film sidewall 27 for depositing a nitride film on the nitride film 25 and performing an etch back process so that the width of the second device isolation region 26 is smaller than the first device isolation region 22 is formed. It is formed in the side surface of the said nitride film 25.
이어, 상기의 질화막(25)과 질화막 측벽(27)을 마스크로하여 선택산화공정(Selec-tive Oxidation Process : SOP)을 실시하여 제1소자격리영역(22)보다 작은 폭을 갖는 제2소자격리영역(26)을 형성한다.Subsequently, a second device isolation layer having a width smaller than the first device isolation region 22 is performed by performing a selective oxidation process (SOP) using the nitride film 25 and the nitride film sidewall 27 as a mask. Area 26 is formed.
그리고 반도체 기판(21)상에 비정질실리콘 또는 폴리실리콘으로 형성된 제1도전형 반도체층(23)을 소자활성영역으로 이용하기 위하여 반도체기판(21)을 시드(Seed)로 하여 레이져(Laser)를 이용한 단결정화방법으로 제1도전형 반도체층(23)을 단결정화시킨다.In order to use the first conductive semiconductor layer 23 formed of amorphous silicon or polysilicon on the semiconductor substrate 21 as the device active region, the semiconductor substrate 21 is used as a seed and a laser is used. The first conductive semiconductor layer 23 is single crystalized by the single crystallization method.
이어, 제2도(e)에서와 같이 상기의 제1도전형 반도체층(23)상의 질화막(25), 질화막 측벽(27), 산화막(24)을 제거한후 게이트 절연막(28)을 형성하고, 게이트 절연막(28)상에 게이트 전극(29)을 형성한다.Subsequently, the gate insulating film 28 is formed after removing the nitride film 25, the nitride film sidewall 27, and the oxide film 24 on the first conductive semiconductor layer 23, as shown in FIG. The gate electrode 29 is formed on the gate insulating film 28.
그리고 상기의 게이트전극(29)을 마스크로 하여 게이트전극(29) 양측 제1도전형 반도체층(23)에 제2도전형 불순물 이온주입을 실시한후, 게이트전극(29) 측면에 절연막측벽(30)을 형성한다.After the second conductive impurity ion is implanted into the first conductive semiconductor layer 23 on both sides of the gate electrode 29 using the gate electrode 29 as a mask, the insulating film side wall 30 is formed on the side of the gate electrode 29. ).
이어, 상기의 절연막 측벽(30)이 형성된 게이트전극(29)을 마스크로 게이트전극(29) 양측의 제1도전형 반도체층(23)에 고농도의 제2도전형 불순물 이온주입을 하여 LDD 구조의 소스영역(31) 및 드레인영역(32)을 형성한다.Subsequently, a high concentration of second conductive impurity ions are implanted into the first conductive semiconductor layer 23 on both sides of the gate electrode 29 by using the gate electrode 29 having the insulating film sidewall 30 formed thereon as a mask to form an LDD structure. The source region 31 and the drain region 32 are formed.
상기와 같은 본 발명의 반도체 소자 제조방법은 다음과 같은 효과를 갖는다. 제1소자격리영역상에 최소의 넓이로 제2소자격리영역을 형성하는 방법으로 소자의 활성영역을 증가시키고 소자의 격리영역을 감소시켜 소자의 집적도를 향상시키는 효과가 있다.The semiconductor device manufacturing method of the present invention as described above has the following effects. The method of forming the second device isolation region on the first device isolation region with a minimum width can increase the active area of the device and reduce the isolation region of the device, thereby improving the integration degree of the device.
또한, 소스 및 드레인영역을 제1소자격리영역상에 형성하여 누설전류의 발생을 감소시키게 되어 필드반전방지등의 목적으로 실시하는 안티 도핑(Anti-doping)과 같은 이온주입공정을 하지 않게 되는 효과가 있다.In addition, the source and drain regions are formed on the first device isolation region to reduce the occurrence of leakage current, thereby eliminating ion implantation processes such as anti-doping for the purpose of field reversal prevention. There is.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940011305A KR0124642B1 (en) | 1994-05-24 | 1994-05-24 | Manufacture of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940011305A KR0124642B1 (en) | 1994-05-24 | 1994-05-24 | Manufacture of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR950034669A KR950034669A (en) | 1995-12-28 |
| KR0124642B1 true KR0124642B1 (en) | 1997-12-10 |
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| KR1019940011305A KR0124642B1 (en) | 1994-05-24 | 1994-05-24 | Manufacture of semiconductor device |
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| KR100685885B1 (en) * | 2005-10-28 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method for fabricating isolation region of semiconductor device |
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