JP2000164857A - Manufacture for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To clean a surface of a silicon substrate at lower temperatures than usual and enhance characteristic in a silicon layer which has been epitaxially grown, by a method wherein ions are implanted on a main surface of a semiconductor substrate to anneal the semiconductor substrate and a semiconductor thin film is epitaxially grown on the surface. SOLUTION: Nitrogen ions are implanted on a surface of a silicon substrate. At this time, impurity elements, etc., forming a damage layer are kicked out. Annealing is performed in a vacuum at 900 deg.C for about 10 min. At this time, a damage layer existing on the surface of the silicon substrate is removed. An epitaxial silicon layer 36 is grown only on a surface of a source/drain region 9 by a selective epitaxial growth. Arsenic is implanted in the epitaxial silicon layer 36. A titanium thin film is formed on the epitaxial silicon layer 36, a high-temperature heat treatment is made, and the epitaxial silicon layer 36 is reacted with titanium to form a titanium silicide layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device improved so that the temperature of heat treatment can be lowered.

[0002]

2. Description of the Related Art A conventional method for manufacturing a field effect transistor using selective epitaxial growth will be described.

Referring to FIG. 21, an element isolation insulating film 2 is formed on a main surface of a silicon substrate 1 by a trench isolation method. By forming the element isolation insulating film 2, a plurality of active regions for forming MOS transistors and the like are formed on the surface of the silicon substrate 1.

Referring to FIG. 22, a gate insulating film 3 is formed on a silicon substrate 1 by a thermal oxidation method. next,
A polysilicon film 4 and a silicon oxide film 5 are deposited, and these are subjected to anisotropic etching using a photoresist having a predetermined shape as a mask to form a gate electrode portion 6.

Referring to FIG. 23, n ^- source / drain regions 7 are formed on the surface of silicon substrate 1 by ion implantation. A side wall spacer 8 is formed on a side wall of the gate electrode portion 6. Next, n ⁺ source / drain regions 9 are formed by ion implantation. Thereby, the source electrode portion 10 and the drain electrode portion 1
1 is formed.

Referring to FIG. 24, an epitaxial silicon layer 12 is formed only on source electrode portion 10 and drain electrode portion 11 by a chemical vapor deposition method or the like. In the epitaxial silicon layer 12, by ion implantation,
Impurities are introduced.

Referring to FIG. 25, a metal thin film 13 such as titanium is formed on silicon substrate 1 by sputtering. A high-temperature heat treatment is performed to react the epitaxial silicon layer 12 and the metal thin film 13 to form a silicide layer 14. The unreacted metal thin film 13 is
For example, it is removed by a mixed solution of sulfuric acid and hydrogen peroxide. Since the epitaxial silicon layer 12 is not formed on the side wall spacer 8, the silicide layer 14 is not formed on the side wall spacer 8. Therefore, the gate electrode portion 6 and the source electrode portion 10
The drain electrode portion 11 is electrically insulated from each other.

Referring to FIG. 26, an interlayer insulating film 15 is formed on a silicon substrate 1 by a chemical vapor deposition method or the like. A contact hole 16 for exposing a part of the surface of the silicide layer 14 is formed in the interlayer insulating film 15.

Referring to FIG. 27, contact hole 16
A tungsten plug 25 is embedded therein. Next, aluminum wiring 26 connected to tungsten plug 25
Forming the gate electrode 6 and the source electrode 18
And a field effect transistor having a drain electrode 19. Although not shown, an interlayer insulating film is further formed,
A semiconductor device is completed by forming a metal wiring or the like thereon.

[0010]

The conventional method for manufacturing a field-effect transistor using the above-mentioned selective epitaxial growth has the following problems.

The conventional method for manufacturing a field effect transistor
In this case, as shown in FIG. ⁺Source / drain
The epitaxial silicon layer 12 is formed only on the region 9.
There is a step to perform. At this time, the normal semiconductor manufacturing process
Through the surface, the surface of the silicon substrate 1
Attachment of impurity elements and contamination with silicon as shown in 28
Reaction with an impurity element or silicon crystal near the surface
A so-called damage layer 21 composed of disorder or the like is formed.
You. This damaged layer 21 is an epitaxial silicon layer
Is known to inhibit the growth of and degrade its properties
I have. Therefore, epitaxial growth is promoted and
In order to improve the characteristics of the epitaxial silicon layer,
Immediately before the epitaxial growth, the surface of the silicon substrate 1
A cleaning step for removing the damaged layer 21 is required.
Was.

For example, there is known a method of cleaning the surface of a silicon substrate 1 by a flushing process (annealing for cleaning) for heating a silicon wafer in a chamber maintained at a high vacuum, as shown in FIG. Have been. In this method, the surface of the silicon substrate 1 can be further cleaned by increasing the heating temperature of the silicon substrate 1 or increasing the heating time of the silicon substrate 1. However, when this method is used for a field-effect transistor using a shallow junction, impurities implanted in the source / drain of the field-effect transistor thermally diffuse during flashing, and a shallow junction is formed. There was a problem that it became impossible.

Further, as shown in FIG. 30, for example, the surface of the silicon substrate 1 is isotropically etched by plasma etching using a fluorine-based gas. Methods for cleaning are known. In this method, the surface of the silicon substrate 1 can be further cleaned by etching the surface of the silicon substrate 1 deeper.

However, when this method is used for a field-effect transistor using a shallow junction, the source / drain region of the field-effect transistor is cut off, and characteristics such as an increase in the internal resistance of the transistor are obtained. There is a problem that deterioration occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made to clean the surface of a silicon substrate at a lower temperature than in the case where normal flashing is performed. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is improved so that the characteristics of the semiconductor device can be improved.

[0016]

In the method of manufacturing a semiconductor device according to the first aspect, first, a semiconductor substrate is prepared.
Ions are implanted into the main surface of the semiconductor substrate. The semiconductor substrate is annealed. A semiconductor thin film is epitaxially grown on the surface of the semiconductor substrate.

According to the present invention, no etching using plasma is performed between the ion implantation step and the step of growing the semiconductor thin film. According to this method, the damaged layer on the surface of the semiconductor substrate is removed by ion implantation, the growth of the semiconductor thin film is promoted, and a semiconductor thin film having good film quality is formed. As a result, a semiconductor device having excellent electrical reliability can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, the annealing is performed at 1100 ° C. or less in a vacuum or an inert gas atmosphere.

According to a third aspect of the present invention, the annealing is performed at 850 ° C. or lower.

According to the present invention, the damaged layer is removed by annealing at 850 ° C. or less, instead of the conventional flashing at 900 ° C. Therefore, when this method is used for a field-effect transistor using a shallow junction, impurities implanted in the source / drain of the field-effect transistor do not thermally diffuse. As a result, a shallow junction can be formed.

According to this method, the damaged layer on the surface of the semiconductor substrate is removed by ion implantation, the growth of the semiconductor thin film is promoted, and a semiconductor thin film having good film quality is formed. Furthermore, the surface can be further cleaned by combining the annealing step. As a result, a semiconductor device having excellent electrical reliability can be obtained.

In particular, the effect of the present invention is remarkable when the semiconductor thin film growth step is performed by solid phase epitaxial growth or vapor phase selective epitaxial growth.

According to this method, solid phase epitaxial growth or vapor phase selective epitaxial growth is used as a semiconductor thin film growth step. In the epitaxial growth, when the growth of the semiconductor thin film is started, the influence of the interface between the semiconductor substrate and the film to be epitaxially grown is particularly strong.
Therefore, in order to promote the growth of the semiconductor thin film and to form a semiconductor thin film having good film quality, it is important to clean the substrate. Conventionally, the substrate has been highly purified by increasing the flushing temperature of the substrate, increasing the flushing time, or increasing the time for performing the chemical dry etching process.

According to the present invention, when cleaning a substrate,
It is not necessary to perform the flushing process, and even when the flushing process is performed, the flushing process can be performed without extending the time of the flushing process or without increasing the temperature of the flushing process.

Further, according to the present invention, the substrate can be cleaned without performing the chemical dry etch process or without increasing the time for performing the chemical dry etch process.

As described above, a favorable epitaxial film can be obtained in a field-effect transistor or the like using a shallow junction, as described in the section of the problem to be solved by the present invention.

According to a fourth aspect of the present invention, the epitaxial growth is performed by selective epitaxial growth.

In the method of manufacturing a semiconductor device according to a fifth aspect, the step of annealing the semiconductor substrate and the step of forming the semiconductor thin film are performed at a degree of vacuum of 1 × 10 ^-10 to
A vacuum chamber at 1 × 10 ⁻¹ Torr, substrate holding means for holding a substrate in the center of the vacuum chamber, heating means for applying radiant heat to one surface of the substrate, and reactive gas on the other surface of the substrate And a reaction gas supply means for supplying the gas. The semiconductor substrate is held by the substrate holding means. The semiconductor substrate is annealed by the heating means. The reaction gas is supplied from the reaction gas supply means to the other surface of the semiconductor substrate to epitaxially grow a semiconductor thin film.

The above-described manufacturing apparatus is an apparatus capable of depositing a good semiconductor thin film, and a combination with a cleaning step by ion implantation can obtain a film having better film characteristics.

In the method of manufacturing a semiconductor device according to the sixth aspect, the ion implantation is performed by implanting ions containing a Group 3 element such as boron, aluminum, potassium, and indium.

According to the present invention, the p-type region can be provided on the surface of the semiconductor substrate at the same time as the removal of the damaged layer, and the manufacturing cost of the semiconductor device can be reduced by reducing the number of steps.

In the method of manufacturing a semiconductor device according to claim 7, the ion implantation is performed by implanting ions containing a Group 4 element such as carbon, silicon or germanium.

According to the present invention, for example, n-type and p-type are formed on the same semiconductor substrate, such as a CMOS device.
In the case where a semiconductor region of a type is provided, by using a Group 4 element, the surface of the n-type region or the p-type region can be cleaned by ion implantation without masking with a resist or the like. The state of doping is not changed. Thus, the number of steps can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, the ion implantation is performed by implanting ions containing a group V element such as nitrogen, phosphorus, arsenic, and antimony.

According to the present invention, an n-type region can be provided on the surface of the semiconductor substrate at the same time when the damaged layer is removed, so that the number of steps can be reduced and the manufacturing cost of the semiconductor device can be reduced.

In the method of manufacturing a semiconductor device according to the ninth aspect, the ion implantation is performed by implanting ions containing a Group 7 element such as fluorine, chlorine, bromine, and iodine.

It is known that the group 7 element has an effect of etching silicon. According to the present invention, the silicon surface is etched by injecting such a gas into the silicon surface very shallowly. Thereby, it can be cleaned.

In the method of manufacturing a semiconductor device according to the tenth aspect, the ion implantation is performed by implanting a Group VIII element such as helium, neon, argon, and krypton.

According to the present invention, for example, an n-type and a p-type are formed on the same semiconductor substrate such as a CMOS device.
In the case where a semiconductor region of a type is provided, the use of a Group VIII element allows doping of the surface even if cleaning is performed by ion implantation without masking the n-type region or the p-type region with a resist or the like. Is not changed. This makes it possible to reduce the number of processes,
The manufacturing cost of the semiconductor device can be reduced.

In the method of manufacturing a semiconductor device according to claim 11, after forming a semiconductor thin film on the surface of the semiconductor substrate, the surface of the semiconductor substrate including the semiconductor thin film is
An element isolation region is formed.

According to the present invention, the surface can be cleaned at a lower temperature before the epitaxial growth is performed on the silicon surface. For this reason, since the epitaxial growth apparatus can be designed for a lower temperature process, the apparatus can be manufactured at low cost.

In a method of manufacturing a semiconductor device according to a twelfth aspect, first, a semiconductor substrate is prepared. An element isolation region for isolating an element region from another element region is formed in the main surface of the semiconductor substrate. Ions are implanted into the main surface of the semiconductor substrate. The semiconductor substrate is annealed. A semiconductor thin film is epitaxially grown on the element region.

According to the present invention, an etching step using plasma is not included between the ion implantation step and the step of growing a semiconductor thin film.

According to the present invention, a shallow and steep doping profile can be formed by forming a good semiconductor thin film in an element formation region. This makes it possible to form a higher performance semiconductor device.

In a method of manufacturing a semiconductor device according to a thirteenth aspect, first, a semiconductor substrate is prepared. An element isolation region for isolating an element region from another element region is formed in the main surface of the semiconductor substrate. A gate electrode is formed in the element region. Ions are implanted into the main surface of the semiconductor substrate.
The semiconductor substrate is annealed. Source / drain regions are formed in the main surface of the semiconductor substrate on both sides of the gate electrode. A semiconductor thin film is epitaxially grown on the source / drain regions.

According to the present invention, the step of etching using plasma is not included between the ion implantation step and the step of growing the semiconductor thin film.

According to the present invention, the thermal budget can be reduced when forming a transistor in the form of an elevated source / drain region. As a result, the source / drain region can be raised for a field effect transistor having a shallow junction, and a more accurate semiconductor device can be formed.

In a method of manufacturing a semiconductor device according to a fourteenth aspect, first, a semiconductor substrate is prepared. An element isolation region for isolating an element region from another element region is formed in the main surface of the semiconductor substrate. A gate electrode is formed on the semiconductor substrate. A low-concentration portion of a source / drain region having an LDD structure is formed in the element region and on both sides of the gate electrode. Sidewall spacers are formed on both sides of the gate electrode. On both sides of the gate electrode, a high concentration portion of the source / drain region having the LDD structure is formed. An interlayer insulating film is formed on the surface of the semiconductor substrate so as to cover the gate electrode. A contact hole for exposing a part of the surface of the source / drain region is formed in the interlayer insulating film. Ions are implanted into the bottom of the contact hole. The semiconductor substrate is annealed. A semiconductor thin film is epitaxially extended on the bottom of the contact hole.

According to the present invention, a good semiconductor thin film can be formed in a contact hole, a contact resistance can be reduced, and a semiconductor element which can operate at higher speed can be formed.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 First, the same processing as the conventional process shown in FIGS. 21 to 23 is performed.

The silicon substrate 1 thus formed
Referring to FIG. 1, there is a damaged layer 21 formed by etching or the like for forming a sidewall.

Referring to FIG. 2, nitrogen ions are implanted into the surface of silicon substrate 1. At this time, the injection energy is
2 to 500 KeV. At this time, impurity elements and the like forming the damaged layer 21 are knocked out. Next, at 900 ° C. (preferably at 850 ° C. or less) in a vacuum, 10
Anneal for about a minute. At this time, the damaged layer 21 existing on the surface of the silicon substrate 1 is removed.

Referring to FIG. 3, epitaxial silicon layer 36 is grown only on the surface of source / drain region 9 by selective epitaxial growth. Next, arsenic is implanted into the epitaxial silicon layer 36.

Thereafter, through a process similar to the conventional process shown in FIG. 25, a titanium thin film is formed on the epitaxial silicon layer 36 by sputtering or the like, and a high-temperature heat treatment is performed. And titanium react to form a titanium silicide layer. Unreacted titanium is removed by a mixed solution of sulfuric acid and hydrogen peroxide.

Further, as shown in FIG. 26, the interlayer insulating film 15 is formed on the silicon substrate 1 by a chemical vapor deposition method or the like.
On top of. After that, a contact hole 16 is formed in the interlayer insulating film 15. Hereinafter, after the flow of forming a normal tungsten plug, aluminum for the wiring is formed. By etching this, a MOS having a gate electrode 6, a source electrode 18, and a drain electrode 19 is formed.
A type transistor is formed. Further, although not shown,
When a metal wiring or the like is formed with an interlayer insulating film interposed, a semiconductor device is completed.

In the method of manufacturing the semiconductor device according to the first embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be performed at a lower temperature than usual. For this reason, a MOS transistor using a shallow junction can be formed. In addition, a thicker silicide layer can be formed on the source / drain regions by applying a salicide process to a transistor using a shallow junction, and the internal resistance of a MOS transistor can be reduced. As a result, the operation speed of the MOS transistor can be improved.

Embodiment 2 Embodiment 2 differs from Embodiment 1 in that arsenic ions are used as ions to be implanted. Since the steps are the same as those of the first embodiment, the second embodiment will be described with reference to FIGS.

Referring to FIG. 1, a damage layer 21 formed by etching or the like for forming sidewall 8 exists on the surface of silicon substrate 1.

Referring to FIG. 2, arsenic ions are implanted into the surface of silicon substrate 1. At this time, the injection energy is
It is about 2 to 500 KeV. Next, 900 ° C in vacuum
(Preferably 850 ° C. or lower) is performed for about 10 minutes. Thereby, the damaged layer 21 on the surface of the silicon substrate 1 is removed.

Referring to FIG. 3, an epitaxial silicon layer 36 is grown only on the surface of source / drain region 9 by selective epitaxial growth. Hereinafter, a semiconductor device is completed through a process similar to that described in the first embodiment.

In the method of manufacturing a semiconductor device according to the second embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be performed at a lower temperature than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain region 9 by applying a salicide process to a transistor using a shallow junction. As a result, the internal resistance of the MOS transistor can be reduced, and the operating speed of the MOS transistor can be improved.

Further, by using arsenic, which is a p-type impurity, as the ion species used in the ion implantation for removing the damaged layer, the removal of the damaged layer and the introduction of the impurity can be performed simultaneously. This effect can be obtained even when an ionic species containing phosphorus or the like, which is also a p-type impurity, is used.

Embodiment 3 In Embodiment 3, BF _{2 is used} as an ion species for ion implantation.
Is different from the first embodiment in that Since the processing steps are the same as those of the first embodiment, a method of manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS.

Referring to FIG. 1, on the surface of silicon substrate 1, there is a damaged layer 21 generated by etching for forming a sidewall.

Referring to FIG. 2, BF ₂ ions are implanted into the surface of silicon substrate 1. At this time, the implantation energy is about 2 to 500 KeV. Next, in a vacuum at 90
Anneal at 0 ° C. (preferably 850 ° C. or less) for about 10 minutes. At this time, the damaged layer 21 on the surface of the silicon substrate 1 is removed.

Next, referring to FIG. 3, only the surface of source / drain region 9 is selectively grown by epitaxial growth.
An epitaxial silicon layer 36 is grown. Hereinafter, a semiconductor device is completed through a process similar to that described in the first embodiment.

In the method of manufacturing a semiconductor device according to the third embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be performed at a lower temperature than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain regions by applying a salicide process to a transistor using a shallow junction, thereby lowering the internal resistance of a MOS transistor. it can. As a result, the operation speed of the MOS transistor can be improved.

Further, by using an ion species containing boron, which is an n-type impurity, as the ion species used for ion implantation for removing the damaged layer, the removal of the damaged layer and the introduction of the impurity can be performed simultaneously. This effect can be obtained even when an ionic species containing aluminum or the like, which is also an n-type impurity, is used.

Embodiment 4 In Embodiment 4, silicon ions are used as ion species for ion implantation. The manufacturing process is the same as in FIGS. 1 to 3 described in the first embodiment.

Referring to FIG. 1, on the surface of silicon substrate 1, there is a damaged layer 21 formed by etching or the like for forming a sidewall.

Referring to FIG. 2, silicon ions are implanted into the surface of silicon substrate 1. The injection energy is 2-5
00 KeV. Next, annealing is performed in a vacuum at 900 ° C. (preferably 850 ° C. or less) for about 10 minutes. Thereby, the damaged layer 21 on the surface of the silicon substrate 1 is removed.

Referring to FIG. 3, an epitaxial silicon layer 36 is grown only on the surfaces of the source / drain regions by selective epitaxial growth. Hereinafter, a semiconductor device is completed through a process similar to that described in the first embodiment.

In the method of manufacturing a semiconductor device according to the fourth embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be performed at a lower temperature than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain regions 9 by applying a salicide process to a transistor using a shallow junction, thereby lowering the internal resistance of the MOS transistor. Thereby, the operation speed of the MOS transistor can be improved.

Further, by using silicon as an ion species used in ion implantation for removing a damaged layer,
The ion implantation energy can be freely selected without changing the distribution of impurity elements in the transistor. A similar effect can be obtained by implanting ion species containing carbon or germanium.

Embodiment 5 In Embodiment 5, helium ions are used as the ion species to be implanted. The manufacturing process is the same as FIGS. 1 to 3 described in the first embodiment.

Referring to FIG. 1, on the surface of silicon substrate 1, there is a damaged layer 21 formed by etching when forming a sidewall.

Referring to FIG. 2, helium ions are implanted into the surface of silicon substrate 1. At this time, the implantation energy is about 2 to 500 KeV. Next, in a vacuum at 90
Anneal at 0 ° C. (preferably 850 ° C. or less) for about 10 minutes. At this time, the damaged layer 21 on the surface of the silicon substrate 1 is removed.

Referring to FIG. 3, epitaxial silicon layer 36 is grown only on the surface of source / drain region 9 by selective epitaxial growth. Hereinafter, a semiconductor device is completed through a process similar to that described in the first embodiment.

In the method of manufacturing a semiconductor device according to the fifth embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be made lower than usual.
Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain regions by applying a salicide process to a transistor using a shallow junction, thereby lowering the internal resistance of the MOS transistor. In addition, the operation speed of the MOS transistor can be improved.

Further, by using helium ions as the ion species used in the ion implantation for removing the damaged layer, the ion implantation energy can be freely selected without changing the distribution of impurity elements in the transistor. . Similar effects can be obtained by implanting other rare gas ions such as argon or neon.

Embodiment 6 In Embodiment 6, fluorine ions are used as ion species.

The manufacturing process is the same as in FIGS. 1 to 3 described in the first embodiment. Referring to FIG. 1, a damage layer 21 formed by etching a sidewall or the like is present on the surface of silicon substrate 1.

Referring to FIG. 2, fluorine ions are implanted into the surface of silicon substrate 1. At this time, the implantation energy is about 2 to 500 KeV. Next, in a vacuum at 90
Anneal at 0 ° C. for about 10 minutes. At this time, the damaged layer 21 on the surface of the silicon substrate 1 is removed.

Next, referring to FIG. 3, an epitaxial silicon layer 36 is grown only on the surface of the source / drain regions by selective epitaxial growth. Hereinafter, a semiconductor device is completed through a process similar to that described in the first embodiment.

In the method of manufacturing a semiconductor device according to the sixth embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be made lower than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain regions by applying a salicide process to a transistor using a shallow junction, thereby lowering the internal resistance of the MOS transistor. In addition, the operation speed of the MOS transistor can be improved.

Further, by using fluorine ions as ion species used in ion implantation for removing a damaged layer, the damaged layer can be more effectively removed by an etching effect of fluorine on a silicon substrate. The same effect can be obtained by other ionic species including fluorine, such as BF ₂ and CF ₄ , or ionic species including chlorine, bromine, iodine and the like.

Seventh Embodiment A method for manufacturing a semiconductor device according to a seventh embodiment will be described with reference to FIGS.

Referring to FIG. 4, on the surface of silicon substrate 1, damaged layer 2 caused by surface polishing, natural oxide film, or the like is formed.
1 is formed. BF ₂ for silicon substrate 1
Is ion-implanted. The ion implantation amount is 1 × 10 ¹³ / cm ²
To about 1 × 10 ¹⁸ / cm ² . Further, the implantation energy is set to about 1 KeV to 1 MeV. Thereafter, annealing is performed at about 700 to 1100 ° C. in a vacuum or an inert gas. Then, referring to FIG. 5, damaged layer 21 is removed.

Referring to FIG. 6, an epitaxial silicon layer 36 is deposited on the surface of silicon substrate 1.

Then, referring to FIG. 7, silicon substrate 1
Is formed on the surface of the device.

According to the method of manufacturing a semiconductor device according to the seventh embodiment, by growing epitaxial silicon layer 36 directly on silicon substrate 1, it is possible to improve the quality of silicon crystal in a region where an element is formed, Consequently, the performance of the semiconductor device formed thereon can be improved.

Further, by introducing impurities into the silicon substrate 1 in advance, or by depositing while introducing the impurities simultaneously with the formation of the epitaxial silicon layer 36, the profile of the impurities can be formed steeply. . Further, in the method of manufacturing a semiconductor device described above, the crystallinity of the epitaxial silicon layer 36 can be further improved, and the thermal history of the silicon substrate 1 can be reduced. This makes it possible to form a steeper impurity profile and improve the performance of the transistor.

Eighth Embodiment FIGS. 8 to 10 are sectional views of a semiconductor device showing a method of manufacturing a semiconductor device according to an eighth embodiment.

Referring to FIG. 8, an element isolation region 22 is formed on the surface of silicon substrate 1. At this time, in the vicinity of the surface of the element formation region where the element isolation region 22 is not formed,
There is a damaged layer 21 caused by the etching process. Next, nitrogen ions are implanted into the surface of the element formation region, and then annealing is performed at about 700 to 1100 ° C. in a vacuum. At this time, referring to FIG. 9, the damaged layer near the surface of the element formation region is removed.

Next, referring to FIG. 10, an epitaxial silicon layer 36 is deposited. Thereafter, through the same steps as in the prior art, the surface of the epitaxial silicon
An OS transistor is formed.

According to the method of manufacturing the semiconductor device according to the eighth embodiment, the quality of silicon crystal in the element isolation region can be improved by growing epitaxial silicon layer 36 in the element formation region of silicon substrate 1. Thus, the performance of the semiconductor device formed thereon can be improved.

Further, it is possible to eliminate the influence of the fall of the edge portion of the element isolation oxide film 2. Further, in the method for manufacturing a semiconductor device according to the present embodiment, the crystallinity of the selective epitaxial silicon layer 36 can be further improved, and the thermal history of the silicon substrate 1 can be reduced. As a result, a more reliable transistor can be formed.

Ninth Embodiment First, conventional steps shown in FIGS. 21 to 22 are performed.

Referring to FIG. 11, gate oxide films located on both sides of gate electrode 6 are removed by plasma etching or the like. At this time, a damage layer 21 is formed on the surface of the silicon substrate 1. Next, arsenic ion implantation is performed.
The implantation energy is about 1 to 100 KeV. Next, annealing at about 700 to 1100 ° C. is performed in a vacuum.

Thus, referring to FIG. 12, the damaged layer on the surface of silicon substrate 1 is removed. Next, in the main surface of the silicon substrate, on both sides of the gate electrode 6,
A source / drain low concentration portion 7 is formed. Then
Referring to FIG. 13, selective epitaxial growth of silicon is performed on the surface of silicon substrate 1 to form epitaxial silicon layer 36.

Referring to FIG. 14, a sidewall spacer 8 is formed on the side wall of gate electrode 6, a high-concentration portion 9 of the source / drain region is formed, and then a transistor is completed through a conventional process. .

In the method of manufacturing a semiconductor device according to the ninth embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be made lower than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. This makes it possible to form a thicker silicide layer on the source / drain regions by applying a salicide process to a transistor using a shallow junction, thereby lowering the internal resistance of a MOS transistor. The operation speed of the MOS transistor can be improved.

Embodiment 10 First, the conventional steps shown in FIGS. 21 to 23 are performed.

Referring to FIGS. 15 and 16, an interlayer insulating film 15 is formed on silicon substrate 1 by a chemical vapor deposition method or the like. A contact hole 16 for exposing a part of the surface of the source / drain region in interlayer insulating film 15
To form At this time, a damage layer 21 due to the etching is formed on the bottom surface of the contact hole 16.

Referring to FIG. 17, contact hole 16 is formed.
Arsenic ions are implanted into the inside of the substrate. Further, annealing is performed in a nitrogen atmosphere. At this time, the damaged layer on the surface of the silicon substrate 1 is removed.

Referring to FIG. 18, contact hole 16
Is selectively epitaxially grown on the bottom surface of the substrate to grow an epitaxial silicon layer. Next, by forming a tungsten plug 25 and an aluminum wiring 26, a field effect transistor including the gate electrode 6, the source electrode 18, and the drain electrode 19 is formed. Further, although not shown, an interlayer insulating film is formed, and a metal wiring or the like is formed with the interlayer insulating film interposed, whereby a semiconductor device is completed.

In the method of manufacturing a semiconductor device according to the tenth embodiment, the temperature of the heat treatment performed before the selective epitaxial growth can be made lower than usual. Therefore, selective epitaxial growth can be applied to a MOS transistor using a shallow junction. Thus, the contact resistance can be reduced, and the operating speed of the MOS transistor can be improved by lowering the internal resistance of the MOS transistor.

Eleventh Embodiment FIG. 19 is a conceptual diagram of a manufacturing apparatus used in a semiconductor manufacturing method according to an eleventh embodiment. Referring to FIG. 19, the thin film manufacturing apparatus sets the degree of vacuum to 1 × 10 ^-10 to 1 × 10 ^-1 Torr.
A film forming chamber 29, a substrate susceptor 31 for holding a silicon substrate 30 substantially at the center of the film forming chamber 29, a substrate heater 32 for applying radiant heat to one surface of the held substrate 30,
A gas inlet 33 for supplying a reaction gas for the substrate; When a method of manufacturing a semiconductor device as described in Embodiment Modes 1 to 10 above is realized on a cleaned surface of a semiconductor substrate using this thin film manufacturing apparatus, cleaning by annealing is more effective. Therefore, the temperature of the heat treatment can be further reduced.

This thin film manufacturing apparatus can be incorporated as shown in FIG. A film forming chamber 29 for manufacturing a thin film
Separately, an annealing chamber 34 for performing annealing is constituted by different vacuum chambers, and these are connected by a vacuum transfer device 35 which can transfer the vacuum chamber therebetween. Further, a load lock 37 for carrying in and a load lock 38 for carrying out are connected to the vacuum transfer device 35. With such an apparatus, a semiconductor device can be manufactured with high throughput.

[0111]

According to the method of manufacturing a semiconductor device according to the present invention, a damaged layer on the surface of a semiconductor substrate is removed by ion implantation, the growth of a semiconductor thin film is promoted, and a semiconductor having good film quality is obtained. A thin film is formed. as a result,
A semiconductor device with excellent electrical reliability can be obtained.

According to the method of manufacturing a semiconductor device according to claims 2 and 3, the damaged layer is removed by annealing at a low temperature. Therefore, when this method is used for a field-effect transistor using a shallow junction, impurities implanted in the source / drain of the field-effect transistor do not thermally diffuse. As a result, a shallow junction can be formed.

According to the method of manufacturing a semiconductor device according to the fourth aspect, a semiconductor thin film having good film quality can be selectively epitaxially grown.

According to the method of manufacturing a semiconductor device according to the fifth aspect, a device having better film characteristics can be obtained.

According to the method of manufacturing a semiconductor device according to the sixth aspect, a p-type region can be provided on the surface of the semiconductor substrate at the same time as the damaged layer is removed. Manufacturing costs can be reduced.

According to the semiconductor device manufacturing method of the present invention, the n-type region or the p-type region is cleaned by ion implantation without masking with a resist or the like. There is no change in appearance. As a result, the number of steps can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

According to the method of manufacturing a semiconductor device according to the eighth aspect, the n-type region can be provided on the surface of the semiconductor substrate at the same time as the removal of the damaged layer, and the number of steps can be reduced. Cost can be reduced.

According to the method of manufacturing a semiconductor device according to the ninth aspect, the surface of the substrate can be cleaned by lightly etching the silicon surface.

According to the method of manufacturing a semiconductor device of the tenth aspect, even if the n-type region or the p-type region is cleaned by ion implantation without masking with a resist or the like, the doping of the surface can be prevented. There is no change in appearance. As a result, the number of steps can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

According to the method of manufacturing a semiconductor device according to the eleventh aspect, the surface can be cleaned at a lower temperature before epitaxial growth is performed on the silicon surface. For this reason, since the epitaxial growth apparatus can be designed for a lower temperature process, the apparatus can be manufactured at low cost.

According to the method of manufacturing a semiconductor device of the twelfth aspect, a shallow and steep doping profile can be formed by forming a good semiconductor thin film in the element formation region. This makes it possible to form a higher performance semiconductor device.

According to the method of manufacturing a semiconductor device according to the thirteenth aspect, the source / drain regions can be raised for a field effect transistor having a shallow junction, and a more accurate semiconductor device can be formed. Become.

According to the method of manufacturing a semiconductor device according to the fourteenth aspect, a good semiconductor thin film can be formed in the contact hole, the contact resistance can be reduced, and the semiconductor can be operated at higher speed. An element can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor device in a third step in the sequence of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention.

FIG. 5 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device in a third step in the sequence of a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor device in a fourth step in the sequence of the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device in a second step in the sequence of the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a semiconductor device in a third step in the sequence of the method for manufacturing the semiconductor device according to the eighth embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention;

FIG. 12 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method for manufacturing the semiconductor device according to the ninth embodiment of the present invention.

FIG. 13 is a cross-sectional view of the semiconductor device in a third step in the order of the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention.

FIG. 14 is a cross-sectional view of the semiconductor device in a fourth step in the sequence of the method for manufacturing the semiconductor device according to the ninth embodiment of the present invention.

FIG. 15 is a cross-sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 16 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method for manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 17 is a sectional view of the semiconductor device in a third step in the sequence of the method for manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 18 is a sectional view of the semiconductor device in a fourth step in the sequence of the method for manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 19 is a conceptual diagram of a manufacturing apparatus used for a semiconductor manufacturing method according to an eleventh embodiment of the present invention.

FIG. 20 is a plan view showing an overall configuration of a manufacturing apparatus used in a semiconductor manufacturing method according to an eleventh embodiment of the present invention.

FIG. 21 shows a first example of a sequence of a conventional method of manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 22 shows a second example of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 23 shows a third example of the order of the conventional semiconductor device manufacturing method;
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 24 is a fourth view of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 25 shows a fifth example of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 26 is a sixth view illustrating the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 27 is a seventh view of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 28 is a cross-sectional view of a semiconductor device showing a problem of a conventional method of manufacturing a semiconductor device.

FIG. 29 is a cross-sectional view of a semiconductor device showing a method for solving a problem of a conventional method of manufacturing a semiconductor device.

FIG. 30 is a cross-sectional view of a semiconductor device showing another example for solving the problem of the conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 1. Silicon substrate, 36 semiconductor thin film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigemitsu Maruno 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Satoshi Yamakawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo 3 Within Rishi Electric Co., Ltd. (72) Inventor Yasutaka Nishioka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanbishi Electric Co., Ltd. (72) Inventor Yuki Tokuda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric F term (reference) 4M104 BB01 BB18 BB25 CC01 DD22 DD37 FF21 FF22 HH20 5F040 DA10 DA13 DC01 EC07 EF02 EH02 EH08 EK01 FA03 FB02 FC06 FC15 FC19

Claims (14)

[Claims] A step of preparing a semiconductor substrate; a step of implanting ions into a main surface of the semiconductor substrate; a step of annealing the semiconductor substrate; and a step of epitaxially growing a semiconductor thin film on the surface of the semiconductor substrate; A method for manufacturing a semiconductor device comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing is performed in a vacuum or an inert gas atmosphere at 1100 ° C. or lower. 3. The method according to claim 1, wherein the annealing is performed at 850 ° C. or less.
A method for manufacturing a semiconductor device according to claim 2. 4. The method according to claim 1, wherein said epitaxial growth includes selective epitaxial growth. 5. The step of annealing the semiconductor substrate and the step of forming the semiconductor thin film include a vacuum chamber having a degree of vacuum of 1 × 10 ^-10 to 1 × 10 ^-1 Torr, and a substrate in the center of the vacuum chamber. A step of preparing a thin-film manufacturing apparatus comprising: a substrate holding unit for holding the substrate; a heating unit for applying radiant heat to one surface of the substrate; Holding the semiconductor substrate on the substrate holding means, annealing the semiconductor substrate with the heating means, supplying the reaction gas from the reaction gas supply means to the other surface of the semiconductor substrate, 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of epitaxially growing a semiconductor thin film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed by implanting ions containing a Group 3 element such as boron, aluminum, potassium, and indium. 7. The method according to claim 1, wherein the ion implantation is performed by implanting ions containing a Group 4 element such as carbon, silicon or germanium. 8. The method according to claim 1, wherein the ion implantation includes nitrogen, phosphorus, arsenic,
The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by implanting ions containing a group V element such as antimony. 9. The method according to claim 1, wherein the ion implantation is performed by implanting ions containing a Group 7 element such as fluorine, chlorine, bromine, and iodine. 10. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed by ion implantation of a Group 8 element such as helium, neon, argon, and krypton. 11. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming a semiconductor thin film on the surface of the semiconductor substrate, forming an element isolation region in the surface of the semiconductor substrate including the semiconductor thin film. Method. 12. A step of preparing a semiconductor substrate; a step of forming, in a main surface of the semiconductor substrate, an element isolation region for separating an element region from another element region; and implanting ions into the main surface of the semiconductor substrate. A step of annealing the semiconductor substrate; and a step of epitaxially growing a semiconductor thin film on the element region. 13. A step of preparing a semiconductor substrate; a step of forming an element isolation region in a main surface of the semiconductor substrate, which isolates an element region from another element region; and forming a gate electrode in the element region. A step of implanting ions into a main surface of the semiconductor substrate; a step of annealing the semiconductor substrate; and forming source / drain regions in the main surface of the semiconductor substrate on both sides of the gate electrode. A method of manufacturing a semiconductor device, comprising: a step of: epitaxially growing a semiconductor thin film on the source / drain regions. 14. A step of preparing a semiconductor substrate; a step of forming an element isolation region in a main surface of the semiconductor substrate for isolating an element region from another element region; and forming a gate on the semiconductor substrate. Forming an electrode; L in the element region on both sides of the gate electrode;
Forming a low concentration portion of the source / drain region of the DD structure; forming sidewall spacers on both sides of the gate electrode; and forming a high concentration portion of the source / drain region of the LDD structure on both sides of the gate electrode. Forming an interlayer insulating film on the surface of the semiconductor substrate so as to cover the gate electrode; and exposing a part of the surface of the source / drain region in the interlayer insulating film. Forming a contact hole; implanting ions into the bottom surface of the contact hole; annealing the semiconductor substrate; and epitaxially growing a semiconductor thin film on the bottom surface of the contact hole. Production method.