JP2800692B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a preferable method of forming an element isolation region.

[0002]

2. Description of the Related Art Silicon insulated gate field effect type (hereinafter referred to as MOS type) semiconductor elements have been miniaturized, and their design rules have been developed around 0.2 μm.
The study of design rules of μm or less is also active. Since the MOS type semiconductor element of such a size is approaching a physical limit, structural improvement is indispensable.

As an example, there is a structure in which the source / drain regions of a MOS transistor are raised as disclosed in Japanese Patent Application Laid-Open No. 64-59861. This technique will be described with reference to FIG.

First, in FIG. 5A, a silicon substrate 5 is formed.
An element isolation region 502 is formed on the semiconductor device 01 by a selective oxidation method called LOCOS, and the gate insulating film 503, the gate electrode 504, the side surfaces of the gate electrode 504, A gate structure composed of a silicon oxide film 505 covering the upper surface is formed.

[0005] Next, in FIG.
02, the surface of the silicon substrate 501 in the groove-shaped space 506 sandwiched between the gate structure and the gate structure is exposed, and a silicon layer 507 is grown by a selective epitaxial method to form a source / drain region.

Next, a polycrystalline silicon film 508 is formed on the entire surface in FIG. 5C, and thereafter, the polycrystalline silicon film 508 is patterned to form a source / drain electrode wiring 509 in FIG. 5D.

Alternatively, a polycrystalline silicon layer is deposited in a trench-shaped space 506 sandwiched between the element isolation region 502 and the gate structure, and the interface between the polycrystalline silicon layer and the silicon substrate is made amorphous by implanting Si ions. Then, the amorphous silicon can be converted into single crystal silicon by heat treatment to form source / drain regions, and the upper polycrystalline silicon layer can be used as source / drain electrode wiring.

[0008] With such a structure in which the source / drain region and its electrode wiring are formed in the silicon layer stacked on the surface of the silicon substrate, the source / drain electrode wiring can be formed in a self-aligned manner without requiring a contact hole. Therefore, the area occupied by the MOS transistors can be reduced, resulting in a highly integrated semiconductor device.

[0009]

When the height of the element isolation region 502 from the main surface of the semiconductor substrate 501 is too low in the above-described structure, as shown in FIG. The epitaxially grown silicon layers 509 come into contact with each other on the element isolation region 502, making it impossible to separate the elements. Further, if selective epitaxial growth is performed so as to lower the silicon layer 509 in order to avoid such an inconvenient contact, a predetermined film thickness for forming the source / drain region and its electrode wiring cannot be obtained.

On the other hand, FIG. 6B shows that when the height of the element isolation region 502 is too low, a polycrystalline silicon layer is deposited,
This shows that the interface is made amorphous by ion implantation of Si ions, the amorphous silicon is converted to single crystal silicon by heat treatment, and the silicon layer 509A is formed by anisotropic etching. Therefore, this upper part cannot be used as the electrode wiring of the source / drain region. When patterning is performed by isotropic etching, the entire thickness of the silicon layer is reduced, and a predetermined thickness for forming the source / drain region and its electrode wiring cannot be obtained.

On the other hand, if the height of the element isolation region 502 from the main surface of the semiconductor substrate 501 is too high, FIG.
In both cases (A) and FIG. 6 (B), since the gate electrode is formed by patterning after forming the element isolation region, the fine gate is formed because the upper surface of the element isolation region is too high and the step is too large. It is difficult to form electrodes with high accuracy.

Therefore, in order to obtain an accurate element function and an accurate element isolation function, the relationship between the height of the element isolation region and the height (thickness) of the gate electrode needs to be within an appropriate range.

In an actual semiconductor device, in order to avoid the problems shown in FIGS. 6A and 6B, the height of the upper surface of the element isolation region must be higher than half the height of the gate electrode structure. On the other hand, in order to facilitate the patterning of the gate electrode, it is practical to reduce the height of the upper surface of the element isolation region to about the upper surface of the gate electrode formed on the gate insulating film.

However, in the prior art, the height of the element isolation region, that is, the dimension between the main surface of the silicon substrate and the upper surface of the element isolation region cannot be obtained with good controllability.
The relative relationship between the height of the gate electrode or the gate structure and the height of the element isolation region is not an appropriate value, which makes it difficult to form a preferable stacked silicon layer structure with good reproducibility.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of controlling the height of the upper surface of a buried element isolation region from a main surface of a semiconductor substrate to a predetermined value with good controllability. It is.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a MOS transistor whose occupied area is reduced by using the buried element isolation region.

[0017]

A feature of the present invention is a step of forming a mask film having a predetermined thickness on a main surface of a semiconductor substrate and having an opening reaching the main surface; Forming a groove in the semiconductor substrate exposed in the opening using a mask as a mask, filling the groove with an insulating film of a different material from the mask film, and placing the upper surface of the insulating film on the upper surface of the mask film. A matching step and a step of removing the mask film, thereby forming a buried element isolation region buried in the semiconductor substrate and protruding from the main surface by a predetermined height from the insulating film. A method for manufacturing a semiconductor device.

Here, the mask film includes a first mask member and a second mask member, and the first mask member formed on the main surface of the semiconductor substrate with the predetermined thickness has the main surface. Forming an opening reaching the surface of the opening, forming an sidewall by the second member on a side surface of the opening having an anisotropic etching step, and forming the opening by an inner wall of the sidewall. it can.

Further, a first side wall insulating film can be formed on a side surface of a portion of the insulating film which becomes the buried type element isolation region from a main surface of the semiconductor substrate.

Further, a gate insulating film can be formed on a main surface of the semiconductor substrate partitioned by the buried element isolation region, and a gate electrode can be formed on the gate insulating film. In this case, a second sidewall insulating film can be formed on the side surface of the gate electrode. Preferably, a silicon layer is deposited on the main surface of the semiconductor substrate exposed between the gate electrode and the buried element isolation region.

[0021]

As described above, according to the present invention, since the height of the upper surface of the buried element isolation region is determined by the thickness of the mask film, the buried element isolation region having a predetermined height can be controlled with good controllability. can get.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure
FIG. 1 is a sectional view showing a manufacturing method of an example serving as a reference of the present invention in the order of steps.

First, in FIG. 1A, a phosphorus-doped silicon oxide film, ie, a PSG film 102 serving as a mask film is formed on a main surface 101M of a single-crystal P-type silicon substrate 101 to a predetermined thickness T _1. Then, an opening 103 surrounding the element region 101A is formed. And the PSG film 102
Is used as a mask to form an element region 10 on a P-type silicon substrate 101.
A groove 104 surrounding 1A is formed. The groove 104 has a depth necessary for element isolation in the substrate.

Next, referring to FIG. 1B, a silicon oxide film (N) that fills the trench 104 and is deposited on the PSG film 102 is formed.
A non-doped silicon oxide film 105 containing no type or P-type impurities is formed as a whole, and etched back under the condition that the silicon oxide film 105 is predominantly etched with respect to the PSG film 102, thereby forming silicon in the trench. The upper surface 105M of the oxide film 105 is replaced with the upper surface 102M of the PSG film 102.
To match.

Next, in FIG. 1C, the PSG film 102
Is removed by etching. This etching can remove only the PSG film 102 without etching the silicon oxide film 105 while maintaining relatively high selectivity with a hydrofluoric acid-based etchant. Or, for example, IED
M 92-259, 10.1.1-10.1.4, a dry treatment method, that is, the use of hydrofluoric acid vapor under reduced pressure substantially etches the silicon oxide film 105 containing no impurities. The PSG film 102 can be entirely removed without performing.

As a result, the element region 101A is surrounded and separated from the element region 101B and the element region 101C.
Buried isolation region 105 that protrudes from the substrate principal surface 101M by a predetermined height T ₁ is composed of a silicon oxide film 105.

Next, in FIG. 2A, a first side wall insulating film 106 may be formed by, for example, a silicon oxide film on the side surface of the silicon oxide film 105 protruding from the main surface 101M of the substrate by anisotropic etching. it can. This first sidewall insulating film 106 may not be formed. That is, although the presence of the first sidewall insulating film 106 goes against miniaturization, the leakage current can be reduced by covering the end of the buried type element isolation region 105 protruding from the main surface.
The selection is made according to the required element characteristics (whether to give priority to miniaturization or to give priority to improvement of reliability and reduction of leak current).

After that, the gate oxide film 201 is formed in the element region 1.
A polycrystalline silicon film 20 for forming a gate electrode is formed on the main surface 101M of the first electrode 101A, 101B, 101C by thermal oxidation.
2 is entirely deposited by a CVD method, and a silicon oxide film 2 is
03 is formed by thermal oxidation, and the polycrystalline silicon film 202 and the silicon oxide film 203 are patterned together to form the silicon gate electrode 202 and the upper surface insulating film 203.

Here, the value obtained by adding the thickness of the gate insulating film 201, the thickness of the silicon gate electrode 202, and the thickness of the upper insulating film 203, that is, the height of the upper surface 107M of the upper insulating film from the main surface 101M of the substrate. When T ₂ a is, T ₂ ≧ T
₁ > (1/2) × T ₂ needs to be satisfied.
For example, when T ₂ is 0.2 μm, T ₁ is a value larger than 0.1 μm and 0.2 or less. Here, the insulating films 201 and
Since the film thickness of 03 is very thin as compared with the silicon gate electrode 202, T ₂ is actually determined by the film thickness of the polycrystalline silicon film 202 for forming the silicon gate electrode.

This patterning must be selectively performed using a gas containing halogen (for example, a mixed gas of HBr and SF ₆ or a mixed gas of Cl ₂ and O ₂ ) in order to eliminate the etching residue at the step. There is.

Thereafter, a second side wall insulating film 204 is formed on the side surface of the gate electrode 203, thereby forming a gate structure 107 including the gate oxide film 201, the gate electrode 202, the upper surface insulating film 203, and the second side wall insulating film 204. Is configured.

Since the second sidewall insulating film 204 is formed by forming an insulating film on the entire surface and etching back by anisotropic etching, the materials of the upper insulating film 203 and the second sidewall insulating film 204 are changed. . For example, since the upper surface insulating film 203 is a silicon oxide film, it is necessary to configure the second sidewall insulating film 204 with a silicon nitride film to have selectivity. Further, since the second sidewall insulating film is formed on the substrate after the entire surface is deposited by etch back by anisotropic etching in the vertical direction, the presence of the first sidewall insulating film is not significantly affected.

The distance between the first sidewall insulating film 106 and the second sidewall insulating film 204, that is, the width of the groove-shaped space 110 in which the main surface 101M of the substrate is exposed in the element region is, for example, 0.2 μm.

Next, in FIG. 2B, a polycrystalline silicon layer 109 is deposited on the entire surface to fill the groove-shaped space 110.
Phosphorus doping (which may contain phosphorus at the time of depositing the polycrystalline silicon layer 109) is performed, and a gas having little anisotropy (for example, a gas containing SF ₆ or the like as a main component) is formed on the gate electrode structure 107 and buried. The polycrystalline silicon layer 109 is left only inside the groove-shaped space 110 by etching away from the silicon oxide film 105 in the mold element isolation region. Phosphorous is transferred from the polycrystalline silicon layer 109 to the silicon substrate 1.
01 and an N-type source / drain diffusion layer 108
Is formed.

The polycrystalline silicon layer is removed by etching under unnecessary over etching conditions since unnecessary portions other than the inside of the groove-shaped space 110 need to be completely removed.
Therefore, the main surface 101M of the substrate is formed inside the groove-shaped space 110.
The thickness of the upper polycrystalline silicon layer 109 is equal to the above-described T
_1, the case of T _2, for example, a 0.05Myuemu～0.15Myuemu.

The upper portion of the polycrystalline silicon layer 109 inside the groove-shaped space 110 serves as a source / drain extraction electrode.

In the above example, the space 110 is filled with the polycrystalline silicon layer 109, and the N-type impurity phosphorus is introduced into the single-crystal P-type silicon substrate 101 therefrom.

However, the interface between the polycrystalline silicon layer and the silicon substrate is made amorphous by implanting Si ions into the polycrystalline silicon layer inside the groove-shaped space 110, and the amorphous silicon is made simple by heat treatment. The source / drain regions may be converted into crystalline silicon, and the upper polycrystalline silicon portion may be used as a source / drain extraction electrode.

Alternatively, as a means for providing a silicon layer on the silicon substrate inside the groove-shaped space 110, the exposed surface of the silicon substrate 501 is seeded, and the N-type silicon layer is formed by selective epitaxial method. It may be grown only inside, the lower part may be a source / drain region, and the upper part may be a source / drain extraction electrode.

If the plurality of gate electrodes 202 in the semiconductor device have a single conductivity type (N-type or P-type), a single type impurity may be removed when forming the polycrystalline silicon film 202 for the gate electrode. The doping method is desirable. On the other hand, when the conductivity types of the plurality of gate electrodes in the semiconductor device are N-type and P-type, each conductivity-type impurity is introduced by an ion implantation method in a later step.

FIG. 3 is a sectional view showing a method of manufacturing a buried element isolation region according to an embodiment of the present invention in the order of steps. FIG.
In FIG. 7, the portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals, and therefore, duplicate description will be omitted as much as possible.

In FIG. 1, the buried type element isolation region 105
If you try to reduce the width W ₁ of the smallest dimension that can be formed in the PR process for forming the opening 103 in the PSG film 102 constituting the mask film is determined.

However, in the manufacturing method shown in FIG. 3, the mask films are the PSG film 102 of the first mask member and the boron-doped silicon oxide film, ie, the BSG film 302 of the second mask member.
Of the side wall insulating film.

Therefore, when the width W ₁ of the buried element isolation region 105 is to be reduced, the BSG film is deposited on the entire surface after forming the opening 103 having the minimum size that can be formed by, for example, the PR process in the PSG film 102. Then, this is anisotropically etched to form the sidewall insulating film 202 of the BSG film, and the inner wall thereof is used as the opening 303 for determining the width W ₂ of the buried element isolation region 105. Area 105
The width W ₂ of the can be reduced than the minimum dimension that can be formed by PR process. After the trench 104 is filled with a non-doped silicon oxide film 105 in FIG. 3B and the upper surfaces thereof are made to coincide with each other by etch-back, the BSG film 302 contains boron as an impurity. )
3C, the non-doped silicon oxide film 105 is removed without etching by the same method as the etching removal method described in FIG.

After the heat treatment shown in FIG.
Boron can be diffused from the G film 302 into the P-type silicon substrate 101 to form the P ⁺ -type channel stopper region 304.

FIG. 4A is a plan view showing a case where the buried element isolation region 105 surrounding the element region 101A is formed to have a large width in the structure shown in FIG. 2B.
FIG. 4B is a cross-sectional view taken along the line BB of FIG.
In FIG. 4, the same or similar parts as those in FIG.

The end in the width direction of the portion where the gate electrode 202 rides on the upper surface 105M of the silicon oxide film 105 in the buried element isolation region, which is the field region, ie, the second end.
Polycrystalline silicon layer 109 on the side surface of side wall insulating film 204 of FIG.
Is formed thickly (in the vertical direction). Therefore, in order to remove the polycrystalline silicon layer 109 at that portion with a highly anisotropic gas, sufficient over-etching is required so that the residual polycrystalline silicon 109R does not occur. On the other hand, it is necessary to control so that the polycrystalline silicon layer 109 in the groove-shaped space 110 is not etched too much.

For this reason, in order to remove an unnecessary portion in the polycrystalline silicon layer 109, a highly anisotropic gas used when forming the gate electrode 202 cannot be used. As described in the step 2 (B), it is necessary to use a gas having little anisotropy.

That is, in order to remove the polycrystalline silicon layer formed on the side surface of the gate electrode at the portion where the gate electrode runs over the buried element isolation region, it is necessary to utilize the etching action from the side surface.

The groove-shaped space 110 is provided with a rectangular projection on the outside, and the polycrystalline silicon film 109 filled therein is connected to the lead-out portions 109C and 109 of the source / drain regions, respectively.
C.

[0051]

According to the present invention as described in the foregoing, since the height T ₁ of the upper surface 105M of the buried isolation region 105 is determined by the thickness of the mask layer 102, good controllability predetermined height Embedded element isolation region is obtained.

Therefore, the silicon layer 109 having a lower portion as a source / drain region and an upper portion as a source / drain electrode wiring is formed to have a predetermined thickness without a sharp inclination and without an undesirable short circuit. can do.

Further, a pattern for forming the shape of the gate electrode is formed.
There is no hindrance to training .

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a step subsequent to FIG. 1 in order;

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention corresponding to the step of FIG. 1 in the order of steps;

FIGS. 4A and 4B are views showing an example of a semiconductor device according to an embodiment of the present invention, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along the line BB of FIG.

FIG. 5 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

FIG. 6 is a cross-sectional view showing a problem of the related art;
(A) shows a case where a silicon layer is grown by a selective epitaxial method, and (B) shows a case where a polycrystalline silicon is deposited and a silicon layer is formed by patterning.

[Explanation of symbols]

Reference Signs List 101 P-type silicon substrate 101M Main surface of silicon substrate 101A, 101B, 101C Element region of silicon substrate 102 PSG film 102M Upper surface of PSG film 103 Opening 104 Groove 105 Silicon oxide film to be buried element isolation region 105M Silicon oxide film Upper surface 106 First sidewall insulating film 107 Gate structure 107M Upper surface of gate structure (upper surface of upper insulating film) 108 Source / drain diffusion layer 109 Embedded silicon layer (polycrystalline silicon layer) 109C Source / drain region extraction portion 109R Polycrystalline residual 110 trench-like space 201 a gate oxide film of the silicon 202 gate electrode 203 top insulating film 204 second sidewall insulating film 302 BSG film 303 opening 304 P ⁺ -type channel stopper region 501 silicon substrate 502 element isolation region 50 The gate insulating film 504 gate electrode 505 silicon oxide film 506 trench-like space 507 silicon layer 508 polysilicon film 509 source / drain electrode wiring

Claims (4)

(57) [Claims] A step of forming a mask film of a first material having a predetermined thickness on the main surface of the semiconductor substrate and having an opening reaching the main surface ; different
After depositing a film of the second material, anisotropic etching is performed.
By doing so, only the side wall of the opening of the first mask film is
Forming a sidewall of the second material and the above method
Using the mask film formed in step 1 as a mask ,
Opening of the mask film is reduced by the sidewall of the second material.
Forming a groove in said semiconductor substrate which is exposed to small is to have the opening, different from the first from the first and second materials
Filling the groove with an insulating film of a material of No. 3 and matching the upper surface of the insulating film with the upper surface of the mask film;
Whether the mask film of the first material and the sidewall of the second material
And a step of removing the Ranaru mask film, which by the embedded in the semiconductor substrate and the buried isolation region that protrudes a predetermined height from the main surface was constructed from the third insulating film A method for manufacturing a semiconductor device, comprising: Wherein a gate insulating film on the main surface of the semiconductor substrate which is defined by the buried isolation region, claim 1, characterized in that forming a gate electrode on the gate insulating film The manufacturing method of the semiconductor device described in the above. 3. The method according to claim 2 , wherein a second sidewall insulating film is formed on a side surface of the gate electrode. Claim 3 or claim, characterized by comprising the step of depositing a silicon layer on a major surface of said semiconductor substrate which is exposed between the gate electrode and the device isolation region
5. The method for manufacturing a semiconductor device according to item 4 .