JPH02260660A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To restrain a parasitic channel effect by a method wherein the groove of an element isolating region is formed using a required laminated film as a mask, and the groove is rounded. CONSTITUTION:A thermal oxide film 11 and an oxidation-resistant silicon nitride film 12 are laminated on a P-type Si substrate 1, which is selectively etched into a patterned mask, and a thermal oxide film 13 biting into the substrate 1 is formed through a thermal treatment to build an element isolating region. Then, the film 13 is removed through etching and a groove is provided to the element isolating region using the film 12 as a mask. A thermal oxide film 21 is formed on the inner wall of the groove 14 and the upper corners of the groove 14 are rounded. Thereafter, a thermal oxide film 22, a gate electrode 4, and others are provided, and thus a MOS integrated circuit restrained in parasitic channel effect and improved in cutoff characteristic can be realized, as an element isolating groove is rounded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a MOS type semiconductor device using element isolation technology by embedding an insulating film. .

(Prior art) Conventionally, in MO3 integrated circuits, it has been necessary to form a thick insulating film in the isolation region between elements (so-called field region) in order to eliminate insulation defects caused by parasitic channels and to reduce parasitic capacitance of wiring. It is being done. As one example, there is known a method (BOX method) in which a trench is formed in an element isolation region by etching, and an oxide film is flattened therein by vapor phase epitaxy (CVD method). This method has the characteristics that there is no bead bark caused by the LOCO8 method, that a fine element region can be formed, and that the surface has excellent flatness.

However, this BOX method also has problems that need to be solved.

For example, in the BOX method, a buried CVD oxide film is formed by an etch-back method using a resist, so that the Si substrate is exposed within the surface of the sea urchin, creating a convex corner in the channel region. The situation will be explained using FIGS. 7(a) and 7(b). 7(a) and 7(b), a trench 22 is formed on a Si substrate 21 by reactive ion etching (RIE), a CVD oxide film 23 is buried in this trench 22, and a gate insulating film 24 is formed in the element region. The state in which the gate electrode 25 is formed (the channel direction is perpendicular to the paper surface) is shown. If the surface of the buried oxide film 23 matches the surface of the Si substrate in the element region as shown in FIG. 7(a), there is no problem. However, in reality, oxide film filling by etchback is not performed with good controllability, and as shown in FIG. 7(b),
The Si substrate in the element region becomes convex. Then, a parasitic channel is formed at corner A, a hump appears in the subthreshold characteristic of the drain current, and the cutoff characteristic of the MOS transistor deteriorates. Its characteristics are shown in FIG. 6 (c) as a conventional example. (a) in Figure 6 is
As shown in FIG. 7(a), this is the characteristic in an ideal state in which the element region does not have a convex shape, and no hump appears in this case.

(Problems to be Solved by the Invention) As described above, when an MO8 integrated circuit is formed using the conventional insulating film embedding method, the substrate in the channel region becomes convex, corners are formed, a parasitic channel is formed, and a cut-off occurs. There was a problem that the characteristics deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a method for manufacturing a MOS type semiconductor device with an insulating film buried structure that provides excellent cutoff characteristics.

[Structure of the Invention] (Means for Solving the Problem) The present invention forms a groove in an element isolation region of a semiconductor substrate, rounds the upper corner of the groove, and then forms a groove in the element region with a gate insulating film interposed therebetween. to form a gate electrode.

(Function) According to the present invention, even if the substrate of the element region is formed to protrude from the surface of the insulating film buried in the element isolation region,
By rounding the corners of the element region to a certain degree, the effects of parasitic channels can be suppressed, and a MOS integrated circuit with excellent cutoff characteristics can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) and 1(b) are a perspective view and a sectional view showing one MOS run lister portion in a MOS integrated circuit according to an embodiment. The cross-sectional view is a plane perpendicular to the channel length direction. FIGS. 2(a) to 2(h) are manufacturing process diagrams viewed in cross section.

First, p with an impurity concentration of about I x 1017/cn3
A thermal oxide film 11 of approximately 50 NO+ and a CVD silicon nitride film 12 of approximately 200 NA+ are laminated on the surface of a type Si substrate 1, and patterned by selective etching so as to remain only in the element region (see FIG. 2(a)). )).

Next, thermal oxidation is performed in a wet atmosphere at about 1000° C. to form a thermal oxide film 13 of about 20 Cj nm on the substrate surface of the element isolation region (FIG. 2(b)). At this time, the thermal oxide film 13 is formed so as to dig into the element region, forming a so-called bird's beak.

Next, the thermal oxide film 13 is removed by etching using NH, F solution, etc., and then RIE is performed using the nitride film 12 as a mask.
A groove 14 having a depth of about 0.3 μm is formed in the element isolation region (FIG. 2(C)).

Groove 14 is formed with generally vertical sidewalls as shown.

Next, if necessary, the inner wall of the groove 14 is etched by 50 to 100 etches with an etching solution containing an alkaline solution to remove the layer damaged by RIE. Then, thermal oxidation is performed to form the groove 14.
An oxide film of about 30 nm on the inner wall of 2. (Fig. 2(d)). At this time, a p-type layer may be formed by implanting boron ions into the groove bottom of the element isolation region to prevent field reversal. When including the step of forming this anti-inversion layer, first a thin thermal oxide film of about 10 rv is formed, ions are implanted, and then thermal oxidation is performed to form an oxide film of about 2On11.

Next, apply a silicon oxide film of about 400 cm by CVD to the entire surface.
nm is deposited, and a photoresist 15 is applied to flatten the surface (FIG. 2(e)). After that, photoresist 1
The entire surface is etched (so-called etch-back) under gas conditions in which the etching conditions are adjusted so that the etching speed is equal to that of the oxide film 2 and the nitride film 12 on the substrate (FIG. 2(r)). .

Next, the nitride film 12 is selectively removed by chemical dry etching (CD E), and then the underlying thermal oxide film 11 is etched using, for example, NH4F solution to expose the substrate surface in the element region (second Figure (g)). In this oxide film etching step, the upper corner 7 of the groove has a radius of curvature of 0.
Form a roundness of 0.05 μm or more. The radius of curvature of this roundness is determined by the radius of curvature of the oxide films 11 and 2. depends on the film thickness.

Thereafter, a gate oxide film 3 is formed in the element region, and a phosphorous-doped polycrystalline silicon film is deposited thereon by CVD and patterned to form a gate electrode 4.

Thereafter, arsenic or phosphorus is ion-implanted into the source 5 according to a normal process. A drain 6 is formed (FIG. 2(h)).

At this time, the source and drain may have an LDD structure by performing ion implantation with a spacer provided on the side wall of the gate electrode.

Finally, although not shown in the figure, a CVD oxide film is deposited on the entire surface, contact holes are opened, and AI wiring is formed to complete the process.

Gate voltage Vg of the MOS) run lister according to this embodiment
FIG. 6 shows the characteristics of the drain current 1d and the drain current 1d. 71F1 constant condition is drain voltage Vd-0, IV.

The source voltage OV and the substrate voltage Ov. The curve in Figure 6 (
b) The radius of curvature of the upper corner of the groove is set to ``-0.05 μm.
In this case, the hump characteristic is suppressed compared to the conventional example. In addition, when it is set to r-1 μm, almost the same characteristics as the curve (A) in the case of the ideal state are obtained. As described above, by making the corners round with a radius of curvature of 0.05 μm or more, the subthreshold characteristics of the MOS transistor are improved and excellent cutoff characteristics can be obtained.

FIGS. 3(a) and 3(b) show the main steps of another embodiment. Parts corresponding to those in the previous embodiment are given the same reference numerals as in the previous embodiment. In this embodiment, an oxide film 11 and a nitride film 1
After patterning the laminated film No. 2, grooves 14 are first formed in the element isolation region by RIE using this as a mask (FIG. 3(a)). After that, it is heated to 1000℃ including water vapor.
Thermal oxidation is performed in an atmosphere of
An oxide film 21 with a thickness of approximately nm is formed (FIG. 3(b)). At this time, the thermal oxide film 21 bites into the element region, so that the upper corner 7 of the trench is rounded with a radius of curvature of 0.05 μm or more. After this, it is sufficient to proceed to the step shown in FIG. 2(e).

FIGS. 4(a) to 4(c) show main steps of another embodiment that is a modification of the above embodiment. In this embodiment, in order to enhance the masking effect during RIE in the embodiment of FIG.
A CVD oxide film 16 of about 20 r+m is overlaid thereon, and a trench 14 is formed in the element isolation region using these laminated films as a mask (FIG. 4(a)). Next, in order to make it easier for bird's beaks to form during oxidation, the oxide film 11 whose end surface is exposed in the groove 14 is slightly laterally etched, for example, by about 0.1 μm, by solution etching, and the end surface is set back ( Figure 4(b)). Thereafter, as in the previous embodiment, a thermal oxide film 2. (Fig. 4(C)).

As a result, a smooth roundness can be formed in the layer.

FIGS. 5(a) to 5(d) are further modified embodiments of the embodiment shown in FIG.
The following shows the main steps when using . Figure 5(a)(b)
) are the same as in Figures 4(a) and (b). Thereafter, the groove side surfaces are etched by CDE using a mixture of CF4 and 02 gas (FIG. 5(C)). As a result, the upper corner 7 of the groove 14 is rounded, and at the same time the bottom corner is also rounded. Thereafter, if necessary, thermal oxidation is performed in a wet atmosphere to form an oxide film 21 of about 5OnI11 on the inner wall of the groove (see Fig. 5 (d).
)). The rest is the same as in the previous embodiment.

According to this embodiment, by using CDE to form the roundness, the magnitude of the curvature of the corner can be controlled with high precision by the etching time.

Furthermore, the damaged layer during RIE is also removed. In addition, in this embodiment, the corners at the bottom of the groove are also rounded, resulting in
This has the effect of alleviating stress due to the difference in thermal expansion coefficient between the insulating film and the substrate that will be embedded later. This suppresses the occurrence of crystal defects and suppresses leakage current at the source and drain junctions, making it possible to obtain excellent device characteristics.

The present invention is not limited to the above embodiments. For example, in the embodiment, a CVD oxide film is buried as an element isolation film, but a polycrystalline silicon film, PSG, or the like can also be buried as an element isolation film through the oxide film, and the present invention is also effective in that case. The gate electrode material is not limited to a polycrystalline silicon film, but may also be a high melting point metal such as molybdenum (M o ) or tungsten (W), or M o S i 2. W Si
2. A polycide film using silicide such as T t S i 2 may also be used.

As for the substrate, in addition to a p-type St substrate, a substrate in which a p-type well is formed on an n-type substrate can be used.

The MOS) run lister according to the invention consists of one transistor/
In addition to cells and transistors in 1-capacitor DRAM, various MO5 integrated circuits.

It can be applied to a CMO3 integrated circuit or a BiCMO5 circuit.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) show M according to an embodiment of the sixth invention.
OS) Perspective view and cross-sectional view showing the structure of the run lister, Part 2-
Figures (a) to (h) are cross-sectional views showing the manufacturing process, Figures 3 (a) and (b) are cross-sectional views showing the manufacturing process of the main parts of the other embodiment, and Figures 4 (a) to (c). ) is a cross-sectional view showing the manufacturing process of the main part of yet another embodiment, FIGS. 5(a) to (d) are cross-sectional views showing the manufacturing process of the main part of still another embodiment, and FIG. FIGS. 7(a) and 7(b) are cross-sectional views for explaining the conventional technology. 1...p-type Si substrate, 2...element isolation film, 2I...
・Thermal oxide film, 2□...CVD oxide film, 3...gate oxide film, 4...gate electrode, 5...source, 6...
・Drain, 7... Corner 11... Thermal oxide film,
12...CVD silicon nitride film, 13...thermal oxide film, 14...element isolation trench, 15...photoresist,
16...CVD oxide film.

Claims (4)

[Claims] (1) Forming a mask consisting of a laminated film of an oxide film and an oxidation-resistant film in the element formation area of the semiconductor substrate and performing thermal oxidation to oxidize the substrate surface in the element isolation area so as to partially penetrate into the element formation area. forming a film; removing the oxide film in the element isolation region by solution etching using the oxidation-resistant film as a mask; and forming a groove in the element isolation region by reactive ion etching using the oxidation-resistant film as a mask. forming a thermal oxide film on the inner wall surface of the trench and rounding the upper corner of the trench at the same time; embedding an element isolation film in the trench by vapor phase growth; A MOS comprising: forming a gate electrode on a substrate surface surrounded by a gate insulating film via a gate insulating film; and forming a source and a drain by introducing impurities using the gate electrode as a mask. A method for manufacturing a type semiconductor device. (2) forming a mask made of a laminated film of an oxide film and an oxidation-resistant film in the element formation region of the semiconductor substrate; and forming a groove in the element isolation region by reactive ion etching using the mask; A step of forming an oxide film on the inner wall surface of the element isolation region by thermal oxidation so as to partially penetrate into the element forming area, and at the same time forming a rounded upper corner of the groove, and forming an element in the groove by vapor phase growth. a step of embedding an isolation film; a step of forming a gate electrode on a substrate surface surrounded by the element isolation insulating film via a gate insulating film; and forming a source and a drain by introducing impurities using the gate electrode as a mask. A method for manufacturing a MOS type semiconductor device, comprising the steps of: 3. The MOS semiconductor device according to claim 2, further comprising the step of etching the oxide film by solution etching using the oxidation-resistant film as a mask after forming the groove to retreat the end face of the oxide film exposed on the inner wall of the groove. manufacturing method. (4) forming a mask made of a laminated film in the element formation region of the semiconductor substrate; forming a groove in the element isolation region by reactive ion etching using the mask; and forming a groove on the inner wall of the groove by isotropic etching. Retreating the exposed end face of the lower layer film, then etching the exposed surface of the substrate in the element isolation region by chemical dry etching, and simultaneously rounding the upper corner of the groove, and forming element isolation in the groove by vapor phase growth. a step of embedding a film; a step of forming a gate electrode on a substrate surface surrounded by the element isolation film via a gate insulating film; and a step of introducing impurities using the gate electrode as a mask to form a source and a drain. A method for manufacturing a MOS type semiconductor device, comprising: