JP2858510B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device , and more particularly to a bipolar transistor having a capacitance element.
And a method for producing the same .

[0002]

2. Description of the Related Art A conventional bipolar transistor having a capacitive element will be described with reference to the drawings. FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method for forming a capacitive element. When a capacitor is formed by providing a nitride film between upper and lower polycrystalline silicon layers serving as electrodes, a method of oxidizing the nitride film is generally used. This is because the nitride film formed on the polycrystalline silicon layer has defects such as pinholes, and a current leak occurs unless the nitride film is oxidized. Conventionally, when a capacitor having such a structure is formed in a bipolar transistor, an opening for forming a base is provided, a polycrystalline silicon layer doped with impurities is formed thereon, and an insulating film for the capacitor is formed thereon. It was formed and a polycrystalline silicon layer was further formed thereon.

First, as shown in FIG. 3A, an N ⁺ -type buried layer 2 is formed in an element forming region on a P-type semiconductor substrate 1 made of silicon, and then a 1.0 μm-thick buried layer 2 is formed thereon. An N-type epitaxial layer 3 is formed by epitaxial growth. Then, after insulating and isolating the element region, an oxide film 4 having a thickness of 0.2 μm is formed using a CVD method. Thereafter, openings 5A and 8A are formed in the collector electrode forming region and the base forming region.
A is provided.

[0004] Next, as shown in FIG. 3 (b), a first polycrystalline silicon layer 6 A having a thickness of 0.2 μm is formed on the entire surface by using the CVD method, and then is formed in the first polycrystalline silicon layer 6 A. The resistance is reduced by ion implantation of boron as an impurity. next,
The photoresist film leaving the base of the drawer portion and the collector portion is patterned by etching using SF ₆ as a mask, to remove unnecessary polycrystalline silicon layer to form a base and collector lead-out electrode.

[0005] Next, as shown in FIG.
Film 7A for a capacitive element having a thickness of 0.01 μm by using the
Is formed, heat treatment is performed on the nitride film 7A in an oxidizing atmosphere to oxidize and fill defects such as pinholes in the nitride film. Thereafter, a second polycrystalline silicon layer 9A having a thickness of 0.2 μm is formed using a CVD method, and then patterned,
An upper electrode of the capacitor is formed.

As shown in FIG. 3D, an oxide film 10A is formed by a CVD method, an opening 11 for forming an emitter is formed, and then a base 12 is formed by an ion implantation method. Next, after forming a nitride film on the entire surface, etching is performed to form sidewalls 13 in the openings 11. Next, after forming a polycrystalline silicon layer and implanting arsenic ions, the emitter 14 is formed by thermal diffusion.

[0007]

In a semiconductor device, it is required to increase the degree of integration of elements. In order to improve the degree of integration of the capacitive element, the capacitance value per unit area must be increased, and it is necessary to increase either the insulating film for the capacitive element or the dielectric constant of the insulating film. is there. In order to increase the dielectric constant, it is necessary to change the material of the insulating film for the capacitor, and to increase the capacitance with the same material, the insulating film needs to be thin. Therefore, in order to increase the capacitance per unit area, it is necessary to form an insulating film having a small leak and a small thickness.

When a capacitor is formed in a conventional bipolar semiconductor device, an opening for forming a base is provided, a polycrystalline silicon layer doped with impurities is formed thereon, and an insulating film for the capacitor is formed thereon. Then, a polycrystalline silicon layer is formed thereon. Therefore, when the insulating film for the capacitor is heat-treated in an oxidizing atmosphere, boron as an impurity is diffused from the lower polycrystalline silicon film into the silicon substrate and has a high concentration (from 1 × 10 ¹⁸ / cm ³ to 1 ×). 10 ¹⁹
/ Cm ³ ) is formed in the silicon substrate. This region has an impurity concentration of 1 × 10 ¹⁷ /
a region forming a base of about 1 × 10 ¹⁹ / cm ³ from cm ^3, a problem that the high concentration of impurities by heat treatment in an oxidizing atmosphere is diffused, it is impossible to form the desired base was there.

Therefore, in order to prevent impurities from diffusing from the first polycrystalline silicon layer into the substrate during the heat treatment of the nitride film, it is necessary to perform the heat treatment in an oxidizing atmosphere of the nitride film at a low temperature for a short time. However, the heat treatment under such conditions cannot sufficiently fill the defects of the nitride film, and it is difficult to form a capacitance nitride film having a small current leak. There was a problem that it was difficult to do.

It is an object of the present invention to provide a bipolar semiconductor device having a small leakage and a large capacitance per unit area.

[0011]

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a lower electrode made of a polycrystalline silicon layer on a semiconductor substrate via a first insulation; Forming a capacitive insulating film on the entire surface including the insulating film; and patterning the capacitive insulating film and the first insulating film to form an opening for forming a base reaching the semiconductor substrate.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate and then patterning the first insulating film to form a first opening for forming a collector extraction electrode; Forming a polycrystalline silicon layer over the entire surface including the opening, and forming a lower electrode filling the first opening by patterning; forming a capacitive insulating film over the entire surface including the lower electrode; Patterning an insulating film and the first insulating film to form a second opening for forming a base reaching the semiconductor substrate.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG.
1A to 1D are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention. In the bipolar static memory of the memory cell according to the present embodiment, a sufficient capacity is required between the collector and the base so that the retained information is not inverted when α-rays enter the memory cell. The present embodiment is an example of a memory cell in which a base region is formed in a self-aligned manner with respect to an emitter region, and a capacitor is formed between a base and a collector of a bipolar transistor using a polycrystalline silicon layer for extracting a base.

First, as shown in FIG. 1A, an N ⁺ type buried layer 2 is formed on a P type semiconductor substrate 1 made of silicon, and then an N type epitaxial layer 3 having a thickness of 1.0 μm is formed. Next, an oxide film 4 having a thickness of 0.2 μm is formed thereon by the CVD method. Next, an opening 5 is formed in the collector electrode forming region.
Is formed, a first polycrystalline silicon layer 6 having a thickness of 0.2 μm is grown on the entire surface by CVD, and then boron is introduced into the polycrystalline silicon layer by ion implantation.
Next, using the photoresist film as a mask, etching is performed by RIE using SF ₆ gas to form a lower electrode of the capacitive element composed of the first polycrystalline silicon layer 6 and a collector extraction electrode of the bipolar transistor. Next, FIG.
As shown in (b), a nitride film 7 for forming a capacitor having a thickness of 0.01 μm is grown on the entire surface by a low pressure CVD method, and a heat treatment is performed at 950 ° C. in an oxidizing atmosphere. Thereafter, an opening 8 is provided in a portion where the base and the emitter are to be formed by photolithography and etching.

Next, as shown in FIG. 1 (c), a second polycrystalline silicon layer 9 having a thickness of 0.2 μm is formed on the entire surface by using a low pressure CVD method, followed by patterning. The second polycrystalline silicon layer 9 is left only in the upper electrode portion. Next, a CVD oxide film 10 is formed on the entire surface.

As shown in FIG. 1D, an opening 11 is formed in the CVD oxide film 10 and the second polycrystalline silicon layer 9 in the same manner as in the prior art, and impurities are introduced by ion implantation to form the base 12. Form. Next, after forming a nitride film on the entire surface, etching is performed to form a sidewall in the opening 11. Next, a third polycrystalline silicon layer is formed, arsenic is ion-implanted, and then the emitter 14 is formed by thermal diffusion.

As described above, the first polycrystalline silicon layer 6 serving as the lower electrode of the capacitor element forming the lead electrode of the base and the nitride film 7 for forming the capacitor are formed, and the heat treatment in an oxidizing atmosphere is sufficiently performed. By doing so, a thin nitride film 7 with less pinholes and leaks can be formed without high-concentration boron diffusing into the silicon substrate from the opening for forming the base during the heat treatment as in the prior art. . For example, while the thickness of the conventional nitride film is 0.02 μm, according to the present embodiment, the thickness of the nitride film is 0.01 μm.
You can:

In the first embodiment, the case where the collector extraction electrode also serves as the lower electrode of the capacitor has been described.
As described above, a capacitive element may be formed on oxide film 4. Hereinafter, as a second embodiment, an example in which a single capacitive element is formed simultaneously with the formation of a bipolar transistor will be described with reference to FIG.

First, a CVD oxide film 4 is formed on an N-type epitaxial layer 3 on a P-type semiconductor substrate, and boron is introduced as an impurity into the polycrystalline silicon layer by an ion implantation method. Next, using the photoresist film as a mask, the polycrystalline silicon layer 6 is etched by RIE using SF ₆ gas to form a lower electrode of the capacitor and a collector lead electrode (not shown) of the bipolar transistor.

Thereafter, a 0.01 μm-thick nitride film 7 for forming a capacitor is grown by a low pressure CVD method, and a heat treatment is performed in a 950 ° C. atmosphere. After an opening (not shown) is provided by photolithography and etching at a portion where a base and an emitter are to be formed, a second polycrystalline silicon layer 9 having a thickness of 0.2 μm is formed on the entire surface by a low pressure CVD method. The second portion is formed only on the base extraction portion and the upper electrode portion of the capacitor by etching using photolithography and RIE.
Is left.

As described above, before forming the base extraction electrode, the first polycrystalline silicon layer 6 serving as the lower electrode of the capacitor and the nitride film 7 for forming the capacitor are formed, and the heat treatment in an oxidizing atmosphere is sufficiently performed. By doing so, it is possible to form a nitride film with less pinholes and leaks without diffusing high-concentration boron from the opening for forming the base into the silicon substrate during the heat treatment as in the conventional example.

[0023]

As described above, according to the present invention, it is possible to heat-treat a nitride film for a capacitor before forming a polycrystalline silicon layer of a base lead electrode. Sufficient heat treatment can be performed without considering diffusion of impurities from the crystalline silicon layer into the substrate. Therefore, since a thin nitride film having few defects such as pinholes can be used, a highly reliable capacitive element having a large capacity per unit area can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for describing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N ⁺ type buried layer 3 N-type epitaxial layer 4 Oxide film 5, 8 Opening 6, 6A First polycrystalline silicon layer 7, 7A Nitride film 9, 9A Second polycrystalline silicon Layer 10, 10A CVD oxide film 11 Opening 12 Base 13 Sidewall 14 Emitter

Claims (2)

(57) [Claims] A step of forming a lower electrode made of a polycrystalline silicon layer on a semiconductor substrate via a first insulating layer; a step of forming a capacitor insulating film over the entire surface including the lower electrode; Forming a base forming opening reaching the semiconductor substrate by patterning the first insulating film and the first insulating film. 2. A step of forming a first insulating film on a semiconductor substrate and then patterning it to form a first opening for forming a collector lead-out electrode, and forming polycrystalline silicon on the entire surface including the first opening. After forming the layer,
Forming a lower electrode that fills the opening of the substrate, forming a capacitive insulating film over the entire surface including the lower electrode, and patterning the capacitive insulating film and the first insulating film to reach the semiconductor substrate. Forming a second opening for forming the semiconductor device.