CN116435366A - Full-surrounding gate device based on semiconductor-on-insulator substrate and preparation method thereof - Google Patents
Full-surrounding gate device based on semiconductor-on-insulator substrate and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a full-surrounding gate device based on a semiconductor substrate on an insulator and a preparation method thereof. According to the preparation method of the full-surrounding gate device, the dummy gate structure is used as a mask to selectively etch until the side wall of the bottom dummy gate is exposed, so that the obtained bottom dummy gate is arranged in a centering manner relative to the middle line of the top dummy gate, and then the surrounding gate structure with improved alignment precision can be obtained through the formation of the dummy gate process, so that the process complexity of preparing the full-surrounding gate transistor is reduced, the grid leakage problem is improved, and meanwhile, the excellent electrical performance of the GAA device is exerted.
Description
Technical Field
The invention relates to a semiconductor integrated circuit design and manufacturing field; in particular to a full-surrounding gate device and a preparation method thereof.
Background
As microelectronic devices continue to shrink, it is expected that existing FinFET technologies will face a larger technology bottleneck at the 5 nm and 3 nm nodes, device performance will not be greatly improved as device size continues to shrink, and the continuous shrinking brings about problems of increased parasitic capacitance, etc. This requires new device technologies such as ring gate transistors with nanowire/nanoplate structures.
The gate-all-around field effect transistor (GAAFET) has a gate with four sides completely surrounding the channel, so that the gate can control the channel on four sides, and the electrostatic performance of the device is essentially improved. Currently, a gate-all-around field effect transistor has various manufacturing methods, wherein the process of a GAA device based on a bulk silicon superlattice substrate is complex, an epitaxial Si/SiGe superlattice structure is required when a suspended nanowire is formed, and a sacrificial layer in the superlattice structure is removed. In contrast, the manufacturing process of GAA devices based On Silicon-On-Insulator (SOI) substrates is much simpler.
Referring to fig. 1, a GAAFET device fabricated on a silicon-on-insulator substrate (vesio substrate) with embedded cavities is provided by etching a suspended silicon nanowire/nanoplatelet structure in the vesio substrate and fabricating a corresponding gate-all-around transistor. When manufacturing GAAFET devices based on cavity embedded silicon-on-insulator (vesio) substrates, it is necessary to ensure that the source-drain regions do not overlap the gates within the cavities too much to reduce parasitic capacitance and mitigate the bias field effects of the overlap regions. However, due to the alignment accuracy of the photolithography process, the length of the top gate portion of the device is generally set to be greater than the length of the back gate portion in the cavity, so as to effectively inhibit the overlapping area of the gate and the source drain region in the cavity, which introduces a non-GAA channel structure with a certain length, and results in that the device cannot sufficiently exhibit the excellent electrical performance specific to the GAA device.
Therefore, it is necessary to provide a fully-around gate device and a method for manufacturing the same to better exploit the advantages of the electrical performance of the device while simplifying the process complexity.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a fully-around gate device and a method for manufacturing the same, for solving the following problems: the gate size in the SOI GAA device process is difficult to define accurately, and a non-ideal channel structure is easy to introduce; full-surrounding gate device technology based on bulk silicon superlattice substrate is only oriented to nodes below 3nm and is difficult to be compatible with conventional CMOS technology nodes.
To achieve the above and other related objects, the present invention provides a fully-round gate device based on a semiconductor-on-insulator substrate, comprising:
a substrate layer;
the insulating layer is positioned on the substrate layer, the upper surface of the insulating layer is formed into a convex insulating structure, and grooves are defined between the insulating structures;
the channel region is spanned above the groove;
the surrounding gate structure comprises a gate dielectric layer and a gate electrode layer which are sequentially formed on the surface surrounding the channel region, wherein the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer also comprises a top gate part which is stacked above the channel region, the back gate part is embedded in the groove, and the central line of the top gate part and the central line of the back gate part are positioned in a plane which is approximately orthogonal to the length direction of the conducting channel; and
The source region and the drain region are respectively connected to two ends of the channel region, are arranged on the insulating layer and are separated from the back gate portion through the insulating structure.
Optionally, the recess does not extend through the insulating layer, and the back gate portion is separated from the substrate layer by an insulating layer therebetween.
Optionally, the top gate portion has a dimension in a length direction of the conductive channel that is not smaller than the recess.
Optionally, a shallow trench isolation structure is further included, the shallow trench isolation structure being located at a side edge of the active region to be separated from an electrode of an adjacent region.
The invention also provides a preparation method of the full-surrounding gate device, which comprises the following steps:
1) Providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a substrate layer, a buried oxide layer and a top semiconductor layer;
2) Patterning the top semiconductor layer to define a channel forming region;
3) Forming a dummy gate structure based on the formed region of the channel, wherein the dummy gate structure comprises a stacked dummy gate dielectric layer and a top dummy gate, and the dummy gate structure further comprises a bottom dummy gate positioned on the buried oxide layer;
4) Selectively etching the dummy gate structure serving as a mask until the side wall of the bottom dummy gate is exposed so that gaps are formed on two sides of the reserved bottom dummy gate, and two ends of a channel region are exposed;
5) Conformally filling an insulating dielectric material in the gap to form an insulating structure, wherein the insulating structure at least covers the side wall of the bottom dummy gate;
6) Forming a source region and a drain region at two ends of the channel region, wherein the source region and the drain region are positioned on the oxygen-buried layer;
7) Forming a passivation layer by covering the dummy gate structure, the source region and the drain region, and performing planarization treatment on the passivation layer to expose the top surface of the dummy gate structure;
8) And removing the dummy gate structure to release the dummy gate trench, forming a full-surrounding gate structure in the dummy gate trench, wherein the full-surrounding gate structure comprises a gate dielectric layer surrounding the surface of a channel region and a gate electrode layer surrounding the surface of the gate dielectric layer, the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer further comprises a top gate part stacked above the channel region, and the back gate part of the gate electrode layer is isolated from the source region and the drain region through the insulating structure.
Optionally, the semiconductor-on-insulator substrate has an embedded cavity at an interface of the buried oxide layer and the top semiconductor layer and disposed so as not to extend through the buried oxide layer.
Optionally, the method further comprises:
further comprises:
2) Patterning the top semiconductor layer to release a suspended channel;
3) Forming the dummy gate structure based on the suspended channel, comprising:
3-1) filling the cavity with a sacrificial dummy gate material to form a bottom dummy gate while forming a stacked dummy gate dielectric layer and sacrificial dummy gate material layer;
3-2) patterning the sacrificial dummy gate material layer to form a top dummy gate, a projection of the top dummy gate onto a floor of the cavity being within the cavity.
Optionally, the semiconductor-on-insulator substrate includes a first buried oxide layer, an intermediate layer, a second buried oxide layer, and a top semiconductor layer sequentially disposed on the substrate layer, wherein a material of the intermediate layer includes a single crystal, a polycrystal, or an amorphous form of one selected from the following materials: si, siGe and Ge.
Optionally, the method further comprises:
3) Forming side walls on two sides of the top dummy gate;
4) And selectively etching the top dummy gate and the side wall serving as a mask until the intermediate layer is exposed, wherein a reserved part of the intermediate layer is formed into a bottom dummy gate.
Optionally, step 5) includes:
5-1) etching back the bottom dummy gate to expand the gap and recess below the channel region to be substantially aligned with sidewalls of the top dummy gate;
5-2) conformally filling the extended gap with an insulating dielectric material, the insulating dielectric material also being formed on a surface of the channel region.
Optionally, the channel region comprises one of a nanowire channel, a nanoplate channel, and a nanoplate channel, wherein step 6) comprises:
6-1) etching by adopting a reactive ion etching process to remove insulating dielectric materials positioned on the side surface of the dummy gate structure and the side surface of the channel region, and exposing opposite end surfaces of the channel region;
6-2) growing source and drain regions from the exposed end surfaces of the channel region.
The invention also provides a preparation method of the full-surrounding gate device, which comprises the following steps:
1) Providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a substrate layer, a buried oxide layer, a back gate dielectric layer and a top semiconductor layer;
2) Patterning the top semiconductor layer to define a channel forming region;
3) Forming a dummy gate structure based on the formed region of the channel, wherein the dummy gate structure comprises a dummy gate dielectric layer and a top dummy gate formed around the dummy gate dielectric layer, and a channel region is defined by the surrounding region of the dummy gate dielectric layer and the back gate dielectric layer;
4) Selectively etching the dummy gate structure as a mask until the side wall of the back gate layer is exposed, so that gaps are formed on two sides of the reserved back gate layer, and two ends of the channel region are exposed;
5) And filling insulating dielectric materials in the gaps in a conformal manner to form insulating structures, wherein the insulating structures at least cover the side walls of the back gate layer.
6) Forming a source region and a drain region based on the channel region, the source region and the drain region being located on the buried oxide layer;
7) Forming a passivation layer by covering the dummy gate structure, the source region and the drain region, and flattening the passivation layer to expose the top surface of the dummy gate structure;
8) And removing the dummy gate structure to release the dummy gate trench, forming a full-surrounding gate structure in the dummy gate trench, wherein the full-surrounding gate structure comprises a gate dielectric layer and a gate electrode layer which surround the surface of the channel region along the extending direction, the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer further comprises a top gate part stacked above the channel region, and the back gate part of the gate electrode layer is isolated from the source region and the drain region through the insulating structure.
Optionally, the back gate layer is located between the back gate dielectric layer and the substrate layer to form a mosaic patterned structure, and the back gate layer has a size not greater than the top dummy gate in the length direction of the conductive channel so that the back gate pattern can be directly used as a sacrificial dummy gate.
As described above, the present invention provides a full surrounding gate device and a method for manufacturing the same, which has the following beneficial effects:
1) According to the full-surrounding gate device, the device layer is arranged on the basis of the semiconductor substrate on the insulator, so that the back gate part and the substrate layer are separated through the insulating layer, and the leakage path in the device is blocked, so that the total dose radiation effect can be effectively inhibited, and the back gate part is isolated from the source drain region through the insulating structure, so that the parasitic capacitance of the back gate part and the source drain region is further reduced;
2) The full-surrounding gate device comprises a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer and the gate electrode layer are surrounded on the surface of a channel region, the central line of the top gate part and the central line of the back gate part are positioned in a plane which is approximately orthogonal to the length direction of a conductive channel, so that the gate electrode layer has good self-alignment precision, a large overlapping area between the back gate part and a source drain region is avoided, parasitic capacitance is reduced, and pi channel structure formed by overlarge top gate is avoided;
3) According to the preparation method of the full-surrounding gate device, the top dummy gate and the side wall are used as masks to be selectively etched until the side wall of the bottom dummy gate is exposed, so that the obtained bottom dummy gate is arranged in a centering mode relative to the middle line of the top dummy gate, and a surrounding gate structure with improved alignment precision can be obtained through the formation of a dummy gate process, the process complexity of preparing the full-surrounding gate transistor is reduced, and further the grid leakage problem is improved.
Drawings
Fig. 1 shows a flow chart of a prior art process for a fully round gate device.
Fig. 2 to 4 show schematic structural diagrams of GAA devices based on vesi substrates.
Fig. 5 is a flow chart showing a method of manufacturing a GAA device based on a semiconductor-on-insulator substrate according to the first embodiment of the present invention.
Fig. 6 to 38 are schematic structural views showing various stages in a manufacturing method of a GAA device based on a semiconductor-on-insulator substrate according to a first embodiment of the present invention.
Fig. 39 is a schematic diagram showing a structure of another example of a semiconductor-on-insulator substrate in accordance with the first embodiment of the present invention.
Fig. 40-41 are partial schematic views of GAA devices based on the semiconductor-on-insulator substrate shown in fig. 40 in accordance with a first embodiment of the present invention.
Fig. 42 is a flow chart showing a method of manufacturing a GAA device based on a semiconductor-on-insulator substrate according to the first embodiment of the present invention.
Fig. 43 is a schematic view showing a structure of a semiconductor-on-insulator substrate in a second embodiment of the invention.
Fig. 44 to 45 are schematic views showing a structure obtained by performing step S260 based on a semiconductor-on-insulator substrate according to the second embodiment of the present invention.
Description of element reference numerals
11. 21, 31 semiconductor-on-insulator substrate
100. Substrate layer
110. 210 first buried oxide layer
220. Intermediate layer
230. A second buried oxide layer
320. Intermediate buried oxide layer
140. 240 top semiconductor layer
112. Cavity cavity
132. Insulation structure
151. False gate dielectric layer
142. Channel formation region
144. 244 channel region
1520. Sacrificial dummy gate material layer
152. Top dummy gate
153. Side wall
121. Bottom dummy gate
147. Source region
148. Drain region
146. Gate electrode layer
145. Gate dielectric layer
1461. Back gate portion
1462. Top gate portion
154. False gate trench
170. Isolation structure
160. Passivation layer
40. Source electrode
50. Drain electrode
S110 to S190, S210 to S290 steps
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure of the present invention. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. For purposes of clarity, components and steps well known to those skilled in the art have been omitted to avoid unnecessarily obscuring the elements of the invention.
In the preparation of a surrounding gate device based on a silicon-on-insulator substrate (VESOI substrate) with embedded cavities, by setting the top gate portion of the device slightly larger than the back gate portion, parasitic capacitance caused by the large overlap region of the back gate portion and the source-drain region can be suppressed. As shown in fig. 2-4, where fig. 3 shows a partial enlargement of the region B1 as indicated in fig. 2, and fig. 4 shows a partial enlargement of the region B2 as indicated in fig. 2, two structures will appear in the channel region in this arrangement: one is a fully surrounding gate structure, i.e., the gate electrode completely encapsulates the channel; the other is a pi channel structure, i.e. the gate electrode wraps three sides of the channel (similar to a FinFET), and the channel opening is usually later than the GAA channel due to the fact that the pi channel structure lacks control of the back gate part, so that the device cannot fully show the excellent electrical performance specific to the GAA device, such as a smaller subthreshold slope, a higher on-state current density and the like.
However, due to the fact that the alignment precision of the photoetching process is limited, a large overlapping area still exists between the surrounding gate structure and the source region and the drain region, the false gate structure is preset up and down through the surrounding channel region, the center lines of the bottom false gate and the top false gate are aligned in the vertical direction, then the gate electrode layer is formed through the false gate process, the self-alignment precision of the subsequently formed surrounding gate structure is improved, meanwhile, the pi channel structure formed due to the fact that the top gate part is too large is avoided, the back gate part is isolated from the source region and the drain region through the insulating structure, and parasitic capacitance of the back gate part and the source drain region is further reduced.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
Moreover, exemplary embodiments are described herein with reference to the accompanying cross-sectional and/or plan views, which are idealized schematic illustrations. Thus, variations in the illustrated shapes of the gate electrode layers resulting from, for example, manufacturing techniques and/or tolerances, are likely to occur, such as by a dummy gate process, with good alignment accuracy, as the center line of the back gate portion and the center line of the top gate portion of the gate electrode layer lie in a plane that is substantially orthogonal to the length of the conductive channel, in which case the term "orthogonal" should be understood to include a range of slight deviations from the orthogonal plane, such as + -0.5 deg. deviations, due to manufacturing techniques, tolerances, and/or other factors. Thus, the illustrative embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
In some embodiments herein, the first conductivity type is one of P-type and N-type doping and the second conductivity type is the other of P-type and N-type doping.
Referring to fig. 5-44, a fully-around gate device based on a semiconductor-on-insulator substrate and a method of fabricating the same will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
Referring to fig. 5 and 6-39, the present embodiment provides a method for manufacturing a full-surrounding gate device based on a semiconductor-on-insulator substrate, the method comprising the steps of:
first, referring to fig. 6 to 8, step S110 is performed to provide a semiconductor-on-insulator substrate including a substrate layer 100, a buried oxide layer 110, and a top semiconductor layer 140.
Specifically, the substrate layer 100 may be selected from a semiconductor material or an insulating material, the buried oxide layer 110 may be selected from silicon dioxide or a similar insulating dielectric material, and the material of the top semiconductor layer 140 may be selected from an unintentionally doped semiconductor material, such as Si, siGe, ge, polysilicon (Poly-Si), amorphous silicon (α -Si); alternatively, the doped semiconductor material is, for example, si, siGe, ge, or other suitable material. In this embodiment, the buried oxide layer 110 is selected to be a silicon dioxide layer, and the top semiconductor layer 140 is selected to be a top silicon layer.
For example, when the semiconductor-on-insulator substrate 11 is used to fabricate a fully-around gate device, the semiconductor-on-insulator substrate 11 has an embedded cavity disposed in at least one of the buried oxide layer 110 and the top semiconductor layer 140 at the interface therebetween, and the cavity may or may not extend through the buried oxide layer 110. The size and position of the cavity can be flexibly adjusted according to the critical dimensions and electrical properties required by the device, and are not particularly limited herein. In this embodiment, the dummy frame shown in fig. 6 indicates the opening position of the cavity 112, and fig. 7 to 8 show side views of the substrate shown in fig. 6 along the sections A-A 'and B-B', where the cavity 112 is disposed in the buried oxide layer 110 adjacent to the interface of the buried oxide layer 110 and the top semiconductor layer 140 and does not penetrate through the buried oxide layer 110.
As an example, referring to fig. 39 to 41, when the semiconductor-on-insulator substrate 21 is used to fabricate a full-around gate device, the semiconductor-on-insulator substrate 21 sequentially includes a substrate layer 100, a first buried oxide layer 210, an intermediate layer 220, a second buried oxide layer 230, and a top semiconductor layer 240, wherein the intermediate layer 220 serves as a bottom dummy gate, and a material of the intermediate layer 220 includes, but is not limited to, a single crystal, a polycrystalline, or an amorphous form of one selected from Si, siGe, and Ge, for example, polysilicon (Poly-Si), amorphous silicon (α -Si). Preferably, the intermediate layer 220 is made of a material different from that of the top semiconductor layer 240, so that the intermediate layer material and the channel region material have different selective etching ratios, which is beneficial to reducing the difficulty of forming the bottom dummy gate by selective etching in the subsequent process.
Then, step S120 is performed, and referring to fig. 9 to 11, the top semiconductor layer is patterned to define a channel formation region 142.
As shown in fig. 9-11, the top semiconductor layer is patterned and the resulting channel forming region 142 is formed as a semiconductor nanowire, nanoplate, or similar semiconductor nanostructure.
When the semiconductor-on-insulator substrate is selected as the semiconductor-on-insulator substrate 11 having the embedded cavity 112, patterning the top semiconductor layer 140 to release the floating channel, wherein the step of releasing the floating channel comprises: forming a hard mask layer over the top semiconductor layer 140; the hard mask layer and the top semiconductor layer 140 are etched sequentially based on a trench mask pattern, the suspended trench straddling over the cavity.
In other examples, when the semiconductor-on-insulator substrate 21 is selected, the top semiconductor layer 240 is patterned to define a channel formation region over the second buried oxide layer 230.
Then, step S130 is performed, referring to fig. 12 to 20, a dummy gate structure is formed based on the channel formation region 142, the dummy gate structure including a stacked dummy gate dielectric layer 151 and top dummy gate 152, and the dummy gate structure further including a bottom dummy gate 121 on the buried oxide layer.
As shown in fig. 12 to 17, at step S130, forming the dummy gate structure based on the floating channel includes: s131, forming a dummy gate dielectric layer 151 around the surface of the suspended channel; s132, forming a sacrificial dummy gate material layer 1520 overlying the dummy gate dielectric layer 151; and S133, patterning the sacrificial dummy gate material layer 1520 to form a top dummy gate 152, wherein a projection of the top dummy gate 132 onto the cavity floor is within the cavity 112.
For example, when the semiconductor-on-insulator substrate 11 is used to manufacture a fully-round gate device, at step S132, a sacrificial dummy gate material layer 1520 is formed overlying the dummy gate dielectric layer 151 with a sacrificial dummy gate material, and the cavity 112 is filled with the sacrificial dummy gate material to form a bottom dummy gate 121; and S133, patterning the sacrificial dummy gate material layer 1520 to form the top dummy gate 152.
In other examples, when the semiconductor-on-insulator substrate 21 is used to fabricate a fully-surrounding gate device, the surrounding area of the dummy gate dielectric layer 152 and the back gate dielectric layer defines a channel region.
As shown in fig. 15 to 17, step S130 further includes: s134, forming side walls 153 on both sides of the top dummy gate 152, for example, by a process known to those skilled in the art The sidewall 153 includes, but is not limited to, a thermal oxidation process by LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, wherein the material of the sidewall includes SiO x 、SiN x And SiN x O y One of the materials of the side wall 153 comprises SiO x 、SiN x And SiN x O y One of them.
As an example, step S133 is performed to cover the dummy gate structure to form a hard mask layer, and etching with a window defined by the hard mask layer as a mask to form a top dummy gate, and then, at step S134, a shallow doped implantation (LDD) process is performed based on the channel region 144 to form a source drain extension region, where a hard mask layer is reserved above the dummy gate structure for passivation protection of the underlying material layer.
By way of example, the material of the dummy gate dielectric layer includes, but is not limited to, insulating dielectric materials commonly used in the art, such as SiO x 、SiN x 、SiN x O y The sacrificial dummy gate material may be selected from polysilicon, amorphous silicon, or the like that is selectively etchable. In this embodiment, the dummy gate dielectric layer 151 is formed by a high density plasma chemical vapor deposition (HDP-CVD) process.
Then, step S140 is performed, referring to fig. 18 to 20, the dummy gate structure is used as a mask to selectively etch until the sidewall of the bottom dummy gate is exposed, so that the two sides of the bottom dummy gate remain to form the gap 122, and two ends of the channel region 144 are exposed.
Specifically, an anisotropic etching process, such as a dry etching process, is performed using the top dummy gate 152 and the sidewall 153 as masks, to define a channel region 144 in the channel forming region 142, and to remove a portion of the bottom dummy gate extending beyond an overlapping region with the top dummy gate, wherein the channel region includes, but is not limited to, a nanowire channel, a nanoplate channel, or a nanoribbon channel.
For example, the anisotropic etching process employs etching gases commonly used in the art, including but not limited to: oxidizing gas and CF 4 、CH 3 F、CHF 3 、CH 2 F 2 、C 4 F 8 、C 4 F 6 One of them or a combination thereof.
As shown in fig. 19, when the semiconductor-on-insulator substrate 11 is used to fabricate a fully-around gate device, the cavity 112 has an orthographic projection extending beyond the top dummy gate 152 and the sidewall 153 on the surface of the buried oxide layer, and a gap 122 is formed between the inner sidewall of the cavity and the remaining bottom dummy gate by removing the portion of the bottom dummy gate extending beyond the overlapping region with the top dummy gate through a selective etching process.
In other examples, as shown in fig. 40 to 41, when the semiconductor-on-insulator substrate 21 is used to fabricate a fully-surrounding gate device, the intermediate layer 220 is used as the bottom dummy gate, the second buried oxide layer 230 is used as a dummy gate dielectric layer, and the isolation structure 170 is formed to isolate the active region before the patterning of the top semiconductor layer 140 is performed in step S120, and a gap is formed between the isolation structure 170 and the remaining bottom dummy gate by removing the bottom dummy gate not covered by the dummy gate structure through a selective etching process.
Then, step S150 is performed, referring to fig. 21 to fig. 26, an insulating dielectric material is conformally filled in the gap 122 to form an insulating structure 132, where the insulating structure 132 covers at least the sidewall of the back gate electrode.
Specifically, step S150 includes: s151, etching back the bottom dummy gate to expand the gap and recess below the channel region to be aligned or substantially aligned with the sidewall of the top dummy gate; and S152, conformally filling an insulating dielectric material in the expanded gaps to form an insulating structure 132, wherein the insulating dielectric material covers the sides of the dummy gate structure and the channel region. Since the insulating structures 132 are formed on both sides of the bottom dummy gate, the bottom dummy gate is separated from other conductive layers formed on both sides thereof in a subsequent process.
As shown in fig. 21 to 23, in step S151, the remaining bottom dummy gate is etched back by using a selective etching or wet etching process. In connection with fig. 19 and 22, since the sacrificial dummy gate material and dummy gate dielectric layer that extend beyond the region overlapping the top dummy gate are removed at step 140, the remaining portion of the bottom dummy gate is centered with respect to the center line of the top dummy gate 152, and the sidewalls of the bottom dummy gate resulting from step S151 may be aligned or substantially aligned with the sidewalls of the top dummy gate by adjusting the depth of the bottom dummy gate, i.e., the recess depth below the channel region, that is etched back. The term "alignment" as used herein is understood to include slight deviations of the machined surface from a precise alignment position within process tolerances.
As shown in fig. 21 to 23, at step S151, the bottom dummy gate remaining by the selective etching or wet etching process is etched back, wherein the bottom dummy gate and the channel region may be made of different materials, including, but not limited to, si, siGe, ge, poly-Si, or α -Si, respectively. For example, when the sacrificial dummy gate material is selected to be polysilicon or amorphous silicon, and the top semiconductor layer is selected to be a top silicon layer, the step of etching back the bottom dummy gate sidewall is performed by using TMAH solution.
By way of example, the insulating dielectric material is deposited by a high step coverage process, which may be selected, for example, as an Atomic Layer Deposition (ALD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, or the like, that conformally fills the extended gaps and is also formed on the sides of the dummy gate structure and the channel region.
Then, step S160 is performed, referring to fig. 27 to 29, a source region 147 and a drain region 148 are formed based on the channel region 144, the source region 147 and the drain region 148 being located on the buried oxide layer 110.
Specifically, as shown in fig. 24 to 29, in step S160, the insulating dielectric material layer located on the side surface of the dummy gate structure and the side surface of the channel region is anisotropically etched to expose the opposite end surfaces of the channel region, for example, a step of removing the insulating dielectric material by using an anisotropic reactive ion etching process; subsequently, a source region 147 and a drain region 148 are grown from the end surfaces exposed from the channel region.
For example, source-drain epitaxy processes are performed on the exposed end surfaces of the channel region 144, such as by metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective Epitaxial Growth (SEG), the like, or a combination of the foregoing, respectively; subsequently, the source region 147 and the drain region 148 are formed by a doping process. The materials used to epitaxially grow source region 147 and drain region 148 may be flexibly adjusted to the device performance requirements and selected, for example, to be compound semiconductor material SiP, siC, siGe, or other suitable materials. Alternatively, the epitaxial material may be co-doped simultaneously with the epitaxial growth of the source 147 and drain 148 regions.
Referring to fig. 28A-28C, which illustrate several aspects of forming an insulating structure on both sides of the bottom dummy gate, the insulating structure 132 may be formed as an L-shaped sidewall or a vertical sidewall on both sides of the back gate electrode, and the source region 40 and the drain region 50 are supported on the insulating structure 132 or the first buried oxide layer 110, respectively.
In this embodiment, step 160 further includes: depositing a layer of metal, such as W, co, ni, etc., on the substrate over the device structure; after annealing, a self-aligned metal silicide 410 is formed in the source region 147 and the drain region 148, such that the source region 147 and the drain region 148 form a metal contact.
Then, step S170 is performed, referring to fig. 30 to 32, a passivation layer 160 is formed to cover the dummy gate structure, the source region 147 and the drain region 148, and the passivation layer 160 is planarized to expose the top surface of the dummy gate structure.
Specifically, the passivation layer 160 is formed to entirely cover the surface of the device structure including the dummy gate structure, and then the surface of the passivation layer 160 is planarized to remove the hard mask layer on the top surface of the top dummy gate to expose the top surface of the top dummy gate 152.
The surface of the device covered with the passivation layer 160 is polished and thinned, for example, by a CMP process or the like, to reveal the top surface of the top dummy gate 152.
Then, step S180 is performed, referring to fig. 33 to 38, the dummy gate structure is removed to release the dummy gate trench 154, and a fully-surrounding gate structure is formed in the dummy gate trench, wherein the fully-surrounding gate structure includes a gate dielectric layer 145 surrounding the surface of the channel region and a gate electrode layer 146, the gate electrode layer 146 extends into a recess between the insulating structures to form a back gate portion 1461 located under the channel region, and the gate electrode layer 146 further includes a top gate portion 1462 stacked over the channel region.
Particularly, since the sidewall of the bottom dummy gate obtained in the step S150 is aligned or substantially aligned with the sidewall of the top dummy gate, the dummy gate trench is defined by the dummy gate process, so that the formed surrounding gate structure has better self-alignment accuracy, a larger overlapping area between the back gate portion and the source drain region is avoided, and the parasitic capacitance of the gate drain is reduced.
For example, in step S180, the selective etching process is performed using a fluorocarbon-based etching gas, and the etching rate of etching the silicon oxide based material with respect to the silicon nitride based material is controlled by the ratio of carbon to fluorine in the fluorocarbon-based etching gas so as to preserve the side walls located at both sides of the top dummy gate.
As an example, the gate dielectric layer 145 is deposited by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, atomic Layer Deposition (ALD), or the like, and the gate electrode layer 146 is formed by a Chemical Vapor Deposition (CVD) or physical vapor deposition process.
As shown in fig. 33 to 35, the back gate portion 1461 is isolated from the source region 147 and the drain region 148 by the insulating structure 132, thereby further reducing parasitic capacitance between the back gate portion and the source drain region.
Then, step S190 is performed, and with continued reference to fig. 36 to 38, a source electrode 40 is formed in the source region 147, and a drain electrode 50 is formed in the drain region 148.
Specifically, at step S190, an interlayer dielectric layer is covered on the structure obtained in step S180, contact vias are formed above the source region and the drain region, and good metal contacts are formed on the contact vias and the exposed gate electrode layer surface.
Example two
The embodiment provides a method for manufacturing a full-surrounding gate device, which adopts substantially the same technical scheme as the first embodiment, and is different from the first embodiment in step S210 of manufacturing the semiconductor-on-insulator substrate.
Specifically, the step S210 of fabricating the semiconductor-on-insulator substrate 31 includes:
s211: providing a substrate layer, and forming a first insulating layer on the surface of the substrate layer;
s212: forming a groove in the first insulating layer, wherein the groove penetrates or does not penetrate through the first insulating layer;
s213: forming an intermediate layer filling at least the groove, wherein a part of the intermediate layer embedded in the groove serves as a back gate layer;
s214: providing a base, wherein the base comprises a supporting substrate and a second insulating layer, and bonding the base with the surface of the second insulating layer facing the intermediate layer, wherein the second insulating layer is used as a back gate dielectric layer of the semiconductor-on-insulator substrate;
S215: the semiconductor layer is thinned to obtain a top semiconductor layer.
Specifically, the material of the first insulating layer includes silicon dioxide or other suitable dielectric materials, the method for forming the first insulating layer includes chemical vapor deposition, physical vapor deposition or other suitable methods, and the material of the intermediate layer includes, but is not limited to, single crystal, polycrystal or amorphous form of one of the following materials: si, siGe and Ge.
Specifically, the method for forming the grooves includes dry etching, wet etching or other suitable methods, and the cross-sectional shape and size of the grooves can be flexibly adjusted according to the critical dimensions of the device and the flow sheet process flow, which is not particularly limited herein.
By way of example, the intermediate layer is at least filled in the groove, and a second buried oxide layer is arranged between the top surface of the intermediate layer and the top semiconductor layer, so that the intermediate layer can directly serve as a back gate when the device is formed by using the SOI substrate later, and the back gate and the top gate can be connected to form the GAA device, thereby widening the application types of the device.
As an example, when the intermediate layer is formed to protrude from the first insulating layer, step S213 further includes thinning a portion of the intermediate layer protruding from the groove.
In this embodiment, the recess is formed so as not to penetrate through the first oxygen-buried layer 210, the intermediate layer is filled in the recess, and when the GAA device is formed by using the semiconductor-on-insulator substrate later, the intermediate layer 322 serves as a back gate layer, and the back gate layer is located between the back gate dielectric layer and the substrate layer, so as to form a inlaid patterned structure.
Specifically, as shown in fig. 43, the exposed top surface of the intermediate layer and the surface of the first oxygen-buried layer are used as bonding interfaces to bond with the substrate, so that bonding quality is improved, and the requirement on the thickness of the oxygen-buried layer in the process of preparing the semiconductor-on-insulator substrate is reduced due to the arrangement of the intermediate layer, and the difficulty of a bonding process is greatly reduced.
By way of example, methods of thinning the substrate include chemical mechanical polishing, hydrogen ion stripping, or other suitable methods. In this embodiment, the method of thinning the substrate is chemical mechanical polishing.
In a specific embodiment, referring to fig. 42 and 44 to 45, the method for manufacturing the fully-surrounding gate device includes:
s210, providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a substrate layer, a buried oxide layer, a back gate dielectric layer and a top semiconductor layer;
S220, patterning the top semiconductor layer to define a channel forming region;
s230, forming a dummy gate structure based on the formation region of the channel, wherein the dummy gate structure comprises a dummy gate dielectric layer and a top dummy gate formed around the dummy gate dielectric layer, and a channel region is defined by the surrounding region of the dummy gate dielectric layer and the back gate dielectric layer;
s240, selectively etching the dummy gate structure as a mask until the side wall of the back gate layer is exposed, so that gaps are formed on two sides of the reserved back gate layer, and two ends of the channel region are exposed;
s250, filling insulating medium materials in the gaps in a conformal mode to form insulating structures, wherein the insulating structures at least cover the side walls of the back gate layer;
s260, forming a source region and a drain region based on the channel region, wherein the source region and the drain region are positioned above the oxygen-buried layer;
s270, forming a passivation layer by covering the buried oxide layer, the source region and the drain region, and flattening the passivation layer to expose the top surface of the dummy gate structure;
s280, removing the dummy gate structure to release the dummy gate trench, forming a full-surrounding gate structure in the dummy gate trench, wherein the full-surrounding gate structure comprises a gate dielectric layer and a gate electrode layer which surround the surface of the channel region along the extending direction, the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer also comprises a top gate part stacked above the channel region, and the back gate part of the gate electrode layer is isolated from the source region and the drain region through the insulating structure;
S290, forming a source electrode in the source region and forming a drain electrode in the drain region.
As shown in fig. 44, the semiconductor-on-insulator substrate 31 includes a substrate layer 100, a first oxygen-buried layer 210, a back gate layer 332, a second oxygen-buried layer 230 and a top semiconductor layer 240, wherein the back gate layer 332 is located between the back gate dielectric layer and the first oxygen-buried layer to form a patterned structure, and the back gate layer 332 may be disposed to be embedded in the middle oxygen-buried layer 320. In other examples, the back gate layer may also be formed embedded in an integral insulating layer and isolated from the substrate layer by a bottom insulating layer.
In this embodiment, when the back gate layer 322 is customized to have a dimension greater than that of the top dummy gate 152 in the length direction of the conductive channel, step S240 is performed to selectively etch the dummy gate structure as a mask until the sidewall of the back gate layer is exposed, and the second buried oxide layer remaining below the channel region is used as a back gate dielectric layer. In other examples, the back gate layer 322 is sized to be no greater than the top dummy gate 152 in the length direction of the conductive channel so that the back gate layer directly acts as a bottom dummy gate.
The manufacturing method of the semiconductor-on-insulator substrate embedded with the back gate layer is applicable to wafer-level preparation, can be customized according to the needs to realize large-scale production, and is beneficial to simplifying the manufacturing method of the surrounding gate field effect transistor and reducing the production cost.
Example III
The embodiment provides a fully-surrounding gate device based on a semiconductor-on-insulator substrate, wherein the fully-surrounding gate device is preferably prepared by the preparation method described in the previous embodiment, and other methods can be adopted.
As shown in fig. 37 to 38, the semiconductor-on-insulator substrate includes a substrate layer 100, an insulating layer, a channel region, a surrounding gate structure, the source region 147 and the drain region 148, wherein the insulating layer is located on the substrate layer 100, the upper surface of the insulating layer is formed as a protruding insulating structure 132, and a groove is defined between the insulating structures 132; the channel region is spanned above the groove; the surrounding gate structure comprises a gate dielectric layer 145 and a gate electrode layer 146 which are formed on the surface surrounding the channel region in sequence; the source region 147 and the drain region 148 are connected to both ends of the channel region, wherein the gate electrode layer 146 extends into the recess to form a back gate portion 1461 located below the channel region, the gate electrode layer 146 further comprising a top gate portion 1462 stacked above the channel region, the back gate portion 1461 being embedded in the recess 132, a center line of the top gate portion and a center line of the back gate portion lying in a plane substantially orthogonal to a length direction of the conductive channel; the source region 147 and the drain region 148 are disposed on the insulating layer and are isolated from the back gate portion 1461 by the insulating structure 132, further reducing parasitic capacitance of the back gate portion and the source drain region.
Specifically, the substrate layer 100 may be a semiconductor material or an insulating material, and the material of the top semiconductor layer 140 may be selected from an unintentionally doped semiconductor material, such as Si, siGe, ge, polysilicon (Poly-Si), amorphous silicon (α -Si); alternatively, the doped semiconductor material is, for example, si, siGe, ge, or other suitable material.
For example, the channel region includes, but is not limited to, a nanowire channel, a nanoplate channel, or a nanoribbon channel.
As an example, the insulating layer is selected as an oxygen buried layer, the grooves do not penetrate through the insulating layer, the back gate portion and the substrate layer are separated by the insulating layer between the back gate portion and the substrate layer, and the insulating performance of the device is improved while the total dose effect is reduced. In this embodiment, the insulating layer is selected to be a silicon dioxide layer, and the top semiconductor layer 140 is selected to be a top silicon layer.
As an example, the top gate portion 1462 has a size not smaller than the recess in the length direction of the conductive channel.
As an example, an isolation structure 170 is further included, the isolation structure 170 being disposed at a side edge of the active area region to be isolated from an electrode structure where an adjacent region may exist, such as a Shallow Trench Isolation (STI) structure.
In summary, the full-surrounding gate device based on the semiconductor-on-insulator substrate and the preparation method thereof have the following beneficial effects:
1) The full-surrounding gate device comprises a gate dielectric layer and a gate electrode layer which are surrounded in a channel region, wherein the gate electrode layer has good self-alignment precision, so that the central line of the top gate part and the central line of the back gate part are in the same plane which is approximately orthogonal with the length direction of a conductive channel, the gate electrode layer has good self-alignment precision, thereby avoiding a large overlapping region between the back gate part and a source drain region, reducing parasitic capacitance and avoiding the formation of a pi channel structure due to overlarge top gate;
2) According to the full-surrounding gate device, the device layer is arranged on the basis of the semiconductor substrate on the insulator, so that the back gate part and the substrate layer are separated through the insulating layer, and the leakage path in the device is blocked, so that the total dose radiation effect can be effectively inhibited, and the back gate part is isolated from the source drain region through the insulating structure, so that the parasitic capacitance of the back gate part and the source drain region is further reduced;
3) According to the preparation method of the full-surrounding gate device, the top dummy gate and the side wall are used as masks to be selectively etched until the side wall of the bottom dummy gate is exposed, so that the obtained bottom dummy gate is arranged in a centering mode relative to the middle line of the top dummy gate, and a surrounding gate structure with improved alignment precision can be obtained through the formation of a dummy gate process, the process complexity of preparing the full-surrounding gate transistor is reduced, and therefore the problem of gate leakage is solved.
4) The preparation method of the full-surrounding gate device can be applied to advanced process node devices, can also be used for upgrading the performance of mature process nodes, and has good process suitability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A fully-around gate device based on a semiconductor-on-insulator substrate, comprising:
a substrate layer;
the insulating layer is positioned on the substrate layer, the upper surface of the insulating layer is formed into a convex insulating structure, and grooves are defined between the insulating structures;
the channel region is spanned above the groove;
the surrounding gate structure comprises a gate dielectric layer and a gate electrode layer which are sequentially formed on the surface surrounding the channel region, wherein the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer also comprises a top gate part which is stacked above the channel region, the back gate part is embedded in the groove, and the central line of the top gate part and the central line of the back gate part are positioned in a plane which is approximately orthogonal to the length direction of the conducting channel; and
The source region and the drain region are respectively connected to two ends of the channel region, are arranged on the insulating layer and are separated from the back gate portion through the insulating structure.
2. The fully-round gate device of claim 1, wherein: the recess does not extend through the insulating layer, the back gate portion and the substrate layer being separated by an insulating layer therebetween.
3. The fully-round gate device of claim 1, wherein: the top gate portion has a dimension in a length direction of the conductive channel that is not smaller than the recess.
4. The fully-round gate device of claim 1, wherein: the shallow trench isolation structure is positioned at the side edge of the active region so as to be separated from the electrode of the adjacent region.
5. A method of fabricating a fully-around gate device, comprising:
1) Providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a substrate layer, a buried oxide layer and a top semiconductor layer;
2) Patterning the top semiconductor layer to define a channel forming region;
3) Forming a dummy gate structure based on the formed region of the channel, wherein the dummy gate structure comprises a stacked dummy gate dielectric layer and a top dummy gate, and the dummy gate structure further comprises a bottom dummy gate positioned on the buried oxide layer;
4) Selectively etching the dummy gate structure serving as a mask until the side wall of the bottom dummy gate is exposed so that gaps are formed on two sides of the reserved bottom dummy gate, and two ends of a channel region are exposed;
5) Conformally filling an insulating dielectric material in the gap to form an insulating structure, wherein the insulating structure at least covers the side wall of the bottom dummy gate;
6) Forming a source region and a drain region at two ends of the channel region, wherein the source region and the drain region are positioned on the oxygen-buried layer;
7) Forming a passivation layer by covering the dummy gate structure, the source region and the drain region, and performing planarization treatment on the passivation layer to expose the top surface of the dummy gate structure;
8) And removing the dummy gate structure to release the dummy gate trench, forming a full-surrounding gate structure in the dummy gate trench, wherein the full-surrounding gate structure comprises a gate dielectric layer surrounding the surface of a channel region and a gate electrode layer surrounding the surface of the gate dielectric layer, the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer further comprises a top gate part stacked above the channel region, and the back gate part of the gate electrode layer is isolated from the source region and the drain region through the insulating structure.
6. The method for manufacturing a fully-round gate device according to claim 5, wherein: the semiconductor-on-insulator substrate has an embedded cavity at an interface of the buried oxide layer and the top semiconductor layer and disposed so as not to extend through the buried oxide layer.
7. The method of manufacturing a fully-round gate device of claim 6, further comprising:
2) Patterning the top semiconductor layer to release a suspended channel;
3) Forming the dummy gate structure based on the suspended channel, comprising:
3-1) filling the cavity with a sacrificial dummy gate material to form a bottom dummy gate while forming a stacked dummy gate dielectric layer and sacrificial dummy gate material layer;
3-2) patterning the sacrificial dummy gate material layer to form a top dummy gate, a projection of the top dummy gate onto a floor of the cavity being within the cavity.
8. The method of claim 5, wherein the semiconductor-on-insulator substrate comprises a first buried oxide layer, an intermediate layer, a second buried oxide layer, and a top semiconductor layer disposed in that order on the substrate layer, wherein the intermediate layer comprises a material comprising a single crystal, a polycrystalline, or an amorphous form selected from one of the following materials: si, siGe and Ge.
9. The method of manufacturing a fully-round gate device of claim 5, further comprising:
3) Forming side walls on two sides of the top dummy gate;
4) And selectively etching the top dummy gate and the side wall serving as a mask until the intermediate layer is exposed, wherein a reserved part of the intermediate layer is formed into a bottom dummy gate.
10. The method of manufacturing a fully-round gate device of claim 5, wherein step 5) comprises:
5-1) etching back the bottom dummy gate to expand the gap and recess below the channel region to be substantially aligned with sidewalls of the top dummy gate;
5-2) conformally filling the extended gap with an insulating dielectric material, the insulating dielectric material also being formed on a surface of the channel region.
11. The method for manufacturing a fully-round gate device according to claim 10, wherein: the channel region comprises one of a nanowire channel, a nanoplate channel, and a nanoplate channel, wherein step 6) comprises:
6-1) etching by adopting a reactive ion etching process to remove insulating dielectric materials positioned on the side surface of the dummy gate structure and the side surface of the channel region, and exposing opposite end surfaces of the channel region;
6-2) growing source and drain regions from the exposed end surfaces of the channel region.
12. The preparation method of the full-surrounding gate device is characterized by comprising the following steps:
1) Providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a substrate layer, a buried oxide layer, a back gate dielectric layer and a top semiconductor layer;
2) Patterning the top semiconductor layer to define a channel forming region;
3) Forming a dummy gate structure based on the formed region of the channel, wherein the dummy gate structure comprises a dummy gate dielectric layer and a top dummy gate formed around the dummy gate dielectric layer, and a channel region is defined by the surrounding region of the dummy gate dielectric layer and the back gate dielectric layer;
4) Selectively etching the dummy gate structure as a mask until the side wall of the back gate layer is exposed, so that gaps are formed on two sides of the reserved back gate layer, and two ends of the channel region are exposed;
5) And filling insulating dielectric materials in the gaps in a conformal manner to form insulating structures, wherein the insulating structures at least cover the side walls of the back gate layer.
6) Forming a source region and a drain region based on the channel region, the source region and the drain region being located on the buried oxide layer;
7) Forming a passivation layer by covering the dummy gate structure, the source region and the drain region, and flattening the passivation layer to expose the top surface of the dummy gate structure;
8) And removing the dummy gate structure to release the dummy gate trench, forming a full-surrounding gate structure in the dummy gate trench, wherein the full-surrounding gate structure comprises a gate dielectric layer and a gate electrode layer which surround the surface of the channel region along the extending direction, the gate electrode layer extends into the groove to form a back gate part positioned below the channel region, the gate electrode layer further comprises a top gate part stacked above the channel region, and the back gate part of the gate electrode layer is isolated from the source region and the drain region through the insulating structure.
13. The method for manufacturing a fully-round gate device according to claim 12, wherein: the back gate layer is positioned between the back gate dielectric layer and the substrate layer to form a mosaic patterned structure, and the back gate layer has a dimension which is not larger than the dimension of the top dummy gate in the length direction of the conducting channel so that the back gate pattern can be directly used as a sacrificial dummy gate.
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