KR0156125B1 - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR0156125B1 KR0156125B1 KR1019940033461A KR19940033461A KR0156125B1 KR 0156125 B1 KR0156125 B1 KR 0156125B1 KR 1019940033461 A KR1019940033461 A KR 1019940033461A KR 19940033461 A KR19940033461 A KR 19940033461A KR 0156125 B1 KR0156125 B1 KR 0156125B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
Abstract
본 발명은 바이폴라 옥사이드 아이솔레이션(Bipolar Oxide Isolation) 공정에 관한것으로, 특히 ELO(Epitaxial Lateral Overgrowth)공정을 이용해 두단계산화를 행하므로써 완벽한 디바이스 아이솔레이션(Device Isolation)을 추구하고 액티브(acti-ve)깊이(depth)가 줄어드는 것을 방지하여 안정된 디바이스 특성을 갖도록 한 반도체 제조방법에 관한 것이다.The present invention relates to a bipolar oxide isolation (Bipolar Oxide Isolation) process, in particular to achieve a perfect device isolation (acti-ve) depth by performing two-step oxidation using an epitaxial lateral overgrowth (ELO) process The present invention relates to a semiconductor manufacturing method which has a stable device characteristic by preventing a decrease in depth.
본 발명의 목적을 달성하기 위하여 제1도전형 기판상에 선택적으로 이온주입하여 고농도 제2도전형 불순물영역을 형성하는 제1공정과, 상기 고농도 제2도전형 불순물영역 양측의 기판에 소자영역격리용 제1열산화막을 형성하는 제2공정과, 상기 기판 전면에 저농도 제2도전형 에피택셜층을 형성하는 제3공정과, 상기 고농도 제1도전형 불순물영역 상측을 제외한 부분의 상기 저농도 제2도전형 에피택셜층을 상기 제1열산화막이 노출되지 않도록 선택 식긱하는 제4공정과, 상기 식각된 부분의 저농도 제2도전형 에피택셜층을 열산화하여 제2열산화막을 형성하는 제5공정을 포함하여 이루어짐을 특징으로 한다.In order to achieve the object of the present invention, a first step of selectively implanting ions onto a first conductive substrate to form a high concentration second conductive impurity region, and isolation of device regions on the substrates on both sides of the high concentration second conductive impurity region A second step of forming a first thermal oxide film for forming the first thermal oxide film, a third step of forming a low concentration second conductive epitaxial layer on the entire surface of the substrate, and a second low concentration of a portion except the upper portion of the high concentration first conductive type impurity region A fourth step of selectively etching a conductive epitaxial layer so that the first thermal oxide layer is not exposed, and a fifth step of thermally oxidizing the low concentration second conductive epitaxial layer of the etched portion to form a second thermal oxide layer Characterized in that comprises a.
Description
제1도는 종래의 바이폴라 옥사이드 아이솔레이션 공정단면도.1 is a cross-sectional view of a conventional bipolar oxide isolation process.
제2도는 본 발명의 바이폴라 옥사이드 아이솔레이션 공정 단면도.2 is a cross-sectional view of the bipolar oxide isolation process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 기판 22, 24 : 제1, 제2절연막21 substrate 22, 24 first and second insulating films
23a : N+불순물확산영역 23b : N형 매립층23a: N + impurity diffusion region 23b: N type buried layer
25 : N형 에피택시층 26 : 옥사이드 아이솔레이션25: N-type epitaxy layer 26: oxide isolation
본 발명은 바이폴라 옥사이드 아이솔레이션(Bipolar Oxide Isolation) 공정에 관한 것으로, 특히 ELO(Epitaxial Lateral Overgrowth : 이하 ELO라 약칭함) 공정을 이용해 두단계산화(Two-Step Oxidation)를 행함으로써 완벽한 디바이스 아이솔레이션(device isolation)을 추구하고 액티브 깊이(active depth)가 줄어드는 것을 방지하여 안정된 디바이스(device)특성을 갖도록 한 반도체 소자 제조방법에 관한 것이다.The present invention relates to a bipolar oxide isolation (Bipolar Oxide Isolation) process, and in particular, complete device isolation by performing two-step oxidation using an ELO (Epitaxial Lateral Overgrowth) process. The present invention relates to a method of manufacturing a semiconductor device, which has stable device characteristics by preventing the decrease in active depth.
종래의 바이폴라 옥사이드 아이솔레이션 제조방법은 첨부된 도면을 참조하여 설명하면 다음과 같다.Conventional bipolar oxide isolation manufacturing method is described with reference to the accompanying drawings as follows.
제1도는 종래의 바이폴라 옥사이드 아이솔레이션 제조공정단면도로써, 제1도(a)에서와 같이 p형 기판(1)상에 제1절연막(2)을 형성하고, 상기 제1절연막(2)상에 노광 및 식각공정으로 불순물 확산영역을 선택적으로 정의한 후 상기 정의된 불순물확산영역에 고농도(N+) 불순물 이온주입하여 N형 불순물영역(3)을 형성한다.FIG. 1 is a cross-sectional view of a conventional bipolar oxide isolation manufacturing process, in which a first insulating film 2 is formed on a p-type substrate 1 and exposed on the first insulating film 2 as shown in FIG. And selectively defining an impurity diffusion region by an etching process, and then implanting a high concentration (N + ) impurity ion into the impurity diffusion region to form an N-type impurity region 3.
이어서 제1도(b)에서와 같이 상기 제1절연막을 제거한 뒤 저농도 N형 에피택시(N-type Ep-itaxy : 이하 N-Epi라 약칭함)층(4)을 성장시킨다.Subsequently, as shown in FIG. 1 (b), the first insulating layer is removed, and then a low concentration N-type epitaxy (N-type Ep-itaxy: hereinafter referred to as N-Epi) layer 4 is grown.
이때 N형 매립층(N-type Buried Layer : 이하 NBL이라 약칭함)(5)이 형성된다.At this time, an N-type buried layer (hereinafter abbreviated as NBL) 5 is formed.
제1도(c)에서와 같이 상기 N형 에피택시(4)상에 제2절연막(산화막 : SiO2)(6) 및 제3절연막(질화막 : SiN4)(7)을 차례로 증착하고, 상기 전면에 노광 및 식각공정으로 아이솔레이션이 형성될 영역을 정의한 뒤 제1도(d)에서와 같이 상기 전면에 열산화(thermal oxidation)를 실시하고, 제3절연막(7a)을 제거하여 제1도(e)에서와 같이 옥사이드 아이솔레이션(8)된다. 제1도 (e)를 상세히 설명하면 다음과 같다.As shown in FIG. 1C, a second insulating film (oxide film: SiO 2 ) 6 and a third insulating film (nitride film: SiN 4 ) 7 are sequentially deposited on the N-type epitaxy 4 , and After defining the area where the isolation is to be formed by the exposure and etching processes on the entire surface, thermal oxidation is performed on the entire surface as shown in FIG. 1 (d), and the third insulating layer 7a is removed to remove the first layer ( oxide is isolated 8 as in e). Referring to Figure 1 (e) in detail as follows.
NBL이 옥사이드 아이솔레이션(oxide isolation)에 맞닿음으로써(점선표시) 액티브(active) A와 B가 완전히 아이솔레이션된다.The active A and B are completely isolated by the NBL's contact with oxide isolation (dotted line).
이때 NBL의 깊이(depth)가 4㎛ 정도이므로 제1도(d)에서 사이드 디프젼팩터(side diffusion factor : depth * 0.8)로 인하여 사이드 디프젼됨으로써 액티브 A의 NBL과 액티브 B의 NBL이 서로 가깝게 접하게 됨으로써 완전한 아이솔레이션을 구현하기 힘들다.At this time, since the depth of the NBL is about 4 μm, the side diffraction is caused by the side diffusion factor (depth * 0.8) in FIG. This makes it difficult to achieve full isolation.
이를 방지하기 위해 NBL의 사이드 디프젼을 고려하여 NBL을 아이솔레이션 안쪽으로 정의(define)하여 프로세스(process)한다.To prevent this, the NBL is defined inside the isolation process in consideration of the side deflection of the NBL.
이때 예를 들면 NBL 깊이가 충분하지 않거나, 열산화(thermal oxidation) 두께가 충분하지 않을 경우 실선표시처럼 디바이스 A와 B간의 아이솔레이션은 일어나지 않는다.In this case, for example, when the NBL depth is not sufficient or the thermal oxidation thickness is not sufficient, the isolation between the devices A and B does not occur like the solid line display.
따라서 디바이스와 다바이스 특성상 문제점을 초래하고, 또 NBL 사이드디프젼을 고려하지 않는다면 NBL 사이드 디프젼 때문에 완전히 아이솔레이션을 위하여 넓은 디자인 룰(design rule)을 가져야 하므로 칩(chip)면적이 넓어지는 문제점이 있다.Therefore, if the device and device characteristics are problematic, and if the NBL side deflection is not considered, the NBL side deflection must have a wide design rule for complete isolation, thereby increasing the chip area.
마지막으로 열산화(thermal oxidation)를 한번에 실시함으로써 산화(oxidation)진행과 동시에 NBL-UP되는 양이 크므로 디바이스 항복(device breakdown)특성이 나빠지는 문제점이 있다.Finally, since the amount of NBL-UP is increased at the same time as the oxidation is progressed by performing thermal oxidation at a time, the device breakdown characteristic is deteriorated.
본 발명은 이와 같은 종래 기술의 문제점을 해결하기 위해 안출된 것으로, ELO 공정을 이용해 두단계산화(Two-Step Oxidation)를 행함으로써 완벽한 디바이스 아이솔레이션을 추구하고 액티브 깊이가 줄어드는 것을 방지하여 안정된 디바이스 특성을 갖도록 하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and seeks perfect device isolation by performing two-step oxidation using an ELO process and prevents the active depth from being reduced, thereby achieving stable device characteristics. Its purpose is to have it.
상기 목적을 달성하기 위한 본 발명의 바이폴라 옥사이드 아이솔레이션공정을 제2도에서와 같이 상세히 설명하면 다음과 같다.Referring to the bipolar oxide isolation process of the present invention for achieving the above object in detail as shown in FIG.
제2도(a)에서와 같이 p형 기판(21)상에 제1절연막(22)을 형성하여 상기 제1절연막(22)을 노광 및 식각 공정으로 불순물 확산영역을 선택적으로 정의한 후 상기 정의된 불순물확산영역에 고농도(N+) 불순물을 이온주입하여 N+형 불순물확산영역(23a)을 형성한다.As shown in FIG. 2A, a first insulating layer 22 is formed on the p-type substrate 21 to selectively define the impurity diffusion region by exposing and etching the first insulating layer 22. High concentration (N + ) impurities are implanted into the impurity diffusion region to form an N + type impurity diffusion region 23a.
이어서 제2도(b)에서와 같이 제1질화막을 제거한 뒤 전면에 제2절연막(산화막 : SiO2) 및 제3절연막(질화막 : SiN4)을 차례로 증착한다.Subsequently, as illustrated in FIG. 2B, the first nitride film is removed, and then a second insulating film (oxide SiO 2 ) and a third insulating film (nitride film SiN 4 ) are sequentially deposited on the entire surface.
상기 전면에 노광 및 식각 공정으로 제1아이솔레이션이 형성될 영역을 정의한 뒤 제1열산화를 실시한다.The first thermal oxidation is performed after defining a region where the first isolation is to be formed by an exposure and etching process on the entire surface.
이때 제2절연막은 NBL 사이드 디프젼을 막는 브로킹(blocking) 제2절연막(24)으로 형성하고, 또 N형 매립층(N-type Buried Layer)(23b)이 형성된다.In this case, the second insulating layer is formed of a blocking second insulating layer 24 that prevents the NBL side difference, and an N-type buried layer 23b is formed.
제2도(c)에서와 같이 제3절연막을 제거한 뒤 상기 전면에 ELO(Epitaxial Lateral Overgrowth)공정을 이용하여 저농도 N-Epi층(N-type Epitaxy Layer)(24)을 성장(g-rowing)시킨다.After removing the third insulating layer as shown in FIG. 2 (c), a low concentration N-type epitaxy layer 24 is g-rowed by using an epitaxial lateral overgrowth (ELO) process. Let's do it.
이때 N-Epi 성장 메카니즘(mechanism)을 살펴보면, 옥사이드(oxide) 위에는 N-Epi가 성장하지 않으면서 위로만 성장하다가 래터럴(lateral)방향으로 오버그로쓰(overg-rowth)되면서 제2도(d)에서와 같이 N-Epi층 합체(coalescence)(25)가 된다.At this time, the N-Epi growth mechanism (mechanism), N-Epi does not grow on the oxide (oxide) only grows up and grows in the lateral direction (overg-rowth) in the second degree (d) As in N-Epi layer coalescing (coalescence) (25).
상기 합체가 된 전면을 제2도(e)에서와 같이 N-Epi층 평탄화(25)를 행하여, 제2도(f)에서와 같이 상기 평탄화된 전면에 제4절연막(산화막 : SiO2) 및 제5절연막(질화막 : SiN4)을 차례로 증착한다.The N-Epi layer is planarized 25 as shown in FIG. 2 (e), and the fourth insulating film (oxide film: SiO 2 ) is formed on the planarized front surface as shown in FIG. A fifth insulating film (nitride film: SiN 4 ) is deposited in sequence.
그리고, 상기 제4절연막과 제5절연막을 상기 N형 매립층(23b) 상측에만 남도록 즉 격리영역에만 제거되도록 선택 사진 식각 공정 한 후에, 상기 제5절연막을 마스크로 상기 N-Epi층(25)을 상기 브르킹 제2절연막(24)이 노출되지 않도록 선택 식각한다.After the selective etching process is performed such that the fourth insulating layer and the fifth insulating layer remain only above the N-type buried layer 23b, that is, removed only in the isolation region, the N-Epi layer 25 is formed using the fifth insulating layer as a mask. Selective etching is performed so that the breaking second insulating layer 24 is not exposed.
그 후, 제2도(g)에서와 같이 상기 전면에 제2열산화를 실시하여 제1아이솔레이션과 맞닿음으로써 옥사이드 아이솔레이션(oxide isolation)(26)을 형성한다.Thereafter, as shown in FIG. 2 (g), second thermal oxidation is performed on the entire surface to contact the first isolation to form an oxide isolation 26.
이때 열산화는 종래보다 열산화되는 두께가 작으므로, 산화진행시 NBL-UP되는 양이 적게되어 높은 항복전압(Breakdown Voltage)을 가질 수 있어 훨씬 안정된 디바이스 특성을 갖게된다.At this time, since thermal oxidation has a smaller thickness of thermal oxidation than in the related art, the amount of NBL-UP during the oxidation process is reduced, so that the thermal oxidation voltage can have a high breakdown voltage and thus have much more stable device characteristics.
또 상기 제2도(d)에서와 같이 액티브영역으로 정의되는 NBL이 완전히 옥사이드면에 브로킹(blocking)됨으로써 제2도(h)에서와 같이 디바이스 C와 D를 확실히 아이솔레이션시킨다.In addition, as shown in FIG. 2D, the NBL defined as the active region is completely blocked on the oxide surface, so that the devices C and D are reliably isolated as in FIG. 2H.
상기와 같은 본 발명의 바이폴라 옥사이드 아이솔레이션 제조방법에 다음과 같은 효과가 있다.The bipolar oxide isolation method of the present invention as described above has the following effects.
첫째, 액티브영역으로 정의되는 NBL이 완전히 옥사이드면에 브로킹(blocking)됨으로써 디바이스와 다바이스간에 확실한 아이솔레이션을 형성시킬 수 있다.First, NBL, which is defined as an active region, is completely blocked on the oxide surface, thereby forming a reliable isolation between the device and the device.
둘째, 두단계산화(Two-Step Oxidation)를 실시함으로써, 종래의 한단계 산화(One-Step Oxidation)에 의해 NBL-UP되는 양보다 작게 NBL-UP시켜 항복전압(Breakdown Voltage)을 높일 수 있어 안정된 디바이스 특성을 얻을 수 있다.Second, by performing two-step oxidation, it is possible to increase breakdown voltage by increasing NBL-UP smaller than the amount of NBL-UP by conventional one-step oxidation. Characteristics can be obtained.
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