KR0148297B1 - Method for isolating semiconductor devices - Google Patents
Method for isolating semiconductor devices Download PDFInfo
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- KR0148297B1 KR0148297B1 KR1019940023287A KR19940023287A KR0148297B1 KR 0148297 B1 KR0148297 B1 KR 0148297B1 KR 1019940023287 A KR1019940023287 A KR 1019940023287A KR 19940023287 A KR19940023287 A KR 19940023287A KR 0148297 B1 KR0148297 B1 KR 0148297B1
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Abstract
본 발명에 의한 반도체 소자간의 격리방법에서는 비즈버크 현상과 좁은 폭효과등에 의해 파생되는 문제와, 기판 내의 불순물층과 격리막과의 오정렬등의 문제를 해결하기 위하여, 반도체 기판상에 자기 정렬방식의 화학기상증착 산화막을 형성한 후에, 소자격리영역에만 화학기상증착 산화막이 잔류하도록 식각하여 격리막을 형성시켜서 반도체 소자간을 격리시킴으로써 반도체 집적회로의 고집적화가 용이하도록 한다.In the isolation method between semiconductor devices according to the present invention, in order to solve the problems caused by the bead buckling phenomenon and the narrow width effect, and the problem of misalignment between the impurity layer and the isolation layer in the substrate, the self-aligned chemistry of the After the vapor deposition oxide film is formed, the chemical vapor deposition oxide film is etched to remain only in the device isolation region to form an isolation film to isolate the semiconductor devices, thereby facilitating high integration of the semiconductor integrated circuit.
Description
제1도는 종래의 반도체 소자간의 격리방법인 국부산화막의 형성방법을 도시한 도면.1 is a view showing a method of forming a local oxide film, which is a method of isolation between conventional semiconductor devices.
제2도는 종래의 반도체 소자간의 격리방법인 화학기상증착 산화막의 형성방법을 도시한 도면.2 is a view showing a method of forming a chemical vapor deposition oxide film as a method of isolation between conventional semiconductor devices.
제3도는 본 발명에 의한 반도체 소자간의 격리방법을 도시한 도면.3 is a diagram showing a method for isolating semiconductor devices according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10.20.30 : 반도체기판 11 : 산화막10.20.30: semiconductor substrate 11: oxide film
12 : 질화막 13 : 국부산화막12: nitride film 13: local oxide film
21.31 : 격리막 22.32 : 측면산화막21.31 Separator 22.32 Lateral oxide
23 : 포토레지스트 A.A'.A : 소자격리영역23: photoresist A.A'.A: device isolation region
B.B'.B : 소자형성영역B.B'.B: device formation area
본 발명은 반도체 집적회로에서의 소자간의 격리방법에 관한 것으로, 특히 자기 정렬방식의 화학기상증착 산화막을 이용하여 소자의 고집적화에 적당하도록 한 반도체 소자간의 격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of isolation between devices in a semiconductor integrated circuit, and more particularly, to a method of isolation between semiconductor devices suitable for high integration of devices using chemical vapor deposition oxide films of a self-aligning method.
반도체 집적회로에 있어서, 각 소자간의 격리는 각 소자의 동작과 집적회로의 고집접화에 많은 영향을 끼친다.In semiconductor integrated circuits, isolation between the devices has a great influence on the operation of each device and the high integration of the integrated circuits.
종래 반도체 소자간의 격리방법으로는 국부산화(LOCOS : Local Oxidation of Silicon)방식으로 형성시킨 국부산화막에 의해 이루어지거나, 화학기상증착(CVD : Chemical Vapor Deposition)산화막을 이용하였다.Conventionally, the isolation method between semiconductor devices is made of a local oxide film formed by LOCOS (Local Oxidation of Silicon), or a chemical vapor deposition (CVD) oxide film is used.
제1도는 종래의 반도체 소자간의 격리방법인 국부산화막의 형성방법을 도시한 도면이고, 제2도는 종래의 반도체 소자간의 격리방법인 화학기상증착 산화막을 이용하여 격리막의 형성방법을 도시한 도면으로, 도면을 참고하여종래의 반도체 소자간의 격리방법을 설명하면 다음과 같다.FIG. 1 is a diagram showing a method of forming a local oxide film, which is a isolation method between conventional semiconductor devices, and FIG. 2 is a diagram showing a method of forming an isolation film using a chemical vapor deposition oxide film, which is a isolation method between conventional semiconductor devices. Referring to the drawings, the isolation method between the conventional semiconductor devices is as follows.
종래의 반도체 집적회로에서 각 소자간의 격리방법으로는 제1도에 도시된 바와 같이, 국부산화막을 형성시키는 방법이 사용되어 왔다.As a method of isolating each element in a conventional semiconductor integrated circuit, a method of forming a local oxide film has been used, as shown in FIG.
반도체기판상에 국부산화막을 형성시키기 위해서는 우선 반도체기판(10)상에 산화막(11)과 질화막(12)을 차례대로 증착시킨 후에, 제1도의 (a)와 같이, 반도체기판(10)상의 산화막(11)과 질화막(12)을 제거하여 소자격리영역(A)과 소자형성영역(B)을 정의한다.In order to form a local oxide film on a semiconductor substrate, first, an oxide film 11 and a nitride film 12 are sequentially deposited on the semiconductor substrate 10, and then, as shown in FIG. 1A, an oxide film on the semiconductor substrate 10 is formed. (11) and the nitride film 12 are removed to define the device isolation region A and the device formation region B. In FIG.
그리고 제1도의 (b)와 같이, 반도체기판(10)상에서 소자형성영역(B)의 질화막(12)을 마스크로 하여 소자격리영역(B)에 기판과 같은 도전형의 불순물을 이온주입한다.As shown in FIG. 1B, ion-implanted impurities, such as a substrate, are implanted into the device isolation region B using the nitride film 12 of the element formation region B as a mask on the semiconductor substrate 10.
그 후에는 제1도의 (c)와 같이, 소자격리영역에 일정 두께이상의 산화막을 성장시킴으로서 국부산화막(13)을 형성시킨다.Thereafter, as shown in FIG. 1C, a local oxide film 13 is formed by growing an oxide film of a predetermined thickness or more in the device isolation region.
이때, 반도체기판상에서 국부산화막을 형성시킨 소자격리영역에서는 문턱전압(threshold voltage)이 높아지게 되어 인접한 소자들간의 국부산화막 아래의 기판 표면으로 전자의 이동이 일어나지 않게되어 소자격리가 이루어지며, 소자격리영역의 문턱전압을 제한된 국부산화막의 두께 조건에서 더욱 증가시키기 위해서 제1도의 (b)와 같이, 기판과 같은 도전형의 불순물을 이온주입하여 채널 스톱용 불순물층을 형성시킨다.In this case, in a device isolation region in which a local oxide film is formed on a semiconductor substrate, a threshold voltage is increased, so that electrons do not move to the surface of the substrate under the local oxide film between adjacent devices. In order to further increase the threshold voltage at the limited local oxide thickness condition, as shown in FIG. 1B, an impurity layer for channel stop is formed by ion implantation of an impurity of a conductive type such as a substrate.
즉, 국부산화막에 의한 소자간의 격리방법에서는 국부산화막의 형성과정에서 반도체기판상의 질화막이 소자형성영역과 소자격리영역을 완전히 분리할 수 있다.That is, in the isolation method between devices by local oxide, the nitride film on the semiconductor substrate can completely separate the device formation region and the device isolation region during the formation of the local oxide film.
그런, 반도체 집적회로의 집접도가 높아짐에 따라 국부산화막의 양쪽 가장자리가 소자형성영역의 측면을 침투(ⓐ부위)하는 버즈비크(bird's beak) 현상에 의해 소자형성영역이 축소되었고, 각 소자간의 격리를 위한 국부산화막 아래의 불순물 이온층의 측면 확산에 의해 소자형성영역에 형성시킨 각 소자의 문턱전압이 증가되는 좁은 폭효과(narrow width effect)가 발생하게 되는 문제가 제기되었다.As the integration degree of the semiconductor integrated circuit increases, the device formation region is reduced by a bird's beak phenomenon in which both edges of the local oxide film penetrate the side of the device formation region, and isolation between the devices is achieved. A problem arises in that a narrow width effect occurs in which the threshold voltage of each device formed in the device formation region is increased by the side diffusion of the impurity ion layer under the local oxide film.
또한, 반도체기판상에서 각 소자간에 폭이 1㎛ 이하의 소자격리영역을 형성시킬 경우에, 소자격리영역의 산화막을 성장시켜 형성시키는 국부산화막의 두께가 원하는 두께보다 얇아지는 현상(oxide thinning effect)이 발생하였다.In addition, when a device isolation region having a width of 1 μm or less is formed between elements on a semiconductor substrate, an oxide thinning effect in which the thickness of a local oxide film formed by growing and forming an oxide film in the device isolation region becomes smaller than a desired thickness. Occurred.
종래의 반도체 소자간의 격리방법에서 국부산화막에 의한 소자간의 격리방법의 이러한 문제점을 보완하기 위해서 사용되었던 또 다른 반도체 소자간의 격리방법은 제2도에 도시된 바와 같이, 화학기상증착 산화막을 이용한 소자격리방법이다.Another isolation method between semiconductor devices, which has been used to solve this problem of the isolation method between devices by local oxides in the isolation method between semiconductor devices, is a device isolation using a chemical vapor deposition oxide film as shown in FIG. Way.
반도체기판상에 화학기상증착 산화막을 형성시키기 위해서는 우선 제2도의 (a)와 같이, 반도체기판(20)상에서 포토레지스트(photoresist)(23)을 이용하여 소자형성영역(B')과 소자격리영역(A')을 정의한 후에, 소자격리영역(A')에만 반도체기판(20)과 같은 도전형의 불순물을 선택적으로 이온주입한다.In order to form a chemical vapor deposition oxide film on a semiconductor substrate, first, as shown in FIG. 2A, the device formation region B 'and the device isolation region are formed on the semiconductor substrate 20 using a photoresist 23. After defining (A '), ion implantation is selectively implanted into the device isolation region A' such as a conductive type impurity such as the semiconductor substrate 20.
그리고 제2도의 (b)와 같이, 반도체기판(20)상에서 소자형성영역(B')의 표면에 있는 포토레지스트(23)를 제거한다.As shown in FIG. 2B, the photoresist 23 on the surface of the element formation region B 'is removed from the semiconductor substrate 20.
이어서, 반도체기판(20) 전면에 산화막을 화학기상증착하여 화학기상증착 산화막을 형성하고 전면에 사진식각하여 소자격리영역(A')에만 화학기상증착 산화막을 잔류시켜서 격리막(21)을 형성시킨 후에, 또 한층의 산화막을 화학기상증착하고 건식식각하여, 제2도의 (c) 와 같이, 소자격리영역(A') 상의 격리막(21)의 양측면에 측면산화막(22)을 형성시켰다.Subsequently, an oxide film is chemically deposited on the entire surface of the semiconductor substrate 20 to form a chemical vapor deposition oxide film, and photochemically etched on the entire surface of the semiconductor substrate 20 to leave the chemical vapor deposition oxide film only in the device isolation region A 'to form the isolation film 21. Further, the oxide film was further subjected to chemical vapor deposition and dry etched to form side oxide films 22 on both sides of the isolation film 21 on the device isolation region A 'as shown in FIG.
종래의 화학기상증착 산화막에 의한 반도체 소자간의 격리방법에서는 국부산화막에 의한 소자간의 격리방법의 버즈비크현상 및 좁은 폭효과등의 문제점을 개선할 수 있었다.In the conventional method for isolating semiconductor devices by chemical vapor deposition oxide film, problems such as the buzz beak phenomenon and the narrow width effect of the device isolation method by local oxide film can be improved.
즉, 종래의 소자격리방법인 국부산화막에 의한 소자 격리방법과 화학기상증착 산화막을 이용한 소자 격리방법중에서, 국부산화막에 의한 소자 격리방법에서는 소자형성영역의 폭이 축소되고 각 소자의 문턱전압이 증가되는 문제가 발생되었고, 화학기상증착 산화막을 이용한 소자 격리방법에서는 국부산화막에 의한 소자격리방법에서 발생되는 문제가 해결되었지만, 기판내의 불순물층과 기판표면의 화학기상증착 산화막간의 오정렬(mis-align)(ⓑ부위)이 발생하게 되었고, 소자격리영역의 불순물층을 화학기상증착 산화막이 충분히 감싸도록 하여야 하므로 반도체 고집적회로에 적용하는데에 어려움이 발생하였다.That is, in the device isolation method using a local oxide film and the device isolation method using a chemical vapor deposition oxide, which are conventional device isolation methods, in the device isolation method using a local oxide film, the width of the device formation region is reduced and the threshold voltage of each device is increased. In the device isolation method using the chemical vapor deposition oxide film, the problem of device isolation by the local oxide film was solved, but the misalignment between the impurity layer in the substrate and the chemical vapor deposition oxide film on the substrate surface was solved. (Ⓑ) was generated, and the impurity layer in the device isolation region had to be sufficiently encapsulated by the chemical vapor deposition oxide film, which made it difficult to apply the semiconductor integrated circuit.
본 발명에 의한 반도체 소자간의 격리방법에서는 이러한 문제를 해결하기 위하여 안출된 것으로, 자기 정렬방식의 화학기상증착 산화막을 이용하여 반도체 소자간을 격리시킴으로써 반도체 집적회로의 고집적화를 용이하게 하는 것이 그 목적이다.The isolation method between semiconductor devices according to the present invention was devised to solve such a problem, and its object is to facilitate high integration of semiconductor integrated circuits by isolating semiconductor devices using chemical vapor deposition oxide films of a self-aligning method. .
본 발명에 의한 반도체 소자간의 격리방법은 반도체기판 표면에 기판과 같은 도전형의 불순물을 이온 주입하여 불순물층을 형성시키는 단계와, 상기 불순물층을 형성시킨 반도체기판 전면에 제1산화막을 화학기상증착하고 상기 반도체기판 상의 소자격리영역에만 잔류되도록 식각하여 소자형성영역을 한정하는 격리막을 형성하는 단계와, 상기 반도체기판 전면에 제2산화막을 화학기상증착하고 에치백하여 상기 격리막의 양측면에 측면산화막을 형성시키는 단계와, 상기 소자격리영역 상의 격리막과 상기 측면산화막을 마스크로 상기 반도체기판과 반대 도전형의 불순물을 이온주입하여 상기 소자형성영역의 불순물층을 상쇄시키는 단계를 포함하여 이루어진다.The isolation method between semiconductor devices according to the present invention comprises the steps of forming an impurity layer by ion implanting an impurity of a conductive type such as a substrate on the surface of the semiconductor substrate, and chemical vapor deposition of a first oxide film on the entire surface of the semiconductor substrate on which the impurity layer is formed. And forming an isolation layer defining an element formation region by etching the residue to remain only in the device isolation region on the semiconductor substrate, and chemically vapor-depositing and etching back the second oxide layer over the entire surface of the semiconductor substrate to form side oxide layers on both sides of the separator. And forming ion-implanted impurities of the opposite type to the semiconductor substrate using the isolation layer and the side oxide film on the device isolation region as a mask to offset the impurity layer of the device formation region.
제3도는 본 발명에 의한 반도체 소자간의 격리방법의 일예를 도시한 도면으로, 도면을 참고하여 본 발명에 의한 반도체 소자간의 격리방법의 일예를 설명하면 다음과 같다.3 is a view showing an example of an isolation method between semiconductor devices according to the present invention, an example of the isolation method between semiconductor devices according to the present invention with reference to the drawings as follows.
먼저 제3도의 (a)와 같이, 반도체기판(30)의 표면에 소자간을 격리시키는 소자격리영역의 문턱전압을 증가시키기 위해서 반도체기판(30)과 같은 도전형의 불순물을 이온주입한다.First, as shown in FIG. 3A, in order to increase the threshold voltage of the device isolation region that isolates the devices from the surface of the semiconductor substrate 30, ion-implanted impurities such as the semiconductor substrate 30 are ion implanted.
그리고 제3도의 (b)와 같이, 반도체기판(30) 전면에 제1산화막을 화학기상증착하여 화학기상증착 산화막을 형성시킨 후에, 건식식각공정으로 반도체기판(30)상에 소자형성영역(B)을 정의하고 소자격리영역(A) 상에만 화학기상증착 산화막을 잔류시켜서 격리막(31)을 형성시킨다. 상기 본 발명의 일예에서 화학기상증착 산화막을 건식식각하여 격리막(31)을 형성하였으나, 본 발명의 다른 실시예로 화학기상증착 산화막을 습식식각하여 격리막(31)을 형성할 수도 있다.As shown in FIG. 3 (b), after the first oxide film is chemically deposited on the entire surface of the semiconductor substrate 30 to form a chemical vapor deposition oxide film, the device formation region B is formed on the semiconductor substrate 30 by a dry etching process. ) And the chemical vapor deposition oxide film is left only on the device isolation region (A) to form the isolation film (31). In the exemplary embodiment of the present invention, the chemical vapor deposition oxide film is dry-etched to form the separator 31. However, in another embodiment of the present invention, the chemical vapor deposition oxide film may be wet-etched to form the separator 31.
그 후에는 반도체기판(30)상에서 건식식각에 의해 형성시킨 소자격리영역(A)에 의해 생성되는 단차로 인한 반도체소자 제조공정의 어려움을 감소시키기 위해서 제2산화막을 화학기상증착하고 에치백하여 격리막(31)의 양측면에 측면산화막(32)을 형성시킨다.Thereafter, in order to reduce the difficulty of the semiconductor device manufacturing process due to the step generated by the device isolation region A formed by dry etching on the semiconductor substrate 30, the second oxide film is chemically vapor deposited and etched back to isolate the separator. The side oxide film 32 is formed on both sides of the 31.
이어서, 제3도의 (c)와 같이, 소자격리영역(A)의 격리막(31)을 마스크로 반도체기판(30)에 반대도전형의 불순물을 이온주입하여 소자형성영역(B)의 불순물층을 상쇄시킨다.Subsequently, as shown in FIG. 3 (c), the impurity layer of the element formation region B is implanted by ion implanting impurities of the opposite conductivity type into the semiconductor substrate 30 using the isolation layer 31 of the element isolation region A as a mask. Offset.
본 발명에서는 반도체기판 상에 자기 정렬방식의 화학기상증착 산화막을 건식식각하여 형성시킨 격리막을 소자격리영역에 형성시켜서 반도체 소자간을 격리시킨다.In the present invention, an isolation film formed by dry etching a self-aligned chemical vapor deposition oxide film on a semiconductor substrate is formed in the device isolation region to isolate semiconductor devices.
본 발명에 의한 반도체 소자간의 격리방법에서는 종래의 반도체 소자간의 격리방법인 국부산화막에 의해서 발생하는 버즈비크현상에 의한 소자형성영역의 채널 폭(chennel width) 감소현상과, 국부산화막형성시의 소자격리영역의 불순물층의 확산에 의해 소자형성영역에 형성시킨 각 소자의 문턱전압증가 현상을 감소시킬 수 있고, 화학기상증착 산화막에 의한 반도체 소자간의 격리방법에서의 오정렬현상을 제거할 수 있으므로 반도체 고집적회로의 소자간의 격리를 용이하게 실시할 수 있다.In the isolation method between semiconductor devices according to the present invention, the reduction of the channel width of the device formation region due to the Buzz Beek phenomenon caused by the local oxide film, which is a conventional isolation method between semiconductor devices, and the isolation of the device at the time of forming the local oxide film The diffusion of the impurity layer in the region can reduce the threshold voltage increase of each element formed in the element formation region and can eliminate the misalignment in the isolation method between semiconductor elements by chemical vapor deposition oxide film. The isolation between the elements can be easily performed.
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