JPS63292644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an element isolation region, which can be flattened and miniaturized by simple steps, by digging the bottom part of a groove, and embedding a single crystal silicon layer in the groove by using a selective epitaxial method in the fourth step. CONSTITUTION:Ions of specified impurity species such as As<+>, B<+>, P<+> and the like are implanted in a groove 4, in which a thermal oxide film 5 is formed, and a channel cutting layer 6 is formed. Only the thermal oxide film 5 at the bottom part of the groove 4 undergoes anisotropic etching by an RIE method in a mixed gas atmosphere. The bottom part of the groove 4 is further etched. The bottom part of the groove 4 is further dug as shown by a numeral 8. Thereafter, a single crystal silicon layer 9 is embedded in the groove 4 by a selective epitaxial method. Finally, the surface is oxidized, and a flat oxide film 10 is formed on the surface of the single crystal silicon layer 9 in the groove 4. Since the oxide films 5 and 10 are insulating films and the channel cutting layer 6 is also an insulating region in this constitution, an element isolation region including the single crystal silicon layer 9 in the groove 4 is formed.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a semiconductor device related to element isolation technology, which includes: forming an insulating film on the sidewalls of a trench formed in a semiconductor substrate, etching the bottom of the trench, and then etching the bottom of the trench. By growing single-crystal silicon in the groove using a selective pitaxial growth method, it is possible to manufacture a semiconductor device having an element isolation region with a flat surface.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a trench having an insulating film formed on the sidewall is used as an element isolation region.

In semiconductor integrated circuits, element isolation technology for electrically isolating semiconductor island regions constituting circuit elements from each other is as follows:
Due to the demand for higher integration of semiconductor integrated circuits, it is necessary to planarize and miniaturize element isolation regions.

[Conventional technology]

Semiconductor devices related to element isolation technology have been proposed in the past, but a representative one is the selective oxidation valve @ (lo
Cal oxidation of 5ilicon:
10cO3) method is known. In this method, a silicon nitride film (Si3N4 film) is formed on a silicon substrate, and a thermal oxidation process is performed using this film as an oxidation-resistant mask to form a thick silicon oxide film (Sin2 film) on the exposed portion of the substrate. S formed by thermal oxidation! 02 film is insulation f1
- is high and constitutes an element isolation region.

Furthermore, as a method for manufacturing a semiconductor device, a method is known in which a trench is dug in a semiconductor substrate and the trench is filled with an insulating material to form an element isolation region. This type 13 also has various groove shapes,
For example, the cross section forms a (1-shaped vortex), then S
After forming the iO2 film, fill the 0-shaped groove with a polycrystalline silicon layer, then back-etch to leave the polycrystalline silicon layer only in the groove, and finally oxidize the surface to obtain a flat element isolation region. A so-called U-groove system is known.

[1-Problem to be Solved by the Invention] However, in the above-mentioned 10CO8 method, the 1-S! There was a problem in that both ends of the 02 film were formed high (so-called bird's head) and could not be completely flattened, making it difficult to miniaturize.

In addition, in the UtM method described above, the insulating layer can be buried more deeply in a narrow area than in the L0COS method, so high integration of integrated circuits can be achieved. There was a problem that the process was complicated, such as back etching.

The present invention has been created in view of the above points, and has a simple T.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form an element valve 1i111γ1 region that can be flattened and miniaturized using a culm.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes a first step of forming a vortex on a semiconductor silicon substrate, and a second step of forming a thermal oxide film on the side walls and bottom of the vortex. After removing the thermal oxide film at the bottom of the trench, a third step is to further dig the bottom to a certain length. 4 and a fifth step (2) of forming an insulating film on the surface of the single crystal silicon layer.

[Effect]

In the third step, the bottom of the vortex is dug down, and the thermal oxide film is removed near and at the bottom of the sidewall of the groove. In the trench in this state, a single crystal silicon layer is embedded using the pitaxial method, so the device is not affected by the width of the trench that is the front region of the device, and 77 sets do not occur. A region can form a valve #.

〔Example〕

FIGS. 1(A) to 1(G) each show a vertical cross-sectional view of an apparatus at each manufacturing step showing an embodiment of the method of the present invention.

In the drawings, the same components are denoted by the same reference numerals, and their explanations will be omitted. First, as shown in FIG. 1(A), a semiconductor substrate +1 is placed on the surface of a crystalline silicon substrate 1. 02 membrane 2 and S! Reactive ion etching is applied to a semiconductor device in which 3N4 films 3 are sequentially stacked.
on etching (RIB) method in a mixed gas atmosphere of, for example, Freon gas (CF4) mixed with 5% oxygen gas. SiO2 film 2
Then, the Si3N4 film 3 is subjected to heterogeneous etching, and the S
i3N4 membrane 3. S! 02 films 2 and reach the inside of the single crystal silicon substrate 1, forming a 4-hole with a narrow width and a deep depth. The depth d of the groove 4 varies depending on the cord to be formed, but is approximately 1.0 μm, for example.

Next, using the 5iaN4 film 3 as an oxidation-resistant mask, for example, H
A thermal oxidation treatment is performed at a temperature of 950° C. in a Ce gas atmosphere, and a thermal oxide film (S!02 film) 5 is formed on the side walls and bottom of the groove 4 to a thickness of approximately 1000° C., as shown in FIG. 1(B). Cover the adhesion.

Next, as shown in FIG. 1(C), Δs is
A channel cut layer 6 is formed by ion-implanting a predetermined range of impurities such as +, B'', and P'' into the area where the thermal oxide film 5 is formed.

Next, for example, 5% oxygen gas is mixed with CF4, and further CH
In a mixed gas atmosphere containing F3, anisotropic etching is performed only on the thermal oxide film 5 at the bottom of the trench 4 by RIE, and only the thermal oxide film 5 at the bottom of the trench 4 is etched. Remove, leaving a thermal oxide film on the sidewalls. As a result, the single-crystal silicon substrate 1 is exposed at the bottom of the groove 4, as shown by 7 in FIG.

Next, the bottom of the groove 4 is etched using the RIE method, and the first
As shown at 8 in Figure (E), the bottom of the groove 4 is, for example, 2800 mm.
~ Dig into about 3,000 people. Therefore, there is no thermal oxide film 5 on the side wall of the trench 4 at a depth of about 2,800 to 3,000 depth from the bottom of the trench 4, and the single crystal silicon substrate 1 is exposed. The reason why the bottom of the groove 4 is dug down as shown by 8 in FIG. 1(F) is to almost eliminate the occurrence of facets in the single crystal silicon layer 9 due to the selective epitaxial method described later.

Next, as shown in FIG. 1(F), a single crystal silicon layer 9 is buried inside 14 by selective epitaxial method. The single crystal silicon layer 9 is grown by this selective epitaxial method at 950°C, for example, using trichlorosilane gas (Si
The test is carried out at a rate of about 500 people/minute in an atmosphere of HCea) under a pressure of about 0.05 oz./grorr.

As a result, the single-crystal silicon layer 9 grows only on the single-crystal silicon substrate 1 and does not grow on the thermal oxide film 5, and the groove 4 is filled with the 11-crystal silicon layer 9. .

Finally, the surface is oxidized by a normal thermal oxidation process to form a flat oxide film 10 on the surface of the single crystal silicon layer 9 in the groove 4, as shown in FIG. 1(G). As a result, the oxide film 5.10 is an insulator film, and the channel cut layer 6.
Since both are insulating regions, an element isolation region is formed including the single crystal silicon layer 9 in the groove 4.

According to this embodiment, the occurrence of facets in the single crystal silicon layer 9 grown by the selective epitaxial method can be almost eliminated. Furthermore, the width of the groove 4 can be made extremely narrow by the RIE method.

〔Effect of the invention〕

As described above, according to the present invention, the occurrence of facets in the single crystal silicon layer filled in the trench can be almost eliminated, so the surface of the element isolation region can be flattened, and back etching etc. are not required. The process is simpler than the above-mentioned U-man method, and it has the advantage that a semiconductor device having a finer element isolation region can be easily manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an apparatus in each manufacturing process showing an embodiment of the method of the present invention. In the figure, 1 is a single crystal silicon substrate, 4 is a groove, 5 is a thermal oxide film (S f 02 film), 6 is a channel cut layer, 9 is a single crystal silicon layer, and 10M film. Figure 1 shows the bacteria in the vagina IC' = 19UbA column of the method of the present invention.

Claims (1)

[Claims] A first step of forming a groove (4) on a silicon substrate (1), and a second step of forming a thermal oxide film (5) on the side walls and bottom of the groove (4). , a third step of etching and removing the thermal oxide film (5) at the bottom of the trench (4), and further digging the bottom of the trench (4) by a certain length; A single crystal silicon layer (9) grown by selective epitaxial method is placed inside the groove (4).
), and a fifth step of forming an insulating film (10) on the surface of the single crystal silicon layer (9) in the groove (4) formed in the fourth step. A method for manufacturing a semiconductor device, characterized by: