JPS6131386A - Vapor phase epitaxial growth process - Google Patents

Vapor phase epitaxial growth process

Info

Publication number
JPS6131386A
JPS6131386A JP15226484A JP15226484A JPS6131386A JP S6131386 A JPS6131386 A JP S6131386A JP 15226484 A JP15226484 A JP 15226484A JP 15226484 A JP15226484 A JP 15226484A JP S6131386 A JPS6131386 A JP S6131386A
Authority
JP
Japan
Prior art keywords
silicon
epitaxial growth
substrate
exposed
selective epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15226484A
Other languages
Japanese (ja)
Inventor
Hiroshi Kitajima
洋 北島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15226484A priority Critical patent/JPS6131386A/en
Publication of JPS6131386A publication Critical patent/JPS6131386A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To retard the growth of facet by dipping a single crystal silicon substrate having surface coated partly with an insulative film in an anisotropic etching soln. to execute etching of silicon at the exposed part and executing selective epitaxial growth of silicon. CONSTITUTION:A silicon oxide film 7 is formed on the surface of a silicon wafer 6, and an opening part 8 having an almost perpendicular side wall is formed by reactive ion etching. When the substrate is dipped in an anisotropic etching soln. capable of exposing selectively a (111) face, a (100) face 9 is exposed on the base surface and a (111) face 10 is exposed on the side surface. An epitaxial layer 11 is formed by executing selective epitaxial growth of silicon thereon.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はシリコンの選択エピタキシャル成長を行うに際
し、側壁部に於けるファセットの形成を抑制する気相エ
ピタキシャル成長法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a vapor phase epitaxial growth method for suppressing the formation of facets on sidewalls when performing selective epitaxial growth of silicon.

(従来技術とその問題点) シリコンのCMO8(Complementary M
etal −0xide −Sem1conducto
r )デバイスは、バイポーラ・デバイスと同等の速度
をもち、MOS に於ける速度・電力積の究極値を実現
できると予想されることから、現在応用範囲を広げつつ
あり、近い将来MO8IC(Integiated C
1rcuit )の有力な技術になると考えられる。そ
うしたCMO8の特徴をよシ先かすために素子分離の微
細化が有効であシ、現在種々の方法が検討されているが
、有力な方法として、選択エピタキシャル成長法がある
(Prior art and its problems) Silicon CMO8 (Complementary M
etal -Oxide -Sem1conducto
r) devices have speeds equivalent to bipolar devices and are expected to be able to achieve the ultimate speed/power product in MOS, so the range of applications is currently expanding, and in the near future MO8IC (Integrated C
1rcuit) is expected to become a powerful technology. In order to take advantage of such characteristics of CMO8, it is effective to miniaturize element isolation, and various methods are currently being considered, and one of the most promising methods is selective epitaxial growth.

選択エピタキシャル成長法の例金第1図に示す。An example of the selective epitaxial growth method is shown in FIG.

シリコン・ウェハ1の上に酸化シリコン膜2ヲ1〜2μ
mの厚さだけ形成し、反応性イオンエツチングによって
部分的にシリコンを露出させたものをエピタキシャル成
長用の基板として用いる。場合によっては9111壁部
を窒化シリコン膜3等でコートする。そのような基板に
、原料ガスとしてS 1H2C1tとHC7とを用いエ
ピタキシ九ル成長を行うと、酸化シリコン膜上には全く
シリコンが堆積せず、シリコンが露出していた領域だけ
にエピタキシャル層4が形成できる〇 しかしながら、たとえば(100)基板を用いた場合に
側壁部付近にファセット5が形成されるという欠点を有
していた。選択エピタキシャル成長が原理的に絶縁物上
にシリコンを堆積させずシリコン上だけに成長させると
いう方法であることから、表面エネルギーが低い面が側
壁部付近にあられれやすいことが原因となっていると考
えられる0これは(111)基板等を用いた場合でも同
様の状況が生ずるo (111)基板を用いた場合には
、表面の対称性が3回対称であjD (100)基板の
4回対称と異ることによってファセットが見られる側壁
と見られない側壁はあるものの本質的には同様の現象が
生ずる。(100)基板と(111)基板と會合わせて
考えると、表面から第1図の様に傾いたところに(11
1)面が存在する場合にファセットが生じている。ファ
セットの面は必ずしも(111)而ではないが、微細に
は(111)面が階段的に露出しているのではないかと
考えられる。
A silicon oxide film 2 of 1 to 2μ is deposited on the silicon wafer 1.
A substrate formed with a thickness of m and with silicon partially exposed by reactive ion etching is used as a substrate for epitaxial growth. In some cases, the wall portion of 9111 is coated with a silicon nitride film 3 or the like. When epitaxial growth is performed on such a substrate using S1H2C1t and HC7 as source gases, no silicon is deposited on the silicon oxide film, and the epitaxial layer 4 is formed only in the exposed silicon region. However, when a (100) substrate is used, for example, the facet 5 is formed near the side wall. Since selective epitaxial growth is a method in which silicon is grown only on the silicon without depositing it on the insulator, we believe that this is because surfaces with low surface energy tend to form near the sidewalls. 0 This is the same situation when using a (111) substrate, etc. o When using a (111) substrate, the surface symmetry is 3-fold symmetry, and jD (100) substrate has 4-fold symmetry. Although there are side walls where facets are visible and side walls where facets are not, essentially the same phenomenon occurs. Considering the (100) and (111) substrates together, the (11)
1) A facet occurs when a surface exists. Although the faces of the facets are not necessarily (111), it is thought that the (111) planes are exposed stepwise in detail.

第1図に示した様なファセットがあると、ゲート′71
L極を形成してMIS )ランジスタとして動作させる
と表面が平坦な場合に較ベトランジスタ特性に次のよう
な劣化が見られる。
If there is a facet as shown in Fig. 1, the gate '71
When an L pole is formed and the transistor is operated as an MIS transistor, the following deterioration is observed in the transistor characteristics when the surface is flat.

1)  V型の部分の先端に電界が集中するためにゲー
ト耐圧が低下する。
1) Gate breakdown voltage decreases because the electric field concentrates at the tip of the V-shaped part.

■)平坦な表面部とファセットの部分でしきい値が異る
こと、すなわち二種のしきい値をもつたトランジスタが
並列に並んでいるものと見なされるが、そのためにサプ
スレッシェホールド特性が悪化する。
■) The threshold value is different between the flat surface and the facet. In other words, it is considered that transistors with two different threshold values are lined up in parallel. Getting worse.

デバイスや分離域の微細化がゲート酸化膜厚の減少をも
意味するとすれば、上記の2つの劣化は、素子寸法を微
細にする程顕著になるだめ、ファセットの存在杖微細化
を阻ける主要な原因であった。
If miniaturization of devices and isolation regions also means a reduction in gate oxide film thickness, the above two deteriorations will become more pronounced as device dimensions become smaller. This was the cause.

(発明の目的) 本発明の目的は、ファセットの形成を低減させるような
気相エピタキシャル成長法を提供することにある。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a vapor phase epitaxial growth method that reduces the formation of facets.

(発明の構成) ファセットの形成は、側壁付近の成長速度が、側壁から
離れた領域の成長速度に較べ小さいという現象であるか
ら、必要な成長膜厚を場所によって変えればよいことに
なる。そのために本発明は、成長前の基板を異方性エツ
チング溶液に浸し側壁から離れた領域をエツチングする
方法を用いているO (実施例) 第2図(a)〜(C1は本発明の工程を模式的に示した
ものである。図中(alは通常の選択エピタキシャル成
長用の基板と同じであシ、シリコン・ウエノ16の表面
に厚さ1〜2μmの酸化シリコン膜7全形成し、反応性
イオンエツチングによってほぼ垂直な側壁をもつ開口部
8を設けた状態を示している。
(Structure of the Invention) Since the formation of facets is a phenomenon in which the growth rate near the sidewall is smaller than the growth rate in the region away from the sidewall, the required thickness of the grown film can be changed depending on the location. To this end, the present invention employs a method in which the substrate before growth is immersed in an anisotropic etching solution to etch regions away from the sidewalls. In the figure (Al is the same as the substrate for normal selective epitaxial growth), a silicon oxide film 7 with a thickness of 1 to 2 μm is entirely formed on the surface of the silicon wafer 16, and the reaction is performed. The opening 8 with substantially vertical side walls is shown formed by ion etching.

この状態の基板を(111)面が選択的に露出しやすい
異方性エツチング溶液に浸した後の状態が(blである
。(ioo)基板を用いると、底面に(100)而9が
表われ、側壁付近に(111)面10が表われる。(C
)は(blの基板を用いて選択エピタキシャル成長を行
った結果を示している。エピタキシャル層11の表面は
、通常の選択エピタキシャル成長膜に較べはるかに平坦
にすることができる。
The state after immersing the substrate in this state in an anisotropic etching solution that tends to selectively expose the (111) plane is (bl). When a (ioo) substrate is used, (100) and 9 are displayed on the bottom surface. The (111) plane 10 appears near the side wall.(C
) shows the results of selective epitaxial growth using a substrate of (bl).The surface of the epitaxial layer 11 can be made much flatter than that of a normal selective epitaxial growth film.

第3図は、異方性エツチング溶液を用いたエツチング量
によってエピタキシャル成長後の表面における段差がど
う変化するかを示したグラフである。異方性エツチング
溶液としてはヒドラジンを用いた。選択エピタキシャル
成長の条件は、原料ガスとしてstn、c/2300 
cc/min 、  HC1!1.317m1n成長温
度950℃、成長圧力50 TorrであるOエピタキ
シャル膜の膜厚は、〜1μmにエツチング量を加えた値
とした口すなわちヒドラジンによるエツチング量が10
00Xの場合には〜1.1μm成長を行い1表面凹凸の
量を測定した。その結果、エツチング量1μm弱の場合
に、表面の凹凸が1000X弱であり、エツチングを行
わない場合に較ベファセットを115以下減少させるこ
とができた0この実施例では絶縁膜パターン側壁には特
に別の材料を形成せず酸化シリコンのままで選択エビを
行なったが、窒化シリコン膜を第1図と同様な方法で側
壁に形成してから本発明の方法を行なってもよい0また
異方性エツチング溶液はヒドラジンに限らずKOH等で
もよい。
FIG. 3 is a graph showing how the level difference on the surface after epitaxial growth changes depending on the amount of etching using an anisotropic etching solution. Hydrazine was used as the anisotropic etching solution. The conditions for selective epitaxial growth are stn, c/2300 as the source gas.
cc/min, HC1!1.317m1n The film thickness of the O epitaxial film, which has a growth temperature of 950°C and a growth pressure of 50 Torr, is ~1 μm plus the etching amount, that is, the etching amount by hydrazine is 10 μm.
In the case of 00X, growth was performed by ~1.1 μm, and the amount of unevenness on one surface was measured. As a result, when the etching amount was less than 1 μm, the surface unevenness was less than 1000×, and compared to the case where no etching was performed, the facet could be reduced to 115 or less. Although selective ejection was carried out using silicon oxide without forming another material, it is also possible to form a silicon nitride film on the side wall in the same manner as shown in Fig. 1 and then carry out the method of the present invention. The etching solution is not limited to hydrazine, but may also be KOH or the like.

(発明の効果) 以上述べた様に、本発明の方法は選択エビタキシャル成
長法を微細素子分離に適用する際の問題点とりわけ、よ
り微細化を志向する際顕著になる問題点であるファセッ
トの形成を抑制することができる。
(Effects of the Invention) As described above, the method of the present invention solves the problems when applying the selective epitaxial growth method to fine element isolation, especially the problem of facets, which becomes noticeable when aiming for further miniaturization. formation can be suppressed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の選択エピタキシャル成長法の場合の模式
的断面図、第2図(,1〜(elは本発明の一実施例を
示す模式的断面図、第3図は本発明を適用した場合のエ
ツチング量と表面凹凸の関係を示す図。 1・・・シリコン・ウェハ、2・・・酸化シリコン膜、
3・・・窒化シリコン瞑、4・・・エピタキシャル層、
5・・・7アセツト、6・・・シリコン・ウェハ、7・
・・酸化シリコン膜、8・・・開口部、9・・・(10
0)面、10・・・(111)面、11・・・エピタキ
シャル層。 代理人弁理土内 原  晋   7.;第1区 第2図 δ 第3図
FIG. 1 is a schematic cross-sectional view of the conventional selective epitaxial growth method; FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention; FIG. A diagram showing the relationship between the etching amount and surface unevenness. 1...Silicon wafer, 2...Silicon oxide film,
3...Silicon nitride layer, 4...Epitaxial layer,
5...7 assets, 6...silicon wafer, 7.
...Silicon oxide film, 8...Opening, 9...(10
0) plane, 10... (111) plane, 11... epitaxial layer. Attorney Susumu Douchi Hara 7. ;1st ward, 2nd figure δ 3rd ward

Claims (1)

【特許請求の範囲】[Claims]  表面を部分的に絶縁膜で被覆した単結晶シリコン基板
を異方性エッチング溶液に浸して露出した部分のシリコ
ンをエッチングした後シリコンの選択エピタキシャル成
長を行うことを特徴とする気相エピタキシャル成長法。
A vapor phase epitaxial growth method characterized by immersing a single crystal silicon substrate whose surface is partially covered with an insulating film in an anisotropic etching solution, etching the exposed silicon, and then performing selective epitaxial growth of silicon.
JP15226484A 1984-07-23 1984-07-23 Vapor phase epitaxial growth process Pending JPS6131386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15226484A JPS6131386A (en) 1984-07-23 1984-07-23 Vapor phase epitaxial growth process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15226484A JPS6131386A (en) 1984-07-23 1984-07-23 Vapor phase epitaxial growth process

Publications (1)

Publication Number Publication Date
JPS6131386A true JPS6131386A (en) 1986-02-13

Family

ID=15536687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15226484A Pending JPS6131386A (en) 1984-07-23 1984-07-23 Vapor phase epitaxial growth process

Country Status (1)

Country Link
JP (1) JPS6131386A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292644A (en) * 1987-05-26 1988-11-29 Fujitsu Ltd Manufacture of semiconductor device
KR100245394B1 (en) * 1997-12-24 2000-02-15 정선종 Semiconductor device fabrication method using selective area growth

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292644A (en) * 1987-05-26 1988-11-29 Fujitsu Ltd Manufacture of semiconductor device
KR100245394B1 (en) * 1997-12-24 2000-02-15 정선종 Semiconductor device fabrication method using selective area growth

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