JPS61288428A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in the characteristics of an element by a method wherein the upper end corner part of the groove, formed on a substrate by performing an isotropic etching of the thin film which is used as a mask when the substrate is etched, is exposed and the corner part is rounded off in the above-mentioned state, thereby enabling to prevent the generation of a leak at the corner part. CONSTITUTION:A thermally oxided film 12 is formed on a P-type Si substrate 11, and a desired resist pattern 13 is formed thereon. Then, the thermally oxided film 12 is selectively etched using the resist film 13 as a mask. Subsequently, after the resist 13 is removed, a groove 14 is formed by performing a selective etching on the Si substrate 11 using the thermally oxided film 12 as a mask. When the thermally oxided film 12 is etched, the upper surface of the Si substrate 11 is exposed a little, and the corners of the upper end of the Si substrate 11 are rounded off when its sputter etching is performed. Then, the thermally oxided film 12 is exfoliated completely. After the substrate 11 is etched, a before-oxidation treatment is performed, a gate oxide film 15 is formed on the substrate, and a polycrystalline Si film 16 is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION C. Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to improvements in microfabrication techniques for single-crystal silicon substrates.

[Technical background of the invention and its problems]

The integration of semiconductor integrated circuits, especially semiconductor memories, is still increasing at a rate of four times every two years, and the design dimensions are about to enter the Bumiron range.

In the case of a dynamic RAM (hereinafter abbreviated as DRAM) whose memory cell is composed of one transistor/one capacitor and stores one bit depending on whether or not the capacitor is charged, in order to perform stable operation and suppress soft errors, , a capacitor capacity of 30 to 50 [fF] is required. In order to ensure the above-mentioned capacitance while pattern dimensions become smaller, it is necessary to make the gate oxide film thinner.

However, there is a limit to how thin the gate oxide film can be made, making it difficult to ensure the above-mentioned capacity.

Therefore, recently, a so-called trench capacitor, in which a 9i substrate is deeply dug and a capacitor is built vertically, has been proposed. As shown in FIG. 4, a Si substrate 41 is vertically etched to form a groove 42, the substrate surface is oxidized to form a gate oxide film 43 on the bottom and side surfaces of the groove 42, and then a gate oxide film 43 is formed on the bottom and side surfaces of the groove 42. A polycrystalline 3i film 44 is embedded therein to constitute one electrode of the capacitor.

However, this type of structure has the following problems. That is, a reactive ion etching method (RIE method) is generally used as a method for forming the groove 42 in the 3i substrate 41, but in this method, as shown in FIG. becomes angular in shape.

Stress is concentrated on these angular parts, especially the upper end 45, which deteriorates the quality of the oxide film in these parts, causing leakage when a capacitor is formed. This leakage is a serious problem in memory cells, leading to poor memory retention.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to round the upper end corners of grooves formed by vertical etching by RIE method etc.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to improving device performance.

[Summary of the invention]

The gist of the present invention is to expose the upper corner of the groove formed in the substrate by etching the thin film, which is a mask during substrate etching, in the same direction, and in this state, round the corner by sputtering.

That is, the present invention provides a method for manufacturing a semiconductor device that includes a step of forming a groove in a silicon substrate, in which a thin film is formed on the silicon substrate, a resist is applied on the thin film, and the resist is exposed and developed to form a desired resist. form a pattern,
Next, the thin film is etched using the resist pattern as a mask, the silicon substrate is etched by anisotropic etching using the thin film as a mask, a part of the thin film is etched by isotropic etching, and then the silicon substrate is etched by isotropic etching. In this method, exposed portions of the substrate are sputter-etched using an inert gas.

〔Effect of the invention〕

According to the present invention, the upper end corners of the grooves formed in the substrate can be rounded by sputtering the substrate using a thin film as a mask. Therefore, when applied to the formation of a capacitor of a memory cell, it is possible to prevent leakage from occurring at the corner portion, and it is possible to improve the device. Further, since the exposed layer on the upper surface of the substrate can be controlled by changing the amount of isotropic etching of the thin film, it is possible to prevent problems such as an increase in the opening width of the groove.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 1 and 2 are cross-sectional views showing a trench capacitor forming process according to an embodiment of the present invention. First, as shown in FIG. 1(a), a P-type S:substrate 11 with a plane orientation of (100) is subjected to hydrogen combustion oxidation at 950 [C] to a thickness of 8500 [C]. ) 12 was formed.Subsequently, a positive photoresist 1 was formed on the thermal oxide film 12.
3 was applied, and this resist was exposed and developed to form a desired resist pattern.

Next, the thermal oxide film 12 was selectively etched by anisotropic etching using the resist 13 as a mask, as shown in FIG. 1(b). For this etching, an ordinary cathode-coupled reactive ion etching apparatus was used, and CHF3 was used as the etching gas.

Next, the resist 13 was removed using a 02 plasma iodization device. Then, by anisotropic etching again, the first
As shown in Figure (C), using the thermal oxide film 12 as a mask,
Grooves 14 were formed by selectively etching the Si substrate 11.

For this etching, a cathode-coupled reactive ion etching apparatus was used as before, and CBrF9 gas was used as the gas. Also, the pressure during etching was 0.04[
torr] and the high frequency power was 600 [W].

At this stage, the 81 substrate 11 was cut into two parts, both were immersed in a buffered hydrofluoric acid solution, and the thermal oxide film 12 of one was etched by about 0.3 [μTrL] as shown in FIG. 1(d). On the other side, the thermal oxide film 12 was completely peeled off.

Since the etching of the oxide film in a buffered hydrofluoric acid solution proceeds in the same direction, the sample in which the thermal oxide film 12 was etched by 0.3 [μm] was as shown in FIG. 2(a). The top surface is slightly exposed. Therefore, this sample was put into the reactive ion etching apparatus again, and Ar gas was used as the inert gas, the pressure was 0.01 [tOrr], and the high frequency power was 60
Sputter etching was performed at 0 [W] for 5 minutes. The sputtering rate varies with the ion incidence angle and is approximately 60
The Si substrate 11 exposed to ions has a maximum value of
The upper end has a rounded shape as shown in FIG. 2(b). Thereafter, the sample was again immersed in a buffered hydrofluoric acid solution to completely peel off the thermal oxide film 12.

Next, immediately after etching the Si substrate 11, the thermal oxide film 1 is etched.
Perform oxidation pretreatment together with the remaining half of the sample from which 2 was peeled off,
As shown in FIG. 2(C), 350 ['
C], gate oxide 1115 is formed in dry 02 (film thickness 90 layers), and polycrystalline 3i film 16 is formed by vapor phase growth.
was formed. Subsequently, under a POCl2 atmosphere, 1000
['C]t'l After performing phosphorus diffusion for 0 minutes, the substrate 11 is immersed in a buffered hydrofluoric acid solution, and the polycrystal S1 is
The oxide film formed on the surface of the film 16 was removed. Thereafter, a positive photoresist was applied to the entire surface, a gate electrode was patterned, and the polycrystalline S1 film 16 was etched using CF4102 mixed gas plasma.

FIG. 3 is a diagram showing the current-voltage characteristics of the trench capacitor formed in this manner. The solid line in the figure shows the embodiment in which the above-described sputtering is performed, and the broken line shows the conventional example in which sputtering is not performed. It can also be seen from this figure that due to the sputtering action, the current value is smaller in the substrate with rounded corners at the upper end, and there is no leakage.

As described above, according to the method of this embodiment, the upper corner of the groove 14 formed in the Si substrate 11 can be rounded by sputtering the 3i substrate 11 using the thermal oxide film 12 as a mask. Therefore, when a trench capacitor is formed, leakage at the corner can be prevented, and the characteristics of a memory cell using the capacitor can be improved. In addition, since the thermal oxide film 12 is not completely removed but is etched isotropically, the groove 14
The width of the opening can be maintained substantially the same as before sputtering without increasing the width of the opening.

That is, if sputtering is performed with the thermal oxide film 12 completely removed, the taper of the groove 14 becomes larger and the opening becomes wider. Furthermore, since sputtering is performed while the thermal oxide film 12 remains on the substrate 11, it is possible to avoid problems such as damage to the element formation region on the substrate 11.

Note that the present invention is not limited to the method of the embodiment described above. For example, the gas used during the sputtering is not limited to Ar, but may be any gas that is inert to 3i. Furthermore, the thin film to be formed on the 3i substrate is not limited to a silicon oxide film, but can be a silicon nitride film or any film that has a sufficiently high etching selectivity with respect to the Si substrate. The length 1 for etching the thin film in the same direction can be changed as appropriate depending on conditions such as the desired taper angle of the groove opening.

In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing the trench capacitor forming process according to an embodiment of the present invention, and FIG. 3 is for explaining the effects of the above embodiment. FIG. 4 is a characteristic diagram showing the current-voltage characteristics of the first one, and a cross-sectional view for explaining the problems of the conventional method. 11...3i substrate, 12...thermal oxide film (thin film), 1
3...Resist, 14...Trench, 15...Gate oxide film, 16...Polycrystal $1 film. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 vg (v) - Figure 3

Claims (4)

[Claims] (1) forming a thin film on a silicon substrate and forming a resist pattern on the thin film; selectively etching the thin film using the resist pattern as a mask;
Next, a step of selectively etching the silicon substrate using the thin film as a mask by anisotropic etching, a step of etching a part of the thin film by isotropic etching, and then a step of etching the exposed portion of the silicon substrate onto the substrate. A method for manufacturing a semiconductor device, comprising the step of sputter etching using an inert gas. (2) The method for manufacturing a semiconductor device according to claim 1, wherein a reactive ion etching method is used when etching the silicon substrate. (3) The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film is used as the thin film. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the taper angle of the groove formed in the substrate is changed depending on the amount of isotropic etching of the thin film.