JPH04340721A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method of a self-alignment type vertical bipolar transistor having little irregularity of various characteristics when said transistor is formed on a single crystal silicon substrate having a (100) face. CONSTITUTION:After a cavity is formed under a base leading-out electrode 102, a second silicon oxide film 113 is formed at least on the surface of an exposed silicon substrate 100a in the manner in which the cavity is not filled, the cavity is filled with a first polycrystalline silicon film 114, a part of the second silicon oxide film 113 is eliminated, and an air gap is formed in a part between the first silicon film 114 and the silicon substrate 100a. The silicon substrate 100a and a base leading-out electrode 102 are connected by filling said gap with a polycrystalline silicon film 115. The growth thickness of the polycrystalline silicon film 115 is about 5nm.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical bipolar transistor.

0002

2. Description of the Related Art A conventional method for manufacturing a vertical bipolar transistor will be described with reference to FIGS. 3 and 4. This vertical bipolar transistor is formed on a (111) plane single crystal silicon substrate.

First, as shown in FIG. 3(a), (111
) surface on an N-type single crystal silicon substrate 100b,
Silicon oxide film 101 for base electrode collector insulation,
A base extraction electrode 102 made of a polycrystalline silicon film containing a high concentration of boron, a silicon oxide film 103, and a silicon nitride film 104 are formed, and the silicon nitride film 104, silicon oxide film 103, and base extraction on the area where the emitter is to be formed are formed. The electrode 102 is selectively etched away to provide an opening. Next, a silicon nitride film 105 for a spacer is formed on the side wall of the opening, and a silicon oxide film 1 is formed until a cavity 106 is formed under the base extraction electrode 102.
01 is etched with hydrofluoric acid. Thereafter, a base diffusion layer 107 is formed by implanting boron ions through the opening.

Next, as shown in FIG. 3(b), the cavity 10
6 is buried with a polycrystalline silicon film 108, and the polycrystalline silicon film 108 in the cavity 106 is converted into a polycrystalline silicon film 108a containing a high concentration of boron by diffusion of boron from the base extraction electrode 102 through heat treatment. Highly concentrated boron is diffused onto the surface of the single crystal silicon substrate 100b via the crystalline silicon film 108a to form a graft base diffusion layer 109. Graft-based diffusion layer 10
9 is connected to the base diffusion layer 107.

Next, as shown in FIG. 3(c), the polycrystalline silicon film 108 is etched with hydrazine. At this time, with hydrazine, (111) single crystal silicon,
Since the etching rate of silicon containing a high concentration of boron is extremely low, the progress of etching stops when the base diffusion layer 107 and polycrystalline silicon film 108a on the surface of the single crystal silicon substrate 100b are exposed.

Next, as shown in FIG. 4, after removing the silicon nitride films 104 and 105, a spacer made of an insulating film 110 is formed on the side wall of the opening, and a high concentration of N for an emitter electrode is formed to cover the opening. A polycrystalline silicon film 111 is formed, and an emitter diffusion layer 112 is formed on the surface of the base diffusion layer 107 by heat treatment.

[0007]

When a bipolar transistor is formed on a (100) plane single-crystal silicon substrate using the above-mentioned conventional technique, there is a drawback that variations in various characteristics of the transistor increase.

That is, as explained in FIG. 3(c), the polycrystalline silicon film 108 is etched with hydrazine (the reason why plasma etching is not used is to avoid damaging the surface of the silicon substrate 100b in the area where the emitter is to be formed). However, when the base diffusion layer 107 was exposed, the etching was stopped when the base diffusion layer 107 was exposed, taking advantage of the fact that the etching rate was extremely low on the (111) plane. In this case, etching does not automatically stop when the base diffusion layer is exposed. Further, the substrate surface in the region where the emitter diffusion layer is formed is anisotropically etched, and a (111) plane is formed on the surface, thereby making it rough. Furthermore, Figure 3(b
) To fill the cavity 106 under the base extraction electrode 104 with the polycrystalline silicon film 108 shown in FIG.
Although polycrystalline silicon may be deposited by a method, the thickness of the deposited film varies by approximately ±10% overall. The height of the cavity is determined by the thickness of the silicon oxide film 101, which is at least several hundred nanometers in order to reduce the parasitic capacitance between the base extraction electrode 103 and the single crystal silicon substrate 100b (collector).
For this reason, the variation in the thickness of the polycrystalline silicon film is expected to be about ±several tens of nanometers.

For this reason, as shown in FIG. 3C, when the polycrystalline silicon film 108 is etched with hydrazine, the etching stops on the polycrystalline silicon film 108a, but the etching on the base diffusion layer 107 is ± several tens of degrees. nm
This will result in more than a certain degree of variation. This variation is based on the base width (i.e., the junction depth of the base diffusion layer 107).
Due to this and the roughness of the surface of the base diffusion layer 107 described above, variations in various characteristics such as amplification factor and breakdown voltage of the bipolar transistor become large.

0010

[Means for Solving the Problems] In the method of manufacturing a semiconductor device of the present invention, in forming a self-aligned vertical bipolar transistor, after forming a cavity under a base lead-out electrode, at least the exposed surface of a silicon substrate is a step of forming a second silicon oxide film without filling the cavity; a step of filling the cavity with the first silicon film;
forming a void between the first silicon film and the silicon substrate by removing a portion of the silicon oxide film; and forming a second silicon film to fill at least the void. are doing.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a cross-sectional view of the process order for explaining the first embodiment of the present invention.

First, as shown in FIG. 1(a), (100
) A silicon oxide film 101 for base electrode collector insulation is formed on an N-type single crystal silicon substrate 100a having a surface of
, a base extraction electrode 102 made of a polycrystalline silicon film containing a high concentration of boron is formed, and the base extraction electrode 102 on the area where the emitter is to be formed is selectively etched away to form an opening. Subsequently, a silicon oxide film 101
A cavity is formed under the base extraction electrode 102 by etching with hydrofluoric acid.

Next, a silicon oxide film 113 with a thickness of about 10 nm is deposited by low pressure CVD, and then a polycrystalline silicon film is deposited on the entire surface by low pressure CVD to fill the cavity, and this polycrystalline silicon film is Figure 1
As shown in (b), the silicon oxide film 113 on the bottom of the opening, the side walls of the opening, and the top surface of the base extraction electrode 102
expose. At this stage, the cavity is formed by the silicon oxide film 11.
3 and a polycrystalline silicon film 114.

Next, the silicon oxide film 113 is etched until a gap is formed between the polycrystalline silicon film 114 and the single crystal silicon substrate 100a, and the polycrystalline silicon film 113 is etched as shown in FIG. 115 is deposited by low pressure CVD method to fill the voids. At this time, the height of the void is 10
Since the thickness of the polycrystalline silicon film 115 is approximately 5 nm, the void is filled by depositing the polycrystalline silicon film 115 to a thickness of approximately 5 nm. Note that thermal oxidation can also be used instead of the low pressure CVD method.

Next, the silicon substrate 100a at the bottom of the opening is
The polycrystalline silicon film 115 is etched with hydrazine until it is exposed. In this case, the silicon substrate surface 100a is anisotropically etched as in the conventional case, and the etching film thickness varies, but the polycrystalline silicon film 11
Since the film thickness of the bipolar transistor 5 is thin, this variation is about ±5 angstroms, which is an order of magnitude smaller than the conventional variation, and the variation in various characteristics of the bipolar transistor can be significantly reduced. Note that plasma etching can also be used instead of etching with hydrazine. This is also because since the amount to be etched is small, the amount of damage to the silicon substrate 100a is also minimal.

Thereafter, as shown in FIG. 1(d), boron is diffused from the base extraction electrode 102 by thermal diffusion.
The polycrystalline silicon film 115 filled in the void and the polycrystalline silicon film 114 filled in the void are converted to P type, and a graft base diffusion layer 109 is formed. Furthermore, a base diffusion layer 107 is formed by boron ion implantation, and an insulating film 116 is formed on the base extraction electrode 102 and on the side walls of the opening.
The opening is covered with a highly concentrated N-type polycrystalline silicon film 111 that will become an emitter electrode, and an emitter diffusion layer 112 is formed by thermal diffusion.

According to this embodiment, the bipolar transistor has improved variation in amplification factor by about 30% compared to the conventional bipolar transistor.

It is clear that this embodiment can also be applied to a single crystal silicon substrate having a (111) plane.

FIG. 2 is a cross-sectional view of the process order for explaining a second embodiment of the present invention. In the first embodiment, the cavity under the base extraction electrode 102 is filled with a silicon oxide film 113.
Although the void between the polycrystalline silicon film 114 and the single crystal silicon substrate 100a is filled with the polycrystalline silicon film 115, filling of the void is not limited to this method. In this example, by using selective epitaxial growth,
The process is further simplified.

First, as shown in FIG. 2A, a gap is formed between the polycrystalline silicon film 114 and the single crystal silicon substrate 100a in the same manner as in the first embodiment. Subsequently, when selective epitaxial growth of silicon is performed, the result is as shown in FIG. 2(b).
), a silicon epitaxial layer 118 having a (100) plane is selectively grown on the surface of the silicon substrate 100a at the bottom of the opening, and a polycrystalline silicon film 117 is grown on the other parts. As a result, the base extraction electrode 1
02 and the silicon substrate 100a are connected by silicon. After that, the graft base diffusion layer 109 is formed by heat treatment.
, a base diffusion layer 107 is formed, and a base extraction electrode 1 is formed.
An insulating film 116 is formed on 02 and on the side walls of the opening, and a polycrystalline silicon film 111 for an emitter electrode and an emitter diffusion layer 112 are formed to obtain a bipolar transistor having the structure shown in FIG. 2(c).

In this example, in order to connect the base lead-out electrode and the silicon substrate using the polycrystalline silicon film grown during selective epitaxial growth, the surface of the silicon substrate in the area where the emitter is to be formed is covered by the thickness of the silicon epitaxial layer. becomes higher. Emitter electrodes can be formed without etching this polycrystalline silicon film and silicon epitaxial layer.
Since the emitter diffusion layer can be formed, the manufacturing process is simpler than in the first embodiment. In addition, the variation in the base width is reduced to only the variation in the thickness of the silicon epitaxial layer, and the variation in characteristics is further reduced than in the first embodiment.

[0022]

Effects of the Invention As explained above, the present invention can reduce the growth thickness of the silicon film for connecting the silicon substrate and the base lead-out electrode by one order of magnitude compared to the conventional method, thereby improving various characteristics of bipolar transistors. Variations can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

100a, 100b single crystal silicon substrate 101
, 103, 113 Silicon oxide film 102
Base extraction electrodes 104, 105 Silicon nitride film 106
Cavity 107 Base diffusion layer 108, 108a, 111, 114, 115, 117
Polycrystalline silicon film 109 Graft base diffusion layers 110, 116 Insulating film 112 Emitter diffusion layer

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device in which a vertical bipolar transistor is formed on one main surface of a single crystal silicon substrate of one conductivity type, wherein a first
forming a polycrystalline silicon film of the opposite conductivity type through the silicon oxide film of the emitter, and forming an opening by selectively removing the polycrystalline silicon film of the opposite conductivity type in the area where the emitter is to be formed; A step of exposing the first silicon oxide film at the bottom and forming a base extraction electrode made of the reverse conductivity type polycrystalline silicon film, and etching the first silicon oxide film with hydrofluoric acid from the opening. , forming a cavity from the end of the opening toward the base lead-out electrode, and forming an exposed surface of the single crystal silicon substrate at the bottom of the opening; forming a second silicon oxide film on the exposed surface; filling the cavity with the first silicon film; and etching the second silicon oxide film to remove at least the first silicon film and the exposed silicon film. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a gap in a part between the surfaces; and filling the gap with a second silicon film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of filling the void with the second silicon film, a single crystal silicon film is selectively formed on the exposed surface.