KR940007656B1 - Manufacturing method of homo, hetero-junction bipolar transistor using substrate junction method - Google Patents

Abstract

The method is for manufacturing a heterojunction and homojunction dipole transistor using a substrate connection method. The method includes the steps of: (A) forming silicon layers (31,32) on a P-type substrate (30); (B) etching the silicon layer to form device region and forming an insulating layer (33); (C) spraying polycrystal silicon (3) and connecting to another P-type silicon substrate (35); (D) polishing the silicon layer (31) until an insulating layer (33) is exposed; (E) forming connecting area (36) on a silicon layer (32) and forming an insulating layer (37), a polycrystal silicon layer (38), and a silicon layer (39); (F) etching to form an active region and forming a groove on side wall of an insulating layer (37); and (G) spraying polycrystal silicon and heating to form an oxide layer.

Description

Method for manufacturing homogenous and heterojunction dipole transistor devices isolated from devices using substrate bonding method

1 is a cross-sectional view of a conventional heterojunction bipolar device manufactured by ultra-high vibration chemical vapor deposition.

2 is a cross-sectional view of a double polycrystalline silicon heterojunction dipole device completed by the manufacturing method of the present invention.

3 is a cross-sectional view for each step of fabricating a double polycrystalline silicon heterojunction dipole device according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high speed bipolar device that can be used in a next generation high speed information processing system such as a computer or a communication device, and more particularly, to fabricating homojunction and heterojunction dipole transistor devices that isolate devices using a substrate bonding method. It is about a method.

In general, unlike homojunction dipole transistors, a heterojunction dipole device using an energy bandgap difference and an emitter and a base are formed of different materials. Intensive research as a high speed dipole element.

In the design of such a heterojunction dipole device, an important factor to be considered is to reduce parasitic resistance and parasitic capacitance due to mask misalignment.

1 is a cross-sectional view of a conventional double polycrystalline silicon heterojunction dipole device manufactured by Ultra high vacuum chemical vapor deposition (UHV / CVD).

In FIG. 1, a collector 12 is grown on an N ⁺ -type silicon layer 11 formed on a P-type silicon substrate 10, and an ultrafine thin film base 16 is formed using polysilicon 15. ) To facilitate metal wiring contact, then grow silicon germanium (SiGe) base, deposit silicon oxide films (17, 19) and nitride film (18), and base polycrystalline silicon (110) Diffuse to form a thin emitter 111.

As a result, the emitter size of the device can be reduced to the limit size of the micro-shaped equipment, and the parasitic capacitance due to the reduction of the overall size of the device increases the operation speed of the device and also enables high integration.

In addition, the device is isolated using a trench isolation process to increase the parasitic capacitance between the device and the isolation part when the device is isolated by conventional dopant ion implantation or diffusion. The degradation of the device performance is prevented, and the degree of integration is achieved.

However, due to parasitic resistance at the side of the insulating film 14 separating the polycrystalline silicon 15 and the collector 12 for the base electrode and the ultra-thin film base, the maximum vibration frequency and the switching speed of the device are deteriorated. When the base is grown by the solid source MBE, it is not certain whether the base is formed on the insulating film 14 and the polycrystalline silicon 15 side.

Therefore, the structure of FIG. 1 is not suitable as an element structure using the solid source molecular beam crystal thin film growth method.

Accordingly, the present invention, in order to solve the structural disadvantages of the conventional heterojunction device, by using the solid source molecular beam crystal thin film growth method to reduce the base parasitic resistance and parasitic capacitance operating characteristics in the high frequency band of the device It is an object of the present invention to provide a method of manufacturing a dipole transistor with an improved structure.

Hereinafter, the present invention will be described in detail.

2 is a cross-sectional view of a heterojunction dipole device manufactured by the solid source molecular beam crystal thin film growth method according to the present invention.

In FIG. 2, the device of the present invention further reduces the base running resistance, which is one of the structural drawbacks of FIG. 1, and further reduces the parasitic capacitance by isolating the device through substrate bonding, thereby improving the operation speed of the device and the performance of the IC. Greatly improved.

First, the collectors 21 and 22 are formed on the first silicon substrate, the thermal oxide film 23 is formed after the etching process for device isolation, and then the polysilicon 24 is filled and then planarized.

Then, the P-silicon substrate 25 is bonded, and then the first substrate on the other side is subjected to selective polishing, so that the collector layer 21 is polished to the surface of the insulating film 23 to finally form a collector thin film.

After that, the insulating film 26, the polycrystalline silicon 27 for the base electrode 27, and the nitride film are sequentially applied, the active region of the device is defined by an etching process, and the polycrystalline silicon 27 for the base electrode 27 and the collector 21 are subsequently applied. ), Grooves are formed in an etching process on the side of the insulating film 26 separating them. This groove is refilled with polycrystalline silicon 28 to ensure the growth of the base 29 layer on the side of the active region, while simultaneously reducing the base resistance.

Thereafter, the silicon low maenyum base layer 29 is grown, an insulating layer 210 is applied to separate the polycrystalline silicon for the base and the base electrode from the polycrystalline silicon emitter 211, and then etched to define an emitter region. Polycrystalline silicon 211 is deposited on the defined emitter portion.

After that, the device is completed by covering the insulating film, opening the contact, and depositing metal on the contact.

As shown in FIG. 1, the structure of FIG. 2 is a double polycrystalline silicon emitter, which can reduce the device size to reduce parasitic capacitance, as well as integrated circuit, and improve the device performance by reducing the base parasitic resistance. Since the device can be manufactured by the crystalline thin film growth method, the advantages of the solid-source molecular beam crystalline thin film growth method have advantages over the ultra-high vacuum chemical vapor deposition method, that is, the steepness of impurity concentration and low maenyum distribution in the emitter and the interface interface. Improves design stability and reproducibility of device performance due to (abruptness) and high quality silicon low maenyum base layer.

In particular, in the structure of FIG. 2 according to the present invention, parasitics due to the bonding between the collector layer 11 and the silicon substrate, which greatly affects the speed reduction which cannot be removed even in FIG. 1 by isolating the device using the substrate bonding method. The capacity was removed to improve operating speed and cutoff frequency.

In addition, one of the difficulties in the design of IC (Intergratedc Circuit) is the performance of the IC according to the MOS (Metal Oxide Semiconductor) capacitor type dispersion capacitance generated between the metal wiring and the substrate, which are the dominant parasitic components of the IC. It is a degradation phenomenon.

In other words, the improvement of IC performance due to the reduction of dispersion capacity is absolutely great, rather than the improvement of IC performance due to the improvement of device performance.

Therefore, in the case of FIG. 2, in the case of FIG. 2, when the insulating film 23 region is extended and the interconnection wiring between the elements passes therethrough, the thickness of the insulating film of the MOS capacitor is large, so that the dispersion capacity is reduced and the thickness can be easily adjusted. As a result, it is easy to reduce the dispersion capacity.

3a-i is a manufacturing process of an embodiment according to the present invention and will be described in detail as follows.

3 is a cross-sectional view after etching and insulating film for device isolation.

In FIG. 3A, first, silicon layers 31 and 3 2 are formed on a P ⁺ -type silicon substrate 30, an element region is defined by an etching process, and then an insulating film 33 is coated.

FIG. 3B shows a process of applying polycrystalline silicon 34 after the device region defining process to fill and then planarize the etched portion and bonding the P-silicon substrate 35 thereon.

3C shows that after the substrate bonding process, the P ⁺ silicon substrate 35 is selectively polished to polish the collector layer 31 to the surface of the insulating film 33, and the collector 32 is brought into metal contact. After forming the connecting portion 36 by impurity ion implantation, the insulating film 37, the polycrystalline silicon 38, and the insulating film 39 are coated thereon.

In FIG. 3D, an active region of the device is defined by an etching process, grooves are formed on the side of the insulating film 37, and polycrystalline silicon is coated and thermally oxidized to refill the grooves to form the oxide film 40. The process of forming is shown.

3E, the thermally oxidized oxide film 40 is etched away to fill the grooves to leave unoxidized polysilicon 41, and the base thin film 42 and polycrystalline silicon grown thereon are simultaneously etched and then the insulating film ( 43 and 44 are shown.

FIG. 3 shows a process of forming an emitter region by sequentially etching the insulating layers 43 and 44.

FIG. 3 shows a process of removing the nitride film 44 and forming a portion where the collector connecting portion 36 and the metal are in contact by etching.

3 shows a process of simultaneously depositing polycrystalline silicon 45 and defining emitter polycrystalline silicon and collector polycrystalline silicon with a mask.

3 is a completed cross-sectional view of the device.

In FIG. 3, after the insulating film 46 is applied and the contacts are formed, the metal 47 is deposited and the wiring is defined by a mask to etch the metal.

If the silicon crystalline thin film is grown by selective epitaxy growh (SEG) with an emitter after performing the third g process in the above-described third process procedure described above and before depositing the polycrystalline silicon 45, A heterojunction dipole device is fabricated using a silicon crystal thin film as an emitter.

In the above description of the manufacturing process of one embodiment, it will be apparent to those skilled in the art that the present invention may be implemented differently without departing from the spirit of the present invention.

Claims (2)

Forming silicon layers 31 and 32 sequentially on the P ⁺ -type silicon substrate 30, etching the silicon layer to define a device region, and then applying an insulating film 33 to the device region; 34) applying and planarizing and bonding with another P-type silicon substrate 35, polishing the silicon layer 31 to the surface of the insulating film 33, and impurity on a part of the silicon layer 32 Forming the connecting portion 36 for metal contact by ion implantation, and subsequently forming the insulating film 37, the polycrystalline silicon 38 and the insulating film 39 thereon, and then etching the active region of the device And forming a flaw on the side of the insulating film 37, and then applying and thermally oxidizing the polycrystalline silicon, and removing the thermally oxidized polycrystalline silicon and then simultaneously growing the base thin film 42 and the polycrystalline silicon grown thereon. Etching and sequentially forming insulating films 43 and 44 Forming an emitter region by etching the insulating films 43 and 44, and forming a portion where the metal 36 and the connecting portion 36 of the collector are to be contacted after the insulating films 43 and 44 are removed. And depositing the polycrystalline silicon 45 and then defining the emitter polycrystalline silicon and the collector polycrystalline silicon simultaneously with a mask, and forming a contact and then depositing the metal 47. Manufacturing method. The process of claim 1, wherein before the polycrystalline silicon 45 is deposited in the process of defining the emitter polycrystalline silicon and the collector polycrystalline silicon, a process of forming an emitter by growing a silicon crystalline thin film using a selective crystalline thin film growth method. Method of manufacturing a dipole transistor to add.