JP2005142430A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor device having a trench capacitor capable of preventing the occurrence in open failures, even if the trench is made deep. <P>SOLUTION: The trench capacitor is provided on a first trench-side surface 6 and in a region deeper than the first trench-side surface 6 and is provided on a second trench-side surface 7 for communicating with the first trench-side surface 6 and in a region deeper than the second trench side surface 7. The trench capacitor further includes a trench 5, defined by a trench-side surface including a third trench-side surface 8 communicating with the second trench-side surface 7 with the trench 5 of a part defined by the first and second trench-side surfaces 6, 7 tapered in the depth direction, and the first trench-side surface 6 has a relaxed taper than that of the second trench-side surface 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a trench capacitor and a manufacturing method thereof.

  9 to 12 are cross-sectional views showing a conventional trench capacitor manufacturing process. First, as shown in FIG. 9, a silicon oxide film 72, a silicon nitride film 73, and a silicon oxide film 74 are sequentially formed on a silicon substrate 71.

  Next, as shown in FIG. 10, the silicon oxide film 72, the silicon nitride film 73, and the silicon oxide film 74 are processed by using a photolithography process and a dry etching process, thereby forming trench patterns 72-74. Thereafter, with the trench patterns 72-74 as a mask, the silicon substrate 71 is etched by an RIE (Reactive Ion Etching) process, and a trench 77 defined by the first trench side surface 75 and the second trench side surface 76 is formed. The

  The taper angle A1 of the first trench side surface 75 is 88.9 °, and the depth of the trench 77 defined by the first trench side surface 75 is 1.3 μm. The second trench side surface 76 has a vertical or overhang shape. The depth of the portion of the trench 77 defined by the second trench side surface 76 is deeper than the depth of the portion of the trench 77 defined by the first trench side surface 75.

  Hereinafter, the portion of the trench 77 defined by the first trench side surface 75 is referred to as a first trench, and the portion of the trench 77 defined by the second trench side surface 76 is referred to as a second trench.

  Next, as shown in FIG. 11, an impurity diffusion region 78 as a capacitor electrode is formed in the silicon substrate 71 around the second trench by a well-known method, and then the silicon oxide film 74 is removed by a wet process. Is done. Next, a capacitor insulating film 79 is formed on the side surface of the trench 77 by a thermal oxidation process, and then a first amorphous silicon film 80 is deposited so as to fill the trench 77. Subsequently, an opening surface of the trench 77 is formed. The first amorphous silicon film 80 and the capacitor insulating film 79 in the region up to about 1.1 μm are removed by the RIE process.

  Next, as shown in FIG. 12, a silicon oxide film 81 is deposited on the inner surface (side surface and bottom surface) of the resulting trench 77 from which the first amorphous silicon film 80 and the capacitor insulating film 79 have been removed. The silicon oxide film 81 on the bottom surface of one trench is removed by the RIE process, and the inside of the trench 77 is filled with the second amorphous silicon film 82 to obtain a trench capacitor.

  However, the conventional trench capacitor process described above has the following problems. As the semiconductor element is miniaturized, the diameter of the first trench is reduced, so that it is difficult to increase the depth of the second trench. As a result, it becomes difficult to realize a trench capacitor having a trench 77 deep enough to secure a necessary charge amount.

  One method for increasing the depth of the second trench is to increase the taper angle A1 of the first trench (for example, Patent Document 1). When the taper angle A1 is increased, as shown in FIG. 13, a void 83 is generated in the first amorphous silicon film 80 in the first trench. Therefore, a V-shaped groove 84 is formed on the surface of the first amorphous silicon film 80 after the step of FIG. 11, as shown in FIG.

When such a V-shaped groove 84 is generated, the silicon oxide film 81 on the bottom surface of the first trench is not removed by the RIE process in the step of FIG. 12, and the silicon oxide film 81 is formed in the V-shaped groove 84. Remains. As a result, as shown in FIG. 15, the silicon oxide film 81 remains between the first amorphous silicon film 80 and the second amorphous silicon film 82, and an open defect occurs.
U.S. Pat. No. 4,784,720

  As described above, in the conventional manufacturing process of a trench capacitor having a deep trench, a silicon oxide film remains between the tapered first trench and the vertical or overhanging second trench below the first trench. There was a problem that defects occurred.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device including a trench capacitor capable of preventing occurrence of an open defect even if the depth of the trench is increased, and a method for manufacturing the same. Is to provide.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  In other words, in order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device comprising a semiconductor substrate and a trench capacitor provided in the semiconductor substrate, wherein the trench capacitor comprises: 1 trench side surface, provided in a region deeper than the first trench side surface, and provided in a region deeper than the second trench side surface and the second trench side surface communicating with the first trench side surface. And a trench defined by a trench side including a third trench side communicating with the second trench side, wherein the trench in a portion defined by the first and second trench sides is in the depth direction Further, the first trench side surface has a taper angle that is gentler than that of the second trench side surface.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate; and a step of forming a trench capacitor in the semiconductor substrate, wherein the step of forming the trench capacitor includes , A first trench side surface, a second trench side surface provided in a region deeper than the first trench side surface and communicating with the first trench side surface, and a region deeper than the second trench side surface. Forming a trench defined by a trench side including and having a third trench side in communication with the second trench side and defined by the first and second trench sides A portion of the trench tapers in the depth direction, and the side surface of the first trench is tapered more gently than the side surface of the second trench. So as to have an angle, and forming the trench.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  ADVANTAGE OF THE INVENTION According to this invention, even if the depth of a trench is made deep, the semiconductor device provided with the trench capacitor which can prevent generation | occurrence | production of an open defect, and its manufacturing method can be implement | achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 8 are cross-sectional views illustrating a manufacturing process of a semiconductor device including a trench capacitor according to an embodiment of the present invention. The trench capacitor constitutes, for example, a DRAM memory cell.

First, as shown in FIG. 1, a silicon oxide film (SiO ₂ film) 2, a silicon nitride film (Si ₃ N ₄ film) 3, and a silicon oxide film (SiO ₂ film) 4 are sequentially formed on a silicon substrate 1. . The silicon oxide film 2 is formed by, for example, a thermal oxidation method. The film thickness of the silicon oxide film 2 is, for example, 6 nm. The silicon nitride film 3 and the silicon oxide film 4 are formed by, for example, a CVD process. The film thickness of the silicon nitride film 3 is, for example, 220 nm, and the film thickness of the silicon oxide film 4 is, for example, 1.4 μm.

  Next, as shown in FIG. 2, the silicon oxide film 2, the silicon nitride film 3, and the silicon oxide film 4 are processed using a photolithography process and a dry etching process to form a trench pattern 2-4. At this time, the surface of the silicon substrate 1 in the trench formation region is exposed.

  Next, as shown in FIG. 3, using the trench pattern 2-4 as a mask, the silicon substrate 1 is etched by an RIE process, and the trench 5 having a forward taper shape in which the taper angle on the side surface of the trench changes in two stages. It is formed.

  At this stage, the trench 5 is defined by the first trench side surface 6 and the second trench side surface 7. As shown in FIG. 3, the taper angle of the first trench side surface 6 is A1, the depth of the trench 5 in the portion defined by the first trench side surface D is D1, and the taper angle of the second trench side surface 7 is A2. (<A1), the depth of the portion of the trench 5 defined by the second trench side surface 7 is denoted as D2.

  Such a trench 5 can be realized by changing the etching conditions for forming the first trench side surface 6 and the etching conditions for forming the second trench side surface 7.

  For example, the pressure at the time of forming the second trench side surface 7 is set higher than the pressure at the time of forming the first trench side surface 6, or the total flow rate at the time of forming the second trench side surface 7 is set to the first trench side surface 6. For example, it may be less than the total flow rate at the time of formation. Further, when a mixed gas containing O (oxygen) and F (fluorine) is used as an etching gas, the O / F ratio at the time of forming the second trench side surface 7 is the same as that at the time of forming the first trench side surface 6. Increasing the O / F ratio may be mentioned.

Specifically, when the etching gas is a mixed gas of HBr / NF ₃ / O ₂ , the first trench side surface 6 has 125 mT, HBr / NF ₃ / O ₂ = 230/35/12.
700 Wh / 450 Wl, 27 sec. The second trench side surface 7 is formed with the following etching conditions: 125 mT, HBr / NF ₃ / O ₂ = 230/35/20, 700 Wh / 450 Wl, 36 sec. The etching conditions are as follows.

When the etching gas is a mixed gas of HBr / SF ₆ / O ₂ , the first trench side surface 6 has 125 mT, HBr / SF ₆ / O ₂ = 230/15/12, 700 Wh / 450 Wl, 27 sec. The second trench side surface 7 is formed with the following etching conditions: 125 mT, HBr / SF ₆ / O ₂ = 230/15/20, 700 Wh / 450 Wl, 36 sec. The etching conditions are as follows.

When the etching gas is a mixed gas of HBr / Cl ₂ / O ₂ , the first trench side surface 6 has 125 mT, HBr / Cl ₂ / O ₂ = 230/35/3, 700 Wh / 450 Wl, 27 sec. The second trench side surface 7 is formed under the following etching conditions: 125 mT, HBr / Cl ₂ / O ₂ = 230/35/5, 700 Wh / 450 Wl, 36 sec. The etching conditions are as follows.

  The taper angle A1 is 89.5 ° or more, and the depth D1 is 0.4 μm or more. The reason is that the taper angle of the first trench is raised, and the taper angle of the first trench is the same as the conventional taper angle and the depth of the first trench is smaller than this value. This is because the merit of the portion with the increased taper angle is small and the trench depth cannot be increased.

  The taper angle A2 is 89.2 ° or less, and the depth D2 is 0.5 μm or more. The reason is that the V-shape cannot be improved if there is no portion with good embeddability in the second trench in order to improve the V-shape due to the deterioration of the embedment in the first trench portion. This is because the above defect occurs.

  Next, as shown in FIG. 4, the silicon substrate 1 is further etched using the trench pattern 2-4 as a mask, and the bottom (bottom surface) of the trench 5 becomes deeper. The third trench side surface 8 formed by the etching at this time has a vertical or overhang shape. The depth D3 of the portion of the trench 5 defined by the third trench side surface 8 is deeper than the depth (D1 + D2) of the portion of the trench 5 defined by the first and second trench side surfaces 6 and 7.

  Next, as shown in FIG. 5, an impurity diffusion region 9 as a first capacitor electrode is formed in the silicon substrate 1 around the side surface of the third trench by a known method. When D1 + D2 is 1.4 μm, an impurity diffusion region 9 is formed around the third trench side surface 8 that is 2.0 μm below the opening surface of the trench 5.

  Next, as shown in FIG. 5, the silicon oxide film 4 is removed, and then a capacitor insulating film 10 is formed on the inner surface of the trench 5. Subsequently, a dopant as a second capacitor electrode is added into the trench 5. The first amorphous silicon film 11 is embedded.

  At this time, a seam 12 is generated in the first amorphous silicon film 11 in the trench 5 at a portion defined by the first trench side surface 6. The seam 12 does not occur in the portion of the trench 5 defined by the second trench side surface 7. The reason is that A1, D1, A2, and D2 are selected as described above.

  Next, as shown in FIGS. 6 and 7, the first amorphous silicon film 11 in a region extending from the opening surface of the trench 5 to the middle of the second trench side surface 7 beyond the first trench side surface 6. Then, the capacitor insulating film 10 is removed.

  At this time, as shown in FIG. 6, during the etching process of the first amorphous silicon film 11 in the trench 5 in the portion defined by the first trench side surface 6, the surface of the first amorphous silicon film 11 is formed. Produces a V-shaped groove 13.

  However, during the etching process of the first amorphous silicon film 11 in the trench 5 at the portion defined by the second trench side surface 7, the surface of the first amorphous silicon film 11 is flattened and has a V-shape. The groove 13 disappears.

  Next, as shown in FIG. 8, an insulating film 14 such as a silicon oxide film is formed on the side and bottom surfaces of the opening of the trench 5 generated by removing the first amorphous silicon film 11 and the capacitor insulating film 10. Thereafter, the insulating film 14 on the bottom surface of the opening of the trench 5 is removed by the RIE process, and the opening in the trench 5 is filled with the second amorphous silicon film 15 containing the dopant through the insulating film 14. .

  At this time, since there is no V-shaped groove on the surface of the first amorphous silicon film 11, the insulating film 14 does not remain at the interface between the first amorphous silicon film 11 and the second amorphous silicon film 152. Therefore, no open failure occurs.

  Through the above steps, the first trench side face 6 and the second trench side face 7 and the second trench side face provided in a region deeper than the first trench side face 6 and communicating with the first trench side face 6 are provided. 7 and includes a trench 5 defined by a trench side including a third trench side 8 that communicates with the second trench side 7 and is provided in a deeper region than the first trench side 6. As a result, a trench capacitor in which the portion of the trench 5 is tapered in the depth direction and the first trench side surface 6 has a gentler taper angle than the second trench side surface 7 is obtained. The first and second amorphous silicon films 11 and 15 become polycrystalline silicon films by a well-known heat treatment in a later process.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these embodiment. For example, although the case where a silicon substrate is used as the semiconductor substrate has been described in the above embodiment, a semiconductor substrate such as an SOI substrate, a substrate including a strained silicon region, or a substrate including a silicon germanium region can be used. .

  Furthermore, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the manufacturing process of the semiconductor device provided with the trench capacitor which concerns on one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device provided with the trench capacitor which concerns on the same embodiment following the same FIG. Sectional drawing which shows the manufacturing process of the semiconductor device provided with the trench capacitor based on the same embodiment following FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device including the trench capacitor according to the embodiment following FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device including the trench capacitor according to the embodiment following FIG. 4. FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device including the trench capacitor according to the embodiment following FIG. 5. Sectional drawing which shows the manufacturing process of the semiconductor device provided with the trench capacitor which concerns on the same embodiment following FIG. Sectional drawing which shows the manufacturing process of the semiconductor device provided with the trench capacitor based on the same embodiment following FIG. Sectional drawing which shows the manufacturing process of the conventional trench capacitor. Sectional drawing which shows the manufacturing process of the conventional trench capacitor following FIG. FIG. 11 is a cross-sectional view showing a conventional trench capacitor manufacturing process following FIG. 10. Sectional drawing which shows the manufacturing process of the conventional trench capacitor following FIG. Sectional drawing which shows the manufacturing process of the other conventional trench capacitor. Sectional drawing which shows the manufacturing process of the other conventional trench capacitor following FIG. Sectional drawing which shows the manufacturing process of the other conventional trench capacitor following FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Silicon nitride film, 4 ... Silicon oxide film, 5 ... Trench, 6 ... 1st trench side surface, 7 ... 2nd trench side surface, 8 ... 3rd trench side surface , 9 ... Impurity diffusion region, 10 ... Capacitor insulating film, 11 ... First amorphous silicon film (first conductive film) containing dopant, 12 ... Seam, 13 ... V-shaped groove, 14 ... Insulating film, 15 ... A second amorphous silicon film (second conductive film) containing a dopant.

Claims (10)

A semiconductor substrate;
A trench capacitor provided in the semiconductor substrate, wherein the trench capacitor is provided in a first trench side surface, in a region deeper than the first trench side surface, and A second trench side surface that communicates with the first trench side surface, and a trench side surface that is provided in a region deeper than the second trench side surface and includes a third trench side surface that communicates with the second trench side surface. Including a defined trench, wherein the trench defined by the first and second trench side surfaces is tapered in the depth direction, and the first trench side surface is slower than the second trench side surface. A semiconductor device characterized by having a tapered angle. 2. The taper angle of the first trench side surface is 89.5 ° or more, and the depth of the trench in a portion defined by the first trench side surface is 0.4 μm or more. Semiconductor device. 3. The taper angle of the second trench side surface is 89.2 [deg.] Or less, and the depth of the trench at a portion defined by the second trench side surface is 0.5 [mu] m or more. A semiconductor device according to 1. The depth of the trench defined by the third trench side surface is deeper than the depth of the trench defined by the first and second trench side surfaces. 4. The semiconductor device according to any one of items 3. 5. The semiconductor device according to claim 1, wherein a side surface of the third trench has a vertical or overhang shape. 6. An insulating film provided on the trench side surface extending from the opening surface of the trench to the middle of the second trench side surface beyond the first trench side surface; and a portion defined in the trench side surface in the trench 6. The semiconductor device according to claim 1, further comprising: a conductive film that is embedded through the insulating film. Preparing a semiconductor substrate; and
Forming a trench capacitor in the semiconductor substrate, comprising the steps of:
The step of forming the trench capacitor includes a first trench side surface, a second trench side surface provided in a region deeper than the first trench side surface and communicating with the first trench side surface, and the second trench side. Forming a trench defined by a trench side surface provided in a region deeper than the trench side surface and including a third trench side surface communicating with the second trench side surface,
In addition, a portion of the trench defined by the first and second trench side surfaces is tapered in the depth direction, and the first trench side surface has a gentler taper angle than the second trench side surface. Thus, the method of manufacturing a semiconductor device, wherein the trench is formed. The step of forming the first and second trench side surfaces uses a mixed gas of HBr, NF ₃ and O _2, a mixed gas of HBr, SF ₆ and O ₂ , or a mixed gas of HBr, Cl ₂ and O _2. The semiconductor device according to claim 7, further comprising a step of etching a surface of the semiconductor substrate, and the etching condition is changed in the step of forming the first and second trench side surfaces. Production method. In the step of forming the first and second trench side surfaces, the pressure at the time of forming the second trench side surface is made higher than the pressure at the time of forming the first trench side surface. The total flow rate at the time of forming the first trench side surface is made smaller than the total flow rate at the time of forming the first trench side surface, or the O / F ratio in the mixed gas at the time of forming the second trench side surface is 9. The method of manufacturing a semiconductor device according to claim 8, wherein the O / F ratio is larger than that at the time of forming the trench side surface. The step of forming the trench capacitor includes:
Filling the trench with a first conductive film;
Removing the first conductive film in a region extending from the opening surface of the trench to the middle of the second trench side surface beyond the first trench side surface;
Forming an insulating film on a side surface of the opening of the trench generated by removing the first conductive film;
10. The method according to claim 7, further comprising: filling the opening of the trench generated by removing the first conductive film with the second conductive film through the insulating film. The manufacturing method of the semiconductor device of description.

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