KR20050063266A - Method for forming shallow trench isolation in semiconductor device processing - Google Patents

Abstract

A method of separating trench elements in a semiconductor device is disclosed. The field forming region is etched in the semiconductor substrate to form a trench for device isolation. The side wall of the trench is oxidized to form an inner wall oxide film. The substrate is nitrided to form nitride at the inner wall oxide layer and the trench interface with the inner wall oxide layer. A first oxide layer is formed to partially fill the trench. A portion of the first oxide film is etched. Subsequently, a second oxide layer is formed on the partially etched first oxide layer to completely fill the trench. By this method, the device can be separated without void and silicon consumption.

Description

Method for forming shallow trench isolation in semiconductor device processing

The present invention relates to a device isolation method. More specifically, the present invention relates to a trench isolation method for separating the active region and the field region in a semiconductor device.

Since most highly integrated memory designs require device isolation structures between cells in the column direction within the array, it is desirable to minimize the size of device isolation structures to increase the density of the memory array.

Conventional device isolation structures are formed using thermal field oxidation processes such as LOCal Oxidation of Silicon (LOCOS). According to LOCOS device isolation, first, an oxide film and a nitride film are sequentially formed on a silicon substrate, and then the nitride film is patterned. Next, the silicon substrate is selectively oxidized using the patterned nitride film as an oxidation mask to form a field oxide film. According to the LOCOS device isolation, a bird's beak is generated at the end of the field oxide film as oxygen penetrates to the side of the oxide film under the nitride film used as a mask for selective oxidation of the silicon substrate. Since the field oxide film is extended to the active area by the length of the buzz beak by such a buzz beak, the width of the active area is reduced to deteriorate the electrical characteristics of the device.

Accordingly, a shallow trench isolation (STI) structure is used in recent semiconductor devices. According to the STI process, after the silicon substrate is etched to form a trench, an oxide film is deposited to fill the trench. Next, the oxide film is etched by etch back or chemical mechanical polishing (CMP) to form a field oxide film in the trench.

However, as the semiconductor devices are highly integrated, the sizes of the active regions and the field regions are greatly reduced, and accordingly, the widths of the trenches for forming the field regions are very narrow and their depths are relatively deep. As described above, as the aspect ratio of the trench is increased, it is very difficult to fill the oxide film without voids or overhangs in the trench.

In order to fill the oxide film without voids in the stepped portion such as the trench, the oxide film may be deposited in two or more steps. Such a method is disclosed, for example, in Korean Patent Publication Nos. 2003-0012112 and 2003-0058671. However, a problem may occur that the silicon substrate is damaged by a treatment process applied to the substrate while performing the oxide film several times, such as an oxygen plasma treatment or a polishing process.

In addition, during the trench isolation process, a portion of the silicon substrate exposed to the sidewall of the trench may be partially removed during the process, and the size of the active region may locally vary due to the silicon consumption. do. Due to the difference in size of the active region, a difference in characteristics of the semiconductor device formed in each cell occurs. In particular, in the case of a nonvolatile memory device having a design rule of 70 nm or less, the threshold voltage distribution of the cell transistor is generated even by a small amount of silicon consumption, resulting in program failure.

Accordingly, it is an object of the present invention to provide a trench element isolation method in which an oxide film is buried in a trench without voids, and semiconductor substrate consumption of the trench sidewalls is reduced.

In order to achieve the above object, the present invention forms a trench for device isolation by etching the field formation region in the semiconductor substrate. The side wall of the trench is oxidized to form an inner wall oxide film. The substrate is nitrided to form nitride at the inner wall oxide layer and the trench interface with the inner wall oxide layer. A first oxide layer is formed to partially fill the trench. A portion of the first oxide film is etched. Subsequently, a second oxide layer is formed on the partially etched first oxide layer to completely fill the trench.

The device isolation trench is formed by performing a masking step and a substrate etching step to define an etching site.

Specifically, the trench is formed on the semiconductor substrate and then patterned to form a pad oxide layer and a hard mask layer to form a pad oxide layer pattern and a hard mask layer pattern. Subsequently, the exposed substrate portion may be etched using the patterns as an etch mask.

Alternatively, the trench forms a pad oxide film on the semiconductor substrate and a first conductive layer on the pad oxide film. A hard mask film is formed on the first conductive layer. The hard mask layer, the first conductive layer, and the pad oxide layer are etched to form a pad oxide layer pattern, a first conductive layer pattern, and a nitride layer pattern. The exposed portions of the substrate may be etched by using the patterns as etching masks. The method can be applied to a nonvolatile memory device, wherein the pad oxide film is provided as a tunnel oxide film, and the first conductive layer pattern is provided as a floating gate.

The nitriding process of the substrate is performed by an NH ₃ plasma treatment process.

The first oxide film and the second oxide film are formed by a high density plasma deposition method. The oxide film formed by the high density plasma deposition method has a dense film and excellent gap fill characteristics.

The first oxide layer fills the trench more than 50%.

Subsequently, when etching the first oxide film, a wet etching process is performed. The process is intended to remove irregular deposits during the deposition of the first oxide and to extend the trench inlet so that the gap fill works well during subsequent deposition of the oxide.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1A to 1G are cross-sectional views illustrating a trench device isolation method according to a first embodiment of the present invention.

Referring to FIG. 1A, an ion implant process such as well formation and pocket p-well formation is performed on a semiconductor substrate 10 such as silicon.

On the silicon substrate 10, a silicon oxide is thinly grown to a thickness of about 50 to 100 GPa to form a pad oxide film 12.

A silicon nitride film, which serves as a hard mask film and a polishing stopper film, is formed on the pad oxide film 12 to a thickness of about 1500 to 3000 kPa.

Subsequently, silicon oxynitride (SiON) is formed on the silicon nitride film to form an antireflection layer (not shown). The anti-reflection layer serves to prevent diffuse reflection of light in a subsequent photographic process and is mostly removed in a subsequent trench formation process.

Subsequently, the anti-reflection layer and the silicon nitride film are dry-etched by the photolithography process to form the hard mask pattern 14. The pad oxide layer 12 is etched using the hard mask pattern 14, and then the exposed portion of the substrate 10 is etched to a depth of about 1500 to 5000 내지 to form the trench 20. At this time, the anti-reflective layer arbitrarily formed above is removed and the hard mask pattern 14 is also etched by a predetermined thickness.

Referring to FIG. 1B, silicon damage caused by high energy ion bombardment during the trench etching process is removed, and the movement of carbon or dopants from the gap buried oxide film to the silicon substrate 10 to be formed in a subsequent process is performed. In order to cut off and prevent leakage current, a trench inner wall oxide layer 22 is formed on the inner surface of the trench 20, that is, on the trench bottom and sidewalls. The trench inner wall oxide layer 22 is formed to a thickness of about 20 to about 300 kPa.

The trench inner wall oxide layer 22 may be formed by a thermal oxidation process or a chemical vapor deposition method. In the thermal oxidation process, as shown in FIG. 1B, since silicon oxide film is formed by reacting silicon exposed to the inner surface of the trench 20 with oxygen, only the silicon exposed portion of the inner surface of the trench is selectively selected. As a result, a trench inner wall oxide film 22 is formed. On the other hand, when performing the chemical vapor deposition method, although not shown, the oxide film is formed not only on the inner surface of the trench 20 but also on the exposed surfaces of the pad oxide film 12 and the hard mask pattern 14.

Although not shown, a middle temperature oxide (MTO) may be further thinly formed on the trench inner wall oxide layer 22 to about 100 GPa.

Referring to FIG. 1C, a plasma treatment process using NH ₃ gas is performed on the resultant product on which the trench inner wall oxide layer 22 is formed.

When the nitriding treatment process using the NH ₃ plasma is performed, silicon of the inner wall of the trench 20 is nitrided while nitrogen diffuses into the trench inner wall oxide layer 22, thereby forming the inner wall of the trench inner wall oxide layer 22 and the trench 20. Silicon nitride 24 is formed at the interface between the silicon. At this time, some nitrogen components may remain in the trench inner wall oxide layer 22. The silicon nitride 24 formed at the interface between the trench inner wall oxide layer 22 and the silicon of the inner wall of the trench 20 serves to prevent the silicon of the inner wall of the trench 20 from being etched during the subsequent etching process.

Referring to FIG. 1D, a first oxide layer 30 is deposited to partially fill the trench 20. Specifically, the first oxide layer 30 is formed to fill 50% or more of the inside of the trench 20. The first oxide film 30 is preferably formed of a silicon oxide film having excellent gap filling characteristics and a dense film. To this end, the first oxide film is formed of an oxide film (hereinafter referred to as HDP oxide film) by high density plasma deposition.

Briefly describing the process of forming the HDP oxide film, for example, SiH ₄ and oxygen gas are provided as deposition source gases. A source power for ionizing the deposition gas and a bias power provided to enhance the straightness of the source gas are applied such that the ionized source gas is provided mostly in the substrate. In addition, the pressure in the deposition chamber is lowered as much as possible to improve the straightness of the deposition gases. Therefore, since the deposition gases are easily provided even inside the stepped portion, the top-level oxide film may be deposited inside the stepped portion, and thus the HDP oxide layer has excellent gap filling characteristics.

Some of the deposition gases are sputter-etched on the top surface of the film to be ionized and deposited in the chamber, so that the top surface of the HDP film that is finally formed has a sharp shape having an angle of about 45 °.

As described above, since only a portion of the trench depth is first gap-filled, formation of voids in the first oxide layer 30 may be minimized even if the aspect ratio of the trench is increased.

Referring to FIG. 1E, the first oxide layer 30a is partially isotropically etched. By the isotropic etching, the thickness of the first oxide film 30a formed on the hard mask pattern 14 is lowered. In addition, by removing an upper portion of the first oxide film 30a embedded in the trench 20, the inlet of the trench 20 is expanded while leaving the first oxide film 30a inside the trench 20. In addition, by the above process, irregular deposits generated during the deposition of the first oxide film 30a are removed.

The isotropic etching includes a wet etching process. By performing the isotropic etching process, the trench inlet portion may be extended to further facilitate the subsequent oxide deposition process.

During the isotropic etching process, all of the first oxide layer 30 and the trench inner wall oxide layer 22 deposited on the sidewalls of the trench 20 may be removed. However, since the nitride 24 formed at the interface between the trench inner wall oxide film 22 and the silicon of the trench sidewalls caps the silicon of the trench sidewalls, the sidewall portions of the trench 20 are hardly consumed. Therefore, a problem such as reduction of an active area due to exhaustion of the sidewall portion of the trench 20 is hardly generated.

Referring to FIG. 1F, the second oxide layer 32 is completely filled in the trench 20 in which the etched first oxide layer 30a is filled. The second oxide film 32 is formed of a silicon oxide film such as USG, O ₃ -TEOS USG, or a high-density plasma (HDP) oxide film having excellent gap filling properties and a dense film having excellent insulating properties.

Referring to FIG. 1G, the first and second oxide films 30a and 32a are polished to expose the hard mask pattern 14 to form a field oxide film 34 filling the trench 20.

According to the above process, the element isolation film can be formed so that almost no semiconductor substrate consumption of the trench sidewalls is generated while the oxide film is buried without voids in the trench.

Example 2

2A through 2D are cross-sectional views illustrating a method of separating a self-aligned shallow trench device according to the present invention in a nonvolatile memory device.

Referring to FIG. 2A, an ion implantation process such as well formation and pocket p-well formation is performed on the silicon substrate 100. Then, the tunnel oxide film 102 is formed on the substrate 100 to a thickness of 30 ~ 100Å.

A polysilicon film for use as a floating gate is formed on the tunnel oxide film 102 to a thickness of 300 to 1000 Å. The polysilicon film is doped with a high concentration of N-type impurities by conventional doping methods such as POCl ₃ diffusion, ion implantation, or in-situ doping.

Silicon nitride is deposited on the polysilicon film to a thickness of about 100 to 3000 mm 3, preferably 600 mm 3, by LPCVD to form a polishing stopper film. Next, a hard mask film made of silicon oxide is formed on the polishing stopper film. Subsequently, an antireflection film (not shown) made of silicon oxynitride (SiON) is further formed on the hard mask film. The anti-reflection film is a film for preventing diffuse reflection during photo patterning, and may not be formed for process convenience.

The anti-reflection film and the hard mask film are patterned by a general photolithography process to form a hard mask pattern 108. After the hard mask pattern 108 is formed, the photoresist pattern used for patterning the hard mask film is stripped.

Using the hard mask pattern 108 as an etch mask, the polishing stop layer, the polysilicon layer, and the tunnel oxide layer are sequentially etched to form the tunnel oxide layer 102, the polysilicon layer pattern 104, and the polishing barrier layer pattern 106. ). Subsequently, the substrate 100 is etched to a thickness of 1500 to 5000Å to form a trench 120 for forming a field region. Most of the anti-reflection film is removed during the etching.

When the trench is formed by the above-described method, there is an advantage in that the floating gate electrode and the active region are self-aligned.

Referring to FIG. 2B, the silicon damage caused by the high energy ion bombardment during the trench etching process is removed, and the movement of carbon or dopants from the gap buried oxide film to the silicon substrate 100 to be formed in a subsequent process is blocked. In order to prevent the occurrence of leakage current, the trench inner wall oxide layer 122 is formed on the inner surface of the trench 120, that is, the trench bottom and sidewalls. The trench inner wall oxide film 122 is formed to a thickness of about 20 to about 300 kPa.

The trench inner wall oxide film 122 may be formed by a thermal oxidation process or a chemical vapor deposition method. In the thermal oxidation process, as illustrated, since silicon and oxygen are reacted with silicon exposed to the inner surface of the trench to form a silicon oxide film, the trench inner wall is selectively formed only on the silicon substrate and the polysilicon portion of the trench inner surface. An oxide film 122 is formed. On the other hand, in the case of performing the chemical vapor deposition method, although not shown, an oxide film is formed on the entire exposed surface area.

Referring to FIG. 2C, a plasma treatment process using NH ₃ gas is performed on the resultant product on which the trench inner wall oxide film 122 is formed.

When the nitriding treatment process using the NH ₃ plasma is performed, the silicon exposed portion of the trench inner wall is nitrided while nitrogen diffuses into the trench inner wall oxide film 122, so that the trench inner wall oxide film 122 and the trench 120 are formed in the inner wall of the trench 120. Silicon nitride 124 is formed at the interface between the silicon of the exposed substrate. In addition, silicon nitride 124 is also formed at the interface between the trench inner wall oxide film 122 and the polysilicon pattern 104. At this time, some nitrogen components may remain in the trench inner wall oxide film 122. The silicon nitride 124 formed at the interface between the trench inner wall oxide film 122 and the silicon in the trench inner wall serves to prevent etching to the trench inner wall in a subsequent etching process.

Referring to FIG. 2D, the trench isolation layer is formed by performing the same process as described with reference to FIGS. 1D to 1G.

In more detail below, the first oxide layer 130 is formed to fill 50% or more of the inside of the trench. The first oxide film 130 may be formed of a silicon oxide film having excellent gap filling characteristics and a dense film and excellent insulating properties. To this end, the first oxide film 130 is provided as an oxide film (hereinafter referred to as HDP oxide film) by high density plasma deposition.

Subsequently, the first oxide layer 130 is partially isotropically etched. By the isotropic etching, the thickness of the first oxide film 130 formed on the hard mask pattern is lowered. In addition, an upper portion of the first oxide film 130 embedded in the trench is removed to extend the trench inlet while leaving the first oxide film 130 inside the trench. In addition, irregular deposits generated during the deposition of the first oxide layer 130 are removed. The isotropic etching process includes a wet etching process.

Subsequently, the second oxide film 132 is completely filled in the trench in which the first oxide film 130 is partially filled. The second oxide film 132 is formed of a silicon oxide film such as USG, O ₃ -TEOS USG, or a high density plasma (HDP) oxide film having excellent gap filling properties and having a dense film and excellent insulating properties.

Subsequently, the hard mask pattern 108 and the first and second oxide layers 130 and 132 are polished to expose the polishing stop layer pattern 106 to form a field oxide layer 134 to fill the trench.

According to the above process, the isolation layer may be formed such that the floating gate and the active region are self-aligned in the nonvolatile memory device. Further, while the oxide film is buried without voids in the trench, the device isolation film can be formed so that the semiconductor substrate consumption of the trench sidewalls is hardly generated.

As described above, according to the present invention, the oxide film can be buried without voids in the trench during the trench element isolation process of the semiconductor device. In addition, by minimizing the consumption of silicon exposed to the sidewalls of the trench, the active region may be formed to have a uniform size in the entire region of the substrate. Therefore, the distribution of operating characteristics of the semiconductor unit element formed on the active region can be maintained uniformly. In particular, in a semiconductor device having a design rule of 70 mm or less, a large difference in operating characteristics of a semiconductor unit element is generated even by a small difference in active regions, and thus device isolation film formation by the method of the present invention is very useful.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1A to 1G are cross-sectional views illustrating a trench device isolation method according to a first embodiment of the present invention.

2A through 2D are cross-sectional views illustrating a method of separating a self-aligned shallow trench device according to the present invention in a nonvolatile memory device.

<Explanation of symbols for the main parts of the drawings>

10, 100: silicon substrate 12: pad oxide film

14: hard mask pattern 20, 120: trench

22, 122: trench inner wall oxide film 24, 124: silicon nitride

30, 130: first oxide film 32, 132: second oxide film

Claims (6)

Etching the field region in the semiconductor substrate to form a trench for device isolation; Oxidizing the sidewalls of the trench to form an inner wall oxide film; Nitriding the substrate to form nitride at the inner wall oxide layer and the trench interface with the inner wall oxide layer; Forming a first oxide layer to partially fill the trench; Isotropically etching a portion of the first oxide film; And And forming a second oxide film on the partially etched first oxide film to completely fill the trench. The method of claim 1, wherein the nitriding of the substrate is performed by an NH ₃ plasma treatment process. The method of claim 1, wherein the first oxide film is formed by a high density plasma deposition method. The method of claim 1, wherein the first oxide layer fills at least 50% of the inside of the trench. The method of claim 1, wherein the first oxide layer is etched by a wet etching process. The method of claim 1, wherein the second oxide layer is formed of a USG, O ₃ -TEOS USG, or a high density plasma (HDP) oxide layer.