KR100570069B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can prevent the phenomenon that the hard mask is lifted during the cleaning process by improving the poor interface characteristics between the hard mask and the insulating film, the present invention provides an insulating film on the substrate Forming; Surface treating the insulating film to increase the surface roughness of the insulating film; Forming a material layer for a hard mask on the surface treated insulating film; Forming a photoresist pattern on the material layer for the hard mask; Etching the hard mask material layer using the photoresist pattern as an etching mask to form a hard mask; And etching the insulating layer using at least the hard mask as an etch mask to form a predetermined pattern.

SAC, insulating film, hard mask, buffer insulating film, surface treatment, lifting.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}             

1A and 1B are cross-sectional views illustrating a SAC forming process according to the prior art.

FIG. 2 is a SEM photograph showing a process cross section after the SAC process of FIG. 1B. FIG.

3 is a SEM photograph showing a process cross section after the cleaning process.

4 is a planar SEM photograph showing the lifting of the hard mask generated by the cleaning process.

5A through 5C are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the first embodiment of the present invention.

6 is a planar SEM photograph of FIG. 5C.

7A to 7C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

8A to 8C are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

50 substrate 51 gate insulating film

52: first conductive film 53: second conductive film

54 gate electrode hard mask 55 spacer

56 source / drain region 57 insulating film

59: surface treated insulating film 60 ': hard mask

62: open section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent lifting of a pattern due to poor interface characteristics between a hard mask and an insulating layer used in an etching process such as a self alignment contact (hereinafter referred to as SAC). It relates to a semiconductor device manufacturing method that can be done.

As the integration of semiconductor devices becomes higher, the DOF value of the exposure apparatus is lowered, and the thickness of the photoresist pattern is also reduced in order to increase the transmittance by using an exposure source of shorter wavelength. As the thickness of the photoresist pattern decreases, the photoresist pattern is exhausted before the pattern formation is completed, and thus the shape of the initial photoresist pattern is deformed.

In order to solve such a problem, a hard mask is employed between an insulating layer and a photoresist pattern during an SAC process. As the hard mask, various materials such as tungsten, tungsten nitride, silicon nitride, or polysilicon are used.

Therefore, in the case of employing the hard mask as described above, since the photoresist pattern acts as an etching mask for patterning only the hard mask (and the antireflection film), a finer pattern can be formed even with a thin photoresist pattern.

1A and 1B are cross-sectional views illustrating a SAC forming process according to the prior art.

Referring to FIG. 1, a plurality of gate electrode patterns are formed on the substrate 10, and the gate electrode patterns include the gate insulating layer 11, the first and second conductive layers 12 and 13, and the hard mask 14. Has a laminated structure.

The gate insulating film 11 mainly uses an oxide film series, and the first and second conductive films 12 and 13 use a single or combined structure of polysilicon, tungsten, tungsten silicide, tungsten nitride, and the like.

The hard mask 14 prevents the first and second conductive films 12 and 13 from being attacked in a subsequent process such as SAC etching, and also an electrical short between the first and second conductive films 12 and 13 and the subsequent connection portion. Serves to prevent. For this purpose, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as the hard mask 14 material.

A buffer insulating layer is deposited along the profile on which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 15 on the side of the gate electrode pattern.

The spacer 15 is formed to form a source / drain of LDD structure on the substrate 10 on the side of the gate electrode pattern by ion implantation and to prevent attack on the side of the gate electrode pattern during the SAC process.

Therefore, the nitride film is formed alone or in various structures such as an oxide film and a nitride film laminated or a nitride film / oxide film / nitride film structure. The nitride film used here includes a silicon oxynitride film or a silicon nitride film.

A source / drain region 16 extending from the surface of the substrate 10 to a predetermined depth is formed in the substrate 10 or the well (not shown) on the side of the gate electrode pattern by ion implantation and thermal diffusion.

In order to prevent the hot carrier effect due to the short channel, a low level impurity doping and a spacer 15 are formed, followed by a high level impurity doping to form a conventional structure. .

Next, an insulating film 17 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed.

The insulating film 17 may be formed of an oxide film series such as a BPSG (Boro Phospho Silicate Glass) film, a BSG (Boro Silicate Glass) film, a PSG (Phospho Silicate Glass) film, a TEOS (Tetra Ethyl Ortho SIlicate) film, or an HDP (High Density Plasma) oxide film. Use substance.

On the other hand, as the high integration increases the vertical height of the gate electrode pattern, the aspect ratio between the gate electrode patterns increases, resulting in gap-fill defects when the insulating layer 17 is deposited.

In order to prevent this, recently, an SOD film having excellent gap-fill characteristics is applied, and a heat treatment process is performed to densify the film.

Subsequently, a hard mask material film 18 is deposited on the insulating film 17 in order to secure a weak etching resistance of the photoresist in a subsequent SAC process, and then a photoresist for forming SAC on the material film 18 for hard mask. The pattern 19 is formed.

Since the hard mask material film 18 is etched with the thickness of the thin photoresist pattern 19, the thickness of the hard mask material film 18 is low, but a high etching selectivity is required for the oxide film-based material film mainly used for interlayer insulation. The nitride film-based material film is mainly used.

Subsequently, the hard mask material layer 19 is etched using the photoresist pattern 19 as an etch mask to define a pattern region, whereby a hard mask 18 'is formed.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern 19, and then a SAC etching process is performed to etch the insulating film 17 using the hard mask 18 'as an etch mask, as shown in FIG. 1B. Open portions 20 exposing the source / drain regions 16, that is, contact holes, are formed.

In the SAC process, an underlying layer (ie, insulating film 17) is etched using an oxide film and a nitride film having an etching selectivity mainly with respect to a fluorine-based gas.

In the above-described example, the photoresist strip process is performed after the hard mask 18 'pattern is formed. However, the photoresist strip process may be performed after the SAC etching process.

After the SAC etching process and the normal etching process, the etch residues are removed, the bottom area of the open portion 20 is sufficiently secured, and the natural oxide film formed in the region of the substrate 10 constituting the source / drain region 16 is removed. In order to achieve this, a washing step is performed. The cleaning process is carried out using BOE or diluted hydrofluoric acid solution.

Meanwhile, the insulating layer 17 and the hard mask 18 ′, which are the etched layers, have different etching characteristics, and for this purpose, their constituent elements are different from each other. Therefore, the adhesive property at the interface between the insulating film 17 and the hard mask 18 'often maintains a good state, and attack occurs along this poor interface in the cleaning process described above.

FIG. 2 is an SEM photograph showing a process cross section after the SAC process of FIG. 1B, and FIG. 3 is an SEM photograph showing a process cross section after the cleaning process. 4 is a planar SEM photograph showing the lifting of the hard mask generated by the cleaning process.

For example, when the BPSG film is used as the insulating film 17 and the silicon nitride film is used as the hard mask 18 ', there is no problem until the SAC formation process, but the natural oxide film generated at the interface is removed or the polymer by-products generated during the etching process are removed. In order to remove native oxide, a cleaning process is essential.

That is, referring to FIG. 2, after the SAC etching process, no lifting of the hard mask 18 ′ due to poor adhesion at the interface between the insulating layer 17 and the hard mask 18 ′ has not occurred. You can check it.

On the other hand, referring to Figure 3, it can be seen that the interface 'a' between the BPSG film used as the insulating film 17 and the silicon nitride film used as the hard mask 18 'is weak by the cleaning process.

Accordingly, when the interface between the two films is separated, the lifting of the hard mask occurs as shown in FIG. 4, resulting in a poor pattern of the semiconductor device.

The present invention has been proposed to solve the above problems of the prior art, and provides a method for manufacturing a semiconductor device that can prevent the phenomenon that the hard mask is lifted during the cleaning process by improving the poor interface characteristics between the hard mask and the insulating film. For that purpose.

The present invention to achieve the above object, forming an insulating film on a substrate; Surface treating the insulating film to increase the surface roughness of the insulating film; Forming a material layer for a hard mask on the surface treated insulating film; Forming a photoresist pattern on the material layer for the hard mask; Etching the hard mask material layer using the photoresist pattern as an etching mask to form a hard mask; And etching the insulating layer using at least the hard mask as an etch mask to form a predetermined pattern.

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In addition, to achieve the above object, the present invention, forming a neighboring first and second conductive pattern on the substrate; Forming an insulating film on the entire structure including the first and second conductive patterns; Selectively removing the insulating layer to planarize the upper portion of the first and second conductive patterns; Forming a material layer for a hard mask on the planarization entire structure; Forming a photoresist pattern on the material layer for the hard mask; Forming a hard mask by etching the insulating layer for the hard mask using the photoresist pattern as an etching mask; And etching the insulating layer using at least the hard mask as an etch mask to form a predetermined pattern.

The present invention provides a method for forming a pattern by improving or reducing an interface property between a hard mask and an insulating film formed between a photoresist pattern and an insulating film in order to prevent pattern deformation in an etching process using the insulating film as an etched layer. The problem that the hard mask is lifted in the cleaning process performed after the etching process may be solved.

There are three ways to do this.

One). By increasing the roughness by surface treatment of the insulating film to be etched, the interfacial adhesion between the insulating film and the hard mask is improved.

2). A buffer insulating film capable of improving the adhesion between the two films is formed between the insulating film and the hard mask.

3). In the SAC process exposing the conductive patterns such as the gate electrode pattern, the insulating film is planarized with the upper part of the conductive pattern (gate hard mask), and the upper surface of the planarized conductive pattern is directly contacted with the hard mask so that the contact interface between the insulating film and the hard mask is made. Reduce

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5A to 5C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and the semiconductor device manufacturing process of the present invention will be described in detail with reference to the drawing.

Referring to FIG. 5A, a plurality of gate electrode patterns are formed on the substrate 50, and the gate electrode patterns include the gate insulating layer 51, the first and second conductive layers 52 and 53, and the hard mask 54. Has a laminated structure.

The gate insulating film 51 mainly uses an oxide film series, and the first and second conductive films 52 and 53 use a single or combined structure of polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like.

The hard mask 54 prevents the first and second conductive films 52 and 53 from being attacked in a subsequent process such as SAC etching, and also electrically shorts between the first and second conductive films 52 and 53 and the subsequent connection portion. Serves to prevent. For this purpose, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as the hard mask 54 material.

A buffer insulating layer is deposited along the profile in which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 55 on the side of the gate electrode pattern.

The spacer 55 forms an LDD structure source / drain on the substrate 50 on the side of the gate electrode pattern by ion implantation and prevents attack on the side of the gate electrode pattern during the SAC process.

Therefore, the nitride film is formed alone or in various structures such as an oxide film and a nitride film laminated or a nitride film / oxide film / nitride film structure. The nitride film used here includes a silicon oxynitride film or a silicon nitride film.

A source / drain region 56 extended to a predetermined depth from the surface of the substrate 50 is formed in the substrate 50 on the side of the gate electrode pattern or a well (not shown) by ion implantation and thermal diffusion.

In order to prevent the hot carrier effect due to the short channel, a low-level impurity doping and a spacer 55 are formed, followed by a high-level impurity doping to form a conventional structure. .

Subsequently, an insulating film 57 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed.

The insulating film 57 uses an oxide film-based material such as a BPSG film, a BSG film, a PSG film, a TEOS film, or an HDP oxide film.

On the other hand, as the high integration increases the vertical height of the gate electrode pattern, the aspect ratio between the gate electrode patterns increases, resulting in gap-fill defects when the insulating layer 57 is deposited.

In order to prevent this, recently, an SOD film having excellent gap-fill characteristics is applied, and a heat treatment process is performed to densify the film.

Subsequently, in order to improve the adhesion at the contact interface between the material film for hard mask and the insulating film 57, the surface treatment 58 of the insulating film 57 is carried out, so that the characteristics of the surface of the insulating film 57 are indicated as '59'. To change.

As a surface treatment method, the film roughness of the surface of the insulating film 57 is increased by a dry method using a plasma or a wet method using a wet solution to improve the bonding force with the material film for the subsequent hard mask.

In the case of using a plasma, N ₂ O, N ₂ , NH ₃ , O ₂ , O ₃ , Ar, or He is used, and it is preferable to carry out for a time of about 5 seconds to 30 seconds.

When using a wet solution, the ratio of HF and NH ₄ F is 7: 1 to 500: 1 BOE, SC (Standard Cleaning) -1 (mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O), SC- 2 (mixture of HCl, H ₂ O ₂ and H ₂ O) or HF diluted 5: 1 to 500: 1 in water is used.

Subsequently, as shown in FIG. 5B, a hard mask material layer 60 is deposited on the surface-treated insulating film 59 to secure a weak etching resistance of the photoresist in a subsequent SAC process, and then a photo for forming an SAC. The resist pattern 61 is formed.

As the semiconductor device is highly integrated, the DOF of the exposure apparatus is lowered and the thickness of the photoresist is lowered. As the thickness of the photoresist decreases, a problem occurs that the initial pattern shape is deformed as the photoresist pattern is exhausted before the pattern formation is completed.

In order to solve this problem, a technique of forming a hard mask using various materials such as tungsten, tungsten nitride, nitride, or polysilicon is applied between the photoresist pattern 61 and the etched layer (here, the insulating layer 57). .

Therefore, since the hard mask material layer 60 is deposited, since the hard mask material layer 60 is etched with the thickness of the thin photoresist pattern 61, the thickness of the hard mask material layer 60 is low, but the thickness of the interlayer insulation layer is increased. Since the etch selectivity is required for the oxide-based material film mainly used, the nitride material film is mainly used.

Here, in the case where the nitride film is used as the hard mask material film 60, when the nitride film is deposited by the plasma enhanced chemical vapor deposition (PECVD) method, the above-described plasma treatment of the insulating film 57 is performed. In-situ can be performed without breaking the vacuum in the same chamber.

Subsequently, as shown in FIG. 5C, the hard mask material layer 60 is etched using the photoresist pattern 61 as an etch mask to define a pattern region, whereby a hard mask 60 ′ is formed. .

Subsequently, a photoresist strip process is performed to remove the photoresist pattern 61, and then a SAC etching process is performed to etch the insulating film 59 and the insulating film 57 having the hard mask 60 ′ as an etch mask. As shown in FIG. 5C, an open portion 62 that exposes the source / drain region 56, that is, a contact hole, is formed.

In the SAC process, the underlying layer (ie, the insulating film 57) is etched mainly by using an oxide film and a nitride film having an etching selectivity with respect to the fluorine-based gas.

Meanwhile, although the SAC process for forming a plug between the gate electrode patterns is taken as an example, the insulating film is an etched layer, and the present invention may be applied to a general pattern forming process for forming a hard mask on the upper portion and etching the insulating film.

In the above-described example, the photoresist strip process is performed after the hard mask 60 'pattern is formed, but the photoresist strip process may be performed after the SAC etching process.

After the SAC etching process and the normal etching process, the etch residues are removed, the bottom area of the open portion 62 is sufficiently secured, and the natural oxide film formed in the region of the substrate 50 forming the source / drain region 56 is removed. In order to achieve this, a washing step is performed. The cleaning process is carried out using BOE or diluted hydrofluoric acid solution.

In the first embodiment described above, the surface roughness is increased through surface treatment of the insulating film 57 to improve the adhesion property with the hard mask 60 ', thereby preventing the lifting of the hard mask 60' according to the cleaning process. You can see that you can.

FIG. 6 is a planar SEM photograph of FIG. 5C, and it may be confirmed that the pattern is well formed without lifting of the hard mask by the cleaning process.

7A to 7C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. With reference to this, the semiconductor device manufacturing process of the present invention will be described in detail with reference to the same elements as in the first embodiment. The same reference numerals are used for, and a detailed description thereof will be omitted.

Referring to FIG. 7A, a plurality of gate electrode patterns are formed on the substrate 50, and the gate electrode patterns include the gate insulating layer 51, the first and second conductive layers 52 and 53, and the hard mask 54. Has a laminated structure.

A buffer insulating layer is deposited along the profile in which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 55 on the side of the gate electrode pattern.

A source / drain region 56 extending from the surface of the substrate 50 to a predetermined depth is formed on the substrate 50 on the side of the gate electrode pattern by ion implantation and thermal diffusion.

Subsequently, an insulating film 57 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed, and the insulating film 57 uses an oxide film-based material such as a BPSG film, a BSG film, a PSG film, a TEOS film, or an HDP oxide film. .

Subsequently, a buffer insulating film 63 is formed on the insulating film 57 to improve the adhesive force at the contact interface between the material film for hard mask and the insulating film 57.

The buffer insulating layer 63 uses an oxide-based material film to secure poor interfacial adhesion characteristics between the insulating film 57 and the subsequent hard mask, and uses a PECVD method.

At this time, it is preferable to use a power of 100 W to 1 KW using a reaction source such as SiH ₄ , TEOS, O _2, or N ₂ O.

Subsequently, as shown in FIG. 7B, a hard mask material layer 60 is deposited on the buffer insulating layer 63 in order to secure weak etching resistance of the photoresist in a subsequent SAC process, and then a photoresist pattern for forming SAC. Form 61.

Since the hard mask material film 60 is etched with the thickness of the thin photoresist pattern 61, the thickness of the hard mask material layer 60 is low, but a high etching selectivity is required for the oxide film-based material film mainly used for interlayer insulation. The nitride film-based material film is mainly used.

Subsequently, the hard mask material layer 60 is etched using the photoresist pattern 61 as an etch mask to define a pattern region, whereby a hard mask 60 'is formed.

Subsequently, the photoresist strip process is performed to remove the photoresist pattern 61, and then the SAC etching process of etching the buffer insulating film 63 and the insulating film 57 using the hard mask 60 'as an etching mask is performed. As shown in FIG. 7C, an open portion 62 that exposes the source / drain region 56 is formed, that is, a contact hole.

In the SAC process, the underlying layer (ie, the insulating film 57) is etched mainly by using an oxide film and a nitride film having an etching selectivity with respect to the fluorine-based gas.

In the above-described example, the photoresist strip process is performed after the hard mask 60 'pattern is formed. However, the photoresist strip process may be performed after the SAC etching process.

After the SAC etching process and the normal etching process, the etch residues are removed, the bottom area of the open portion 62 is sufficiently secured, and the natural oxide film formed in the region of the substrate 50 forming the source / drain region 56 is removed. In order to achieve this, a washing step is performed. The cleaning process is carried out using BOE or diluted hydrofluoric acid solution.

In the second embodiment described above, the buffer insulating film 63 is formed between the insulating film 57 and the hard mask 60 'to improve the interfacial adhesion characteristics, thereby lifting the hard mask 60' according to the cleaning process. It can be confirmed that it can prevent.

8A to 8C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a third embodiment of the present invention. The semiconductor device manufacturing process of the present invention will be described in detail with reference to the first and second embodiments. The same reference numerals are used for the same components, and detailed description thereof will be omitted.

Referring to FIG. 8A, a plurality of gate electrode patterns are formed on the substrate 50, and the gate electrode patterns include the gate insulating layer 51, the first and second conductive layers 52 and 53, and the hard mask 54. Has a laminated structure.

A buffer insulating layer is deposited along the profile in which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 55 on the side of the gate electrode pattern.

A source / drain region 56 extending from the surface of the substrate 50 to a predetermined depth is formed on the substrate 50 on the side of the gate electrode pattern by ion implantation and thermal diffusion.

Subsequently, an insulating film 57 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed, and the insulating film 57 uses an oxide film-based material such as a BPSG film, a BSG film, a PSG film, a TEOS film, or an HDP oxide film. .

Subsequently, the insulating film 57 is selectively removed 64 so as to be planarized to be substantially the same height as the hard mask 54 of the gate electrode pattern.

The planarization may be performed by performing a CMP process, or may use dry or wet front surface etching, and may plan only a region where the gate electrode pattern is not formed in order to prevent loss of the insulating layer 57 in the region where the gate electrode pattern is not formed. Masking and dry and wet etching can also be performed.

Subsequently, as shown in FIG. 8B, the hard mask material layer 60 is deposited on the entire structure of the gate electrode pattern and the insulating layer 57 to secure the weak etching resistance of the photoresist during the subsequent SAC process. Next, a SAC forming photoresist pattern 61 is formed.

Since the hard mask material film 60 is etched with the thickness of the thin photoresist pattern 61, the thickness of the hard mask material layer 60 is low, but a high etching selectivity is required for the oxide film-based material film mainly used for interlayer insulation. The nitride film-based material film is mainly used.

Subsequently, the hard mask material layer 60 is etched using the photoresist pattern 61 as an etch mask to define a pattern region, whereby a hard mask 60 'is formed.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern 61, and then a SAC etching process is performed to etch the insulating film 57 using the hard mask 60 'as an etch mask, as shown in FIG. 8C. Open portions 62 that expose the source / drain regions 56, that is, contact holes, are formed.

In the SAC process, the underlying layer (ie, the insulating film 57) is etched mainly by using an oxide film and a nitride film having an etching selectivity with respect to the fluorine-based gas.

In the above-described example, the photoresist strip process is performed after the hard mask 60 'pattern is formed. However, the photoresist strip process may be performed after the SAC etching process.

After the SAC etching process and the normal etching process, the etch residues are removed, the bottom area of the open portion 62 is sufficiently secured, and the natural oxide film formed in the region of the substrate 50 forming the source / drain region 56 is removed. In order to achieve this, a washing step is performed. The cleaning process is carried out using BOE or diluted hydrofluoric acid solution.

In the third embodiment, the hard mask 60 'is planarized with the hard mask 54 on the gate electrode pattern to minimize the contact area between the insulating film 57 and the hard mask 60', thereby cleaning the process. It can be seen that the lifting phenomenon of the hard mask 60 'can be prevented.

According to the present invention as described above, in order to prevent pattern deformation in an etching process using an insulating film as an etched layer, an interface property between a hard mask and an insulating film formed between the photoresist pattern and the insulating film is improved or the interface is reduced. In the cleaning process performed after the etching process for forming the pattern, the problem that the hard mask is lifted has been found through the examples.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the gate electrode pattern forming process is taken as an example. However, the present invention may be applied to various conductive patterns having the structure (a structure in which a hard mask and a conductive film are stacked).

The present invention as described above can prevent the deformation of the pattern by inhibiting the lifting of the hard mask, it can be expected an excellent effect that can ultimately improve the yield of the semiconductor device.

Claims (11)

Forming an insulating film on the substrate; Surface treating the insulating film to increase the surface roughness of the insulating film; Forming a material layer for a hard mask on the surface treated insulating film; Forming a photoresist pattern on the material layer for the hard mask; Etching the hard mask material layer using the photoresist pattern as an etching mask to form a hard mask; And Etching the insulating layer using at least the hard mask as an etch mask to form a predetermined pattern Semiconductor device manufacturing method comprising a. The method of claim 1, In the step of surface treatment of the insulating film, A method of manufacturing a semiconductor device, comprising increasing the roughness of the surface of the insulating film by using a plasma containing at least one of N ₂ O, N ₂ , NH ₃ , O ₂ , O ₃ , Ar, or He. The method of claim 1, In the step of surface treatment of the insulating film, BOE, SC-1 (mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O), SC-2 (HCl, H ₂ O ₂ and H) with a ratio of HF to NH ₄ F 7: 1 to 500: 1 Method for manufacturing a semiconductor device characterized in that to increase the roughness of the surface of the insulating film using a wet solution of any one of a mixed solution of ₂ O) or HF diluted 5: 1 to 500: 1 in water. delete delete delete Forming neighboring first and second conductive patterns on the substrate; Forming an insulating film on the entire structure including the first and second conductive patterns; Selectively removing the insulating layer to planarize the upper portion of the first and second conductive patterns; Forming a material layer for a hard mask on the planarization entire structure; Forming a photoresist pattern on the material layer for the hard mask; Etching the hard mask material layer using the photoresist pattern as an etching mask to form a hard mask; And Etching the insulating layer using at least the hard mask as an etch mask to form a predetermined pattern Semiconductor device manufacturing method comprising a. The method of claim 7, wherein In the planarizing step, a method of manufacturing a semiconductor device, characterized in that using the chemical mechanical polishing or surface etching process. The method of claim 7, wherein The conductive pattern includes a gate electrode pattern. The method according to claim 1 or 7, The insulating film is a semiconductor device manufacturing method comprising an oxide film-based material film. The method according to claim 1 or 7, The hard mask material layer may include any one of tungsten, tungsten nitride, nitride, and polysilicon.

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