KR20070093672A - Method for forming a pattern and method for forming a floating gate of the non-volatile memory device using the same - Google Patents

Abstract

A pattern forming method and a method for forming a floating gate in a nonvolatile memory device using the same are provided to prevent the generation of seams at a material layer for forming a pattern by using a wet etching process. First patterns are repeatedly formed on a substrate(100). The first pattern has a sidewall with a negative slope. The first pattern is made of a first material. First opening portions(110a) between the first patterns are filled with a second material with a different etch ratio from that of the first material, so that second patterns are formed on the resultant structure. Pre-second opening portions are formed between the second patterns by removing the first patterns from the resultant structure using a first wet etching process. Second opening portions with vertical sidewalls are formed by removing partially upper sidewalls of the second patterns using a second wet etching process. Third patterns are formed on the resultant structure by filling the second opening portions with a third material.

Description

Method for forming a pattern and method for forming a floating gate of the non-volatile memory device using the same

1A to 1F are cross-sectional views illustrating a method of forming a pattern according to an embodiment of the present invention.

2A to 2H are cross-sectional views illustrating a method of forming a floating gate in a nonvolatile memory device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 and 200: semiconductor substrate 102: first material layer

104: first pattern 106: first opening

108: second pattern 110a, 214a: first opening

204: nitride film for hard mask 210: trench

212a: device isolation layer pattern 218: floating gate

The present invention relates to a pattern forming method and a floating gate forming method of a nonvolatile memory device using the same, and more particularly, to a pattern method capable of preventing the generation of seams and a floating gate forming method of the nonvolatile memory device using the same. It is about. Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable and programmable ROM (EEPROM) or flash memory capable of electrically inputting / outputting data. The flash memory device has a structure for electrically controlling input and output of data by using F-N tunneling or channel hot electron injection.

Looking at the flash memory device from a circuit point of view, the NAND type in which n cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. Each cell transistor can be classified into a NOR type in which parallel connection is made between a bit line and a ground line. The NOR type is advantageous for high speed operation, while the NAND type is advantageous for high integration.

Flash memory cells generally have a vertically stacked gate structure with floating gates formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate.

Typically, the stacked gate structure of the NAND type flash memory cell is provided with floating gate electrodes on each of the line type active regions. The floating gate electrode should be formed to be exactly aligned on the active region. However, as the design rule of the memory cell becomes smaller and smaller, the area of the active region is further reduced, and the threshold of the floating gate electrode is also smaller. Therefore, the misalignment problem between the floating gate electrode and the active region is seriously raised.

In order to reduce the problem, a method of forming a floating gate from self-aligned polysilicon (SAP) is used. In this case, an opening is formed in a region where the floating gate is to be formed, and the method proceeds to embedding polysilicon in the opening.

However, when embedding polysilicon in the opening, a seam may be generated in which the polysilicon is not filled in the central portion of the opening due to the high step coverage deposition characteristic of the polysilicon. In addition, since the opening has a negative slope having a wider bottom portion than the inlet portion, polysilicon is filled along the sidewall and the bottom of the opening, and the opening portion of the opening portion is blocked without polysilicon being deposited at the center portion. As it occurs, the seams are generated more frequently.

Undesirable oxides may be formed in the site where the seam is generated by a subsequent process, and there is a problem of deteriorating characteristics of the semiconductor device.

A first object of the present invention for solving the above problems is to provide a pattern forming method that can prevent the formation of seams by forming an opening with a vertical profile of the side wall.

A second object of the present invention for solving the above problems is to provide a floating gate forming method of a nonvolatile memory device capable of preventing the generation of seams using the pattern forming method.

According to an aspect of the present invention, there is provided a method of forming a pattern structure, repeatedly forming first patterns having inclined sidewalls having a width of an upper portion greater than a width of a lower portion on a substrate, and A second material having a different etch rate with respect to the first material is buried in the first openings corresponding to the first patterns to form second patterns, and the first pattern is removed by a first wet etching process. Subsequently, after forming the preliminary second openings between the second patterns, the second sidewalls of the second patterns may be partially removed by a second wet etching process to form second openings having vertical sidewalls, and the second openings may be formed. A third material is embedded in the opening to form third patterns.

The first material includes a nitride, the second material includes an oxide, and the first wet etching process uses a H ₃ PO ₄ strip process.

In addition, the first material includes an oxide, the second material includes polysilicon, and the first wet etching process uses HF or LAL Chemical.

The second wet etching process uses SC-1 (NH ₄ OH: H ₂ O ₂ : H ₂ O), and the first wet etching process and the second wet etching process are in-situ. Is performed.

According to another aspect of the present invention, there is provided a method of forming a floating gate of a nonvolatile memory device in which a hard mask pattern is formed on a semiconductor substrate, and the substrate is etched using the hard mask pattern as an etching mask. By forming a device isolation trench having an upper width greater than that of a lower width, an oxide having a different etching rate with respect to the hard mask pattern is deposited to fill the device isolation trench to form a device isolation film pattern. The hard mask pattern is removed by a first wet etching process to form a preliminary opening that exposes the substrate between the device isolation layer patterns. Subsequently, a portion of an upper portion of the device isolation layer pattern is removed to form an opening having vertical sidewalls by a second wet etching process, and a tunnel oxide layer is formed on the substrate exposed through the opening, and the tunnel oxide layer and the device are formed. After forming the conductive layer for the floating gate on the separator pattern, the floating gate is formed by planarizing the conductive layer for the floating gate so that the device isolation layer is exposed.

The hard mask pattern may include a nitride, and the first wet etching process may use a phosphate strip (H ₃ PO ₄ strip) process. In addition, the second wet etching process uses SC-1 (NH ₄ OH: H ₂ O ₂ : H ₂ O), and the first wet etching process and the second wet etching process are performed in-situ. .

The pattern forming method and the floating gate forming method of the nonvolatile memory device using the same according to the present invention configured as described above can prevent seam or the like from occurring.

Hereinafter, a pattern structure forming method and a floating gate forming method of a nonvolatile semiconductor device using the same according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is limited to the following embodiments. Those skilled in the art will appreciate that the present invention may be embodied in various other forms without departing from the spirit of the invention. In the accompanying drawings, the dimensions of semiconductor substrates, layers (films), patterns, or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pattern, or structure is referred to as being formed on, on or under a semiconductor substrate, each layer (film), region, or patterns. , Means that regions, patterns or structures are directly formed on or below the semiconductor substrate, each layer (film), region or patterns, or other layers (films), other regions, other patterns or other structures are on the substrate. It may be formed additionally.

Example 1

1A to 1F are cross-sectional views illustrating a method of forming a pattern according to an embodiment of the present invention.

Referring to Figure 1A. The first material layer 102 including the first material is formed on the semiconductor substrate 100.

The first material may comprise an oxide or nitride. In this case, an insulating layer or a conductive layer may be further formed on the substrate.

The first material layer 102 may include a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an atomic layer deposition (ALD) process, and sputtering. It is formed using a sputtering process, a pulsed laser deposition (PLD) process, or the like.

1b. The first material layer 102 is etched to repeatedly form a first pattern 104 including a first opening 106 having an inclined sidewall having a width greater than that of the lower portion.

Specifically, a photoresist pattern (not shown) for selectively exposing the first material layer 102 is formed on the first material layer 102. The first opening 106 is formed by etching the first material layer 102 through an etching process using the photoresist pattern as an etching mask. Examples of the etching process include a dry etching process using a plasma, a reactive ion etching process, and the like. In general, the side surface of the opening formed by performing the anisotropic etching process as described above has a predetermined slope, and the sidewall of the first opening 106 also has a predetermined slope according to the characteristics of the anisotropic etching process as described above. . That is, the first opening 106 has an upper width wider than the lower width.

Subsequently, the photoresist pattern is removed through an ashing process or a strip process.

Referring to Figure 1C. A second pattern 108 may be formed to fill the first opening with a second material having an etch rate different from that of the first material.

Specifically, the first opening 106 is sufficiently filled with a second material having an etching rate different from that of the first material on the first pattern 104.

 When the first pattern 104 is formed of nitride, the second pattern 108 may be formed of oxide. Alternatively, when the first pattern 104 includes an oxide, the second pattern 108 includes polysilicon.

Specifically, the oxide may be formed by chemical vapor deposition of an oxide film having excellent gap filling characteristics such as USG (Undoped Silicate Glass), O3-TEOS USG (O3-Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or High Density Plasma (HDP) oxide film. It is formed by a chemical vapor deposition (CVD) method.

The nitride film may be a low pressure chemical vapor deposition (LPCVD) process or plasma enhanced chemical vapor deposition using silicon nitride or silicon oxynitride, such as SiH ₂ Cl ₂ gas, SiH ₄ gas, NH ₃ gas, or the like. It may be formed by performing a vapor deposition (PECVD) process.

In addition, the polysilicon film is a chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PE-CVD) process, high density plasma chemical vapor deposition (HDP-CVD) process, atomic layer deposition (ALD) process, sputtering Process, or pulsed laser deposition (PLD) process or the like.

Subsequently, the upper portion of the second material layer is removed through a planarization process such as an etch back or chemical mechanical polishing (CMP) process so that the upper surface of the first pattern 104 is exposed. 2 Pattern 108 is completed.

Referring to FIG. 1D. The first pattern 104 is removed by a first wet etching process to form a preliminary second opening 110 between the second patterns 108.

According to an embodiment of the present invention, when the first pattern 104 includes a nitride and the second pattern 108 includes an oxide or the like, a phosphoric acid strip (H ₃ PO ₄ strip) process is performed. The first pattern 104 may be selectively removed.

According to another embodiment of the present invention, when the first pattern 104 includes an oxide and the second pattern 108 includes polysilicon, HF or HF, NH ₄ F and DI (deionized water). The first pattern 104 may be selectively removed using a LAL solution including

The preliminary second opening formed through the process is formed such that the opening width of the upper portion is wider than the opening width of the lower portion.

Referring to FIG. 1E, the second sidewalls 110a having vertical sidewalls may be formed by partially removing the upper sidewalls of the second patterns by a second wet etching process.

An etching solution generally known as a standard cleaning solution (SC-1) may be used for the second wet etching process, and preferably, a new standard cleaning solution (NSC-1) may be used.

The NSC-1 includes NH ₄ OH, H ₂ O _2, and H ₂ O having a molar ratio of 3 to 10: 1: 60 to 200. In particular, the NSC-1 preferably comprises NH ₄ OH, H ₂ O ₂ and H ₂ O having a molar ratio of 4: 1: 95.

The first wet etching process and the second wet etching process may be performed in-situ.

When the second wet etching process is performed, the sidewalls of the second opening are changed to be perpendicular to the vertical direction by removing the second patterns positioned on the upper portion rather quickly. However, when the second wet etching process is excessively performed, the second opening 110a may be formed to have a sidewall having a positive slope.

Through the second wet etching process, the etching residue remaining in the second opening 110a may be removed. In addition, during the second wet etching process, the height of the second pattern 112 may be slightly lowered, and the edge portion may be gently etched.

Referring to FIG. 1F. A third material is buried in the second opening 110a to form a third pattern 114.

A third material layer (not shown) including a third material is formed on the semiconductor substrate exposed through the second opening having sidewalls perpendicular to the substrate by the second wet etching process.

Subsequently, the third material layer may be planarized, such as a CMP process, to complete the third pattern 114. As the width of the upper portion and the lower portion of the sidewall of the second opening 110a is substantially the same, it is possible to suppress the generation of voids in the third pattern 114.

Example 2

2A to 2H are cross-sectional views illustrating a method of forming a floating gate of a nonvolatile semiconductor device according to another embodiment of the present invention.

Referring to FIG. 2A, a hard mask pattern is formed on a semiconductor substrate 200.

Specifically, a pad oxide film 202 is formed on a semiconductor substrate 200 such as a silicon wafer, and a hard mask nitride film 204 is formed on the pad oxide film 202 to form a hard mask pattern.

The pad oxide layer 102 may be formed of silicon oxide, and may be formed through a thermal oxidation process, a chemical vapor deposition (CVD) process, or the like.

The nitride film 104 may be formed of silicon nitride, and may be formed through an LPCVD process using a SiH 2 Cl 2 gas, a SiH 4 gas, an NH 3 gas, or a plasma enhanced chemical vapor deposition (PECVD) process.

Referring to FIG. 2B, a photoresist pattern (not shown) for selectively exposing the nitride film 204 is formed on the nitride film 204.

The nitride film pattern 208 is formed through an etching process using the photoresist pattern as an etching mask. Examples of the etching process include a dry etching process using a plasma, a reactive ion etching process, and the like. In general, the side surface of the opening formed by performing the above anisotropic etching process has a predetermined inclination, and the first opening 206 defined by the mask pattern 208 also has the characteristics of the above anisotropic etching process. Has a predetermined slope. In detail, the first opening 206 has an upper width wider than a lower width.

The photoresist pattern is removed through an ashing process and a stripping process after forming the mask pattern 208.

In this case, the portion of the substrate W exposed by the photoresist pattern becomes a field region, and the portion of the substrate W masked by the photoresist pattern becomes an active region.

In this case, an organic antireflection film (not shown) may be further formed on the nitride film 208 for the hard mask. The organic antireflective film is a film for preventing the sidewall profile of the photoresist pattern from being deteriorated by diffuse reflection in a subsequent photographic process. An example of the organic antireflection film may be a silicon oxynitride film (SiON).

Referring to FIG. 2C, the substrate 200 is etched using the hard mask pattern as an etch mask to form a device isolation trench 210 having an upper width greater than a lower width.

Specifically, by performing an anisotropic etching process using the mask pattern 208 as an etch mask, the surface portions of the pad oxide layer 202 and the field region of the semiconductor substrate 200 are etched to cross the semiconductor substrate 200. An isolation trench 210 is formed in the first direction.

Subsequently, although not shown, a thermal oxide layer (not shown) may be selectively formed inside the trench 210. In more detail, the thermal oxide layer thermally oxidizes the surface of the trench 120 in order to cure surface damage generated during the dry etching process, and thus, the inside of the trench 210 in a very thin thickness. Is formed.

In addition, an insulating film liner (not shown) may be formed on an inner side surface and a bottom surface of the trench 210 in which the thermal oxide layer is formed to a thickness of several hundreds. The insulating film liner is formed to reduce stress in the device isolation layer embedded in the trench 120 by a subsequent process and to prevent impurity ions from penetrating into the field region. The insulating film liner should be formed of a material having a high etching selectivity with respect to a silicon oxide film, which will be described later, under specific etching conditions. For example, the insulating film liner may be formed of silicon nitride (SiN).

Referring to FIG. 2D, a preliminary device isolation layer pattern 212 is formed by depositing an oxide having a different etching rate with respect to the hard mask pattern to fill the device isolation trench 210.

The trench 210 is filled with a material such as an oxide having a different etching rate with respect to the mask pattern 208. Specifically, the gap filling characteristics such as Undoped Silicate Glass (USG), O3-TEOS USG (O3-Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or High Density Plasma (HDP) oxide film are excellent to fill the trench 210. The oxide film is deposited by a chemical vapor deposition (CVD) method to form a device isolation film (not shown).

The upper portion of the isolation layer is removed through a planarization process such as an etch back or chemical mechanical polishing (CMP) process so that the upper surface of the mask pattern 208 is exposed. A preliminary device isolation layer pattern 212 that functions as an isolation layer and defines an active region of the semiconductor substrate 200 is completed.

Referring to FIG. 2E, a preliminary second opening 214 exposing the substrate 200 between the device isolation layer patterns is formed by removing the hard mask pattern 208 by a first wet etching process.

Specifically, the mask pattern 208 and the pad oxide layer 202 are removed to form a preliminary second opening 214 exposing the active region defined by the preliminary isolation layer pattern 212.

In the first wet etching process according to an embodiment of the present invention, the mask pattern 116 may be removed through a H3PO4 strip process using an etching solution containing phosphoric acid, and the diluted hydrofluoric acid solution may be used. The pad oxide layer 102 may be removed.

Referring to FIG. 2F, a portion of an upper portion of the preliminary isolation layer pattern 212 is removed by a second wet etching process to form a second opening 214a having vertical sidewalls.

The process of removing a portion of the upper portion of the preliminary isolation layer pattern 212 may be performed through a wet etching process. For example, the etchant used in the wet etching process may include NH 4 OH, H 2 O 2 and H 2 O. Specifically, in the wet etching process, an etchant commonly known as SC-1 may be used, and preferably NSC-1 may be used.

During the cleaning process, the side portion of the device isolation layer pattern 212a is partially etched to extend the width of the second opening 214a, and the side surface of the device isolation layer pattern 212a is substantially vertical. Has That is, the upper width and the lower width of the expanded second opening 214a are substantially the same.

In addition, when the height of the device isolation layer pattern 212a may be slightly lowered by the second wet etching process, edges of the device isolation layer pattern 212a may be smoothly formed. The etching residue remaining in the second opening 214a may be removed through the second wet etching process.

Referring to FIG. 2G, a tunnel oxide layer 216 is formed on the semiconductor substrate 200 exposed through the second opening 214a where the sidewalls are vertical.

As the tunnel oxide layer 216, a silicon oxide layer formed through thermal oxidation may be used. As another example of the tunnel oxide layer 216, a fluorine-doped silicon oxide layer, a carbon-doped silicon oxide layer, or a low-k material layer may be used.

The low dielectric constant material film may include polyallyl ether resin, cyclic fluorine resin, siloxane copolymer, polyallyl fluoride resin, polypentafluorostyrene, polytetrafluorostyrene resin, fluorinated polyimide resin, polynaphthalene fluoride, and polyside resin. It may be made of an organic polymer such as. The organic polymer may be formed by processes such as PECVD, high density plasma chemical vapor deposition (HDP-CVD), atmospheric pressure chemical vapor deposition (APCVD), spin coating, and the like.

Referring to FIG. 2H, a floating gate conductive layer (not shown) is formed on the tunnel oxide layer 216 and the device isolation layer pattern 212a to sufficiently fill the second opening 214a. The conductive layer may be made of impurity doped polysilicon.

The impurity doped polysilicon may be formed through an LPCVD process and an impurity doping process. In detail, the first conductive layer 126 made of impurity doped polysilicon may be formed by simultaneously performing an impurity doping process by an in-situ method while forming the polysilicon layer through the LPCVD process. Alternatively, the polysilicon layer may be formed through the LPCVD process, and the polysilicon layer may be formed as the first conductive layer 126 through the impurity doping process. Examples of the impurity doping process include an ion implantation process or an impurity diffusion process.

The second opening 214a has the same width as that of the upper portion. Therefore, it is possible to suppress the generation of voids while filling the second opening 214a by forming the conductive layer on the tunnel oxide film 216 and the device isolation layer pattern 212a. In addition, by performing the above process, it is possible to form a device isolation film having a predetermined predetermined height even in a highly integrated semiconductor device.

The floating gate 218 is formed on the tunnel oxide film 216 by removing the upper portion of the conductive layer through a planarization process such as a CMP process. The CMP process may be performed to expose the top surface of the device isolation layer pattern 214a.

According to the embodiments of the present invention as described above, it is possible to prevent the problem that the seam or the like is generated in the material layer for forming a pattern by performing a wet etching process. In addition, using the pattern forming method as described above Seaming can be minimized in the process of forming the floating gate of the nonvolatile semiconductor device. Therefore, the operating performance of the memory semiconductor device can be improved.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to vary the present invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that modifications and variations can be made.

Claims (12)

Repeatedly forming first patterns of a first material on the substrate, the inclined sidewalls of which a width of the upper part is wider than a width of the lower part; Forming second patterns by filling a second material having a different etching rate with respect to the first material in a first opening corresponding to the first patterns; Removing the first pattern by a first wet etching process to form a preliminary second opening between the second patterns; Partially removing the upper sidewalls of the second patterns by a second wet etching process to form a second opening having vertical sidewalls; And And embedding a third material in the second opening to form third patterns. The method of claim 1, wherein the first material comprises nitride and the second material comprises an oxide. The method of claim 2, wherein the first wet etching process comprises a phosphoric acid strip (H 3 PO 4 strip) process. The method of claim 1, wherein the first material comprises an oxide and the second material comprises polysilicon. The method of claim 4, wherein the first wet etching process uses HF or LAL Chemical. The method of claim 1, wherein the second wet etching process uses SC-1 (NH 4 OH: H 2 O 2: H 2 O). The method of claim 1, wherein the first wet etching process and the second wet etching process are performed in-situ. Forming a hard mask pattern on the semiconductor substrate; Etching the substrate using the hard mask pattern as an etch mask to form a trench for device isolation, the width of which is greater than the width of the lower portion; Forming an isolation layer pattern by depositing an oxide having a different etching rate with respect to the hard mask pattern to fill the isolation isolation trench; Removing the hard mask pattern by a first wet etching process to form a preliminary opening that exposes a substrate between the device isolation layer patterns; Removing a portion of the upper portion of the device isolation layer pattern by a second wet etching process to form an opening having vertical sidewalls; Forming a tunnel oxide film on the substrate exposed through the opening; Forming a conductive layer for a floating gate on the tunnel oxide layer and the device isolation layer pattern; And And forming a floating gate by planarizing the conductive film for the floating gate so that the device isolation layer is exposed. 10. The method of claim 8, wherein the hard mask pattern comprises nitride. 10. The method of claim 9, wherein the first wet etching process uses a phosphate strip (H3PO4 strip) process. The method of claim 8, wherein the second wet etching process uses SC-1 (NH 4 OH: H 2 O 2: H 2 O). 10. The method of claim 8, wherein the first wet etching process and the second wet etching process are performed in-situ.

Images