JPH03211885A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH03211885A
JPH03211885A JP2007470A JP747090A JPH03211885A JP H03211885 A JPH03211885 A JP H03211885A JP 2007470 A JP2007470 A JP 2007470A JP 747090 A JP747090 A JP 747090A JP H03211885 A JPH03211885 A JP H03211885A
Authority
JP
Japan
Prior art keywords
trench
groove
oxide film
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007470A
Other languages
Japanese (ja)
Inventor
Masahiko Miyano
宮野　昌彦
Toshihiko Uno
宇野　利彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2007470A priority Critical patent/JPH03211885A/en
Publication of JPH03211885A publication Critical patent/JPH03211885A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To reduce a capacitance between the gate and the drain of a field effect transistor and to perform a high speed operation by increasing the thickness of an insulating film in the bottom of a groove thicker than that of an insulating film of the sidewall of the groove. CONSTITUTION:An oxide film 21 formed in a bottom of a groove of a thermal oxide film formed in a groove is formed thicker than an oxide film 2 formed on the sidewall of the groove. Thus, a capacity between a gate electrode 3 formed of polysilicon and a drain region 11 can be reduced. Since the film 21 of the bottom of the groove is formed thicker than the film 2 of the sidewall of the groove, a capacitance between the gate and the drain of a field effect transistor can be reduced, and a high speed operation can be performed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、表面を絶縁膜で被膜した垂直溝を有する半導
体装置の構造及び製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure and manufacturing method of a semiconductor device having a vertical groove whose surface is coated with an insulating film.

従来の技術 従来、この種の半導体装置は第４図に示すような構成で
あった。第４図において半導体基板１に形成した垂直溝
に形成する熱酸化ＩＩＩ　１０の膜厚は溝の側壁と溝の
底部とにおいて同じ膜厚になっていた。従って、第３図
に示すように、この熱酸化膜を形成した垂直溝部をポリ
シリコンで埋込んでつくられた従来の垂直溝型電界効果
トランジスタでは、ゲート絶縁膜となる溝側壁の酸化膜
９の厚さとドレイン層１１とゲート電極３との重なり容
量の要因となる溝底部の酸化膜９１の厚さは同じ厚さに
なる。一般に、ゲート酸化膜は薄く設計されるため、ド
レイン・ゲート間容量が増加する結果になっていた。2. Description of the Related Art Conventionally, this type of semiconductor device has had a configuration as shown in FIG. In FIG. 4, the thickness of the thermally oxidized III film 10 formed in the vertical trench formed in the semiconductor substrate 1 was the same on the sidewalls of the trench and the bottom of the trench. Therefore, as shown in FIG. 3, in a conventional vertical trench field effect transistor in which the vertical trench in which the thermal oxide film is formed is filled with polysilicon, the oxide film 9 on the trench sidewall, which becomes the gate insulating film, is The thickness of the oxide film 91 at the bottom of the groove, which is a factor in the overlap capacitance between the drain layer 11 and the gate electrode 3, is the same. Generally, the gate oxide film is designed to be thin, resulting in an increase in drain-gate capacitance.

発明が解決しようとする課題 このような従来の構成では、溝部絶縁膜の厚さを側壁と
底部とで変えることは困難であった。即ち、絶縁膜を被
膜した垂直溝を有する半導体装置、きくにこの溝部をポ
リシリコンで埋込んだ垂直溝型電界効果トランジスタで
は、溝底部の酸化膜はゲート・ドレイン間容量を構成す
るため、高速動作のためにはこの部分の容量は大きくな
い方が良い。しかし、溝部に熱酸化によって酸化膜を形
成する場合、溝側壁お溝底部は同じ膜厚になり、異なっ
た厚みにっくるこ古は不可能であった。Problems to be Solved by the Invention In such a conventional structure, it is difficult to change the thickness of the trench insulating film between the side walls and the bottom. In other words, in a semiconductor device having a vertical trench coated with an insulating film, or in a vertical trench field effect transistor in which the trench is buried with polysilicon, the oxide film at the bottom of the trench constitutes a capacitance between the gate and drain, so that high-speed For proper operation, the capacity of this part should not be large. However, when an oxide film is formed in the trench by thermal oxidation, the film thickness is the same on the trench side walls and the trench bottom, making it impossible to coat the trench with different thicknesses.

本発明はこのような課題を解決するもので、溝底部と溝
側壁部の絶縁膜の厚みを変えて形成させることを目的と
するものである。The present invention is intended to solve these problems, and aims to form an insulating film with different thicknesses at the trench bottom and trench sidewalls.

課題を解決するための手段 この課題を解決するために、本発明では溝底部の絶縁膜
厚を、溝側壁の絶縁膜厚より厚くすることでゲート・ド
レイン間容量を低減している。そのために溝側壁にのみ
ＳｉＮを残し、その後熱酸化により溝底部に厚い酸化膜
を形成したものである。Means for Solving the Problem In order to solve this problem, in the present invention, the gate-drain capacitance is reduced by making the insulating film at the bottom of the trench thicker than the insulating film at the side wall of the trench. For this purpose, SiN is left only on the side walls of the trench, and then a thick oxide film is formed at the bottom of the trench by thermal oxidation.

作用 この構成により、溝底部の絶縁膜を溝ｆｌＩＩＩ壁の絶
縁膜よりも厚くすることができるので、電界効果型トラ
ンジスタのゲート・ドレイン間容量を低減でき、高速動
作が可能となる。Effect: With this configuration, the insulating film at the bottom of the trench can be made thicker than the insulating film at the wall of the trench flIII, so the gate-drain capacitance of the field effect transistor can be reduced and high-speed operation can be achieved.

実施例 第１図は本発明の一実施例による半導体装置である垂直
溝型電界効果トランジスタ装置の構成を示す。溝部に形
成された熱酸化膜は、溝底部に形成された酸化膜２１の
方が溝側壁に形成された酸化膜２より厚くなっている。Embodiment FIG. 1 shows the structure of a vertical trench field effect transistor device which is a semiconductor device according to an embodiment of the present invention. Regarding the thermal oxide film formed in the trench, the oxide film 21 formed at the bottom of the trench is thicker than the oxide film 2 formed on the side walls of the trench.

このためポリシリコンで形成されたゲート電極３とドレ
イン領域１１との間の容量は、溝側壁と溝底部の酸化膜
厚が同じである従来構造に比べ大幅に低減できる。なお
、４はリース領域、５は基板ソース領域を示している。Therefore, the capacitance between the gate electrode 3 made of polysilicon and the drain region 11 can be significantly reduced compared to the conventional structure in which the oxide film thicknesses on the trench side walls and the trench bottom are the same. Note that 4 indicates a lease region and 5 indicates a substrate source region.

第２図は本発明による製造方法の一実施例である。垂直
溝を有するドレイン領域となる半導体基板１に予備の酸
化膜６を数百人形成し、次いで、減圧ＣＶＤ法によって
ＳｉＮ膜を５００〜３０００人成長させ同図（ｂ）に示
す構造にする。この状態の半導体基板１をＣＦＡ系ガス
を用いた反応性イオンエツチング法によりエツチングす
ると同図（Ｃ）に示すように、溝の側壁にのみＳｉＮ膜
７を残すことができる。その後、熱酸化し、さらにリン
酸によってＳｉＮ膜７を除去すれば同図（ｄ）に示す構
造となる。即ち、垂直溝部に形成した酸化膜の膜厚は、
溝底部に形成された酸化膜８の方が溝側壁に形成された
酸化膜６より厚（なっている。なお、ここでフッ化水素
容液によって溝側壁の予備の酸化膜６を除去し、新たに
所望の膜厚のゲート酸化１ｌＩＪを熱酸化によって形成
することも可能である。FIG. 2 shows an embodiment of the manufacturing method according to the present invention. Several hundred preliminary oxide films 6 are formed on the semiconductor substrate 1, which will become the drain region having a vertical groove, and then 500 to 3000 SiN films are grown by low-pressure CVD to form the structure shown in FIG. 3(b). When the semiconductor substrate 1 in this state is etched by a reactive ion etching method using a CFA-based gas, the SiN film 7 can be left only on the side walls of the grooves, as shown in FIG. Thereafter, thermal oxidation is performed, and the SiN film 7 is removed using phosphoric acid, resulting in the structure shown in FIG. 4(d). In other words, the thickness of the oxide film formed in the vertical groove is:
The oxide film 8 formed on the trench bottom is thicker than the oxide film 6 formed on the trench sidewalls. Here, the preliminary oxide film 6 on the trench sidewalls is removed using a hydrogen fluoride solution. It is also possible to newly form gate oxide 1lIJ with a desired thickness by thermal oxidation.

発明の効果 以上のように本発明によれば、電界効果型トランジスタ
のゲート・ドレイン間容量を低減でき高速動作が可能と
なる。また、本発明の製造方法によれば、垂直溝に形成
する絶縁膜の膜厚を溝側壁と溝底部で異なる膜厚に形成
することができる。Effects of the Invention As described above, according to the present invention, the gate-drain capacitance of a field effect transistor can be reduced and high-speed operation can be achieved. Further, according to the manufacturing method of the present invention, the thickness of the insulating film formed in the vertical trench can be different between the trench side walls and the trench bottom.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例による電界効果トランジスタ
の断面図、第２図は本発明の製造方法の一実施例を示す
製造工程図、第３図は従来構造の断面図、第４図は従来
の製造方法の製造工程図である。 １・・・・・・半導体基板、２，２１・・・・・・酸化
膜、３・・・・・・ゲート電極、４・・・・・・ソース
領域、５・・・・・・基板ソース領域、６・・・・・・
酸化膜、７・・・・・・ＳｉＮ膜５８・・・・・・酸化
膜、１１・・・・・・ドレイン領域。FIG. 1 is a sectional view of a field effect transistor according to an embodiment of the present invention, FIG. 2 is a manufacturing process diagram showing an embodiment of the manufacturing method of the present invention, FIG. 3 is a sectional view of a conventional structure, and FIG. 4 1 is a manufacturing process diagram of a conventional manufacturing method. 1... Semiconductor substrate, 2, 21... Oxide film, 3... Gate electrode, 4... Source region, 5... Substrate Source area, 6...
Oxide film, 7... SiN film 58... Oxide film, 11... Drain region.

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板に形成した垂直溝部の側壁と溝底部の
絶縁膜の膜厚が異なることを特徴とする半導体装置。(1) A semiconductor device characterized in that the sidewalls of a vertical groove formed in a semiconductor substrate and the insulating film at the bottom of the groove have different thicknesses. （２）絶縁膜を有した垂直溝部をポリシリコンで埋込み
、ゲート電極として利用したことを特徴とする垂直溝型
電界効果トランジスタ型の半導体装置。(2) A vertical trench field effect transistor type semiconductor device characterized in that a vertical trench portion having an insulating film is filled with polysilicon and used as a gate electrode. （３）垂直溝部を有する半導体基板にＳｉＮ膜を形成し
、このＳｉＮ膜を反応性イオンエッチングによって溝側
壁にのみ残し、次いで熱酸化することを特徴とする請求
項１または請求項２記載の半導体装置の製造方法。(3) The semiconductor according to claim 1 or claim 2, characterized in that a SiN film is formed on a semiconductor substrate having a vertical groove, the SiN film is left only on the side walls of the groove by reactive ion etching, and then thermally oxidized. Method of manufacturing the device.
JP2007470A 1990-01-17 1990-01-17 Semiconductor device and manufacture thereof Pending JPH03211885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007470A JPH03211885A (en) 1990-01-17 1990-01-17 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007470A JPH03211885A (en) 1990-01-17 1990-01-17 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03211885A true JPH03211885A (en) 1991-09-17

Family

ID=11666683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007470A Pending JPH03211885A (en) 1990-01-17 1990-01-17 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03211885A (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032335A (en) * 1996-04-10 1998-02-03 Harris Corp Improved type trench mos gate device
WO2003015180A3 (en) * 2001-08-10 2003-11-06 Siliconix Inc Mis device having a trench gate electrode and method of making the same
JP2004507092A (en) * 2000-08-16 2004-03-04 フェアチャイルド　セミコンダクター　コーポレイション Thick oxide layer at bottom of trench structure in silicon
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
WO2005053032A3 (en) * 2003-11-29 2005-08-25 Koninkl Philips Electronics Nv Trench insulated gate field effect transistor
US7009247B2 (en) 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US7028139B1 (en) 2003-07-03 2006-04-11 Veritas Operating Corporation Application-assisted recovery from data corruption in parity RAID storage using successive re-reads
US7033876B2 (en) 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
JP2007242943A (en) * 2006-03-09 2007-09-20 Fuji Electric Device Technology Co Ltd Process for fabrication of mos semiconductor device
US7291884B2 (en) 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
JP2008004686A (en) * 2006-06-21 2008-01-10 Denso Corp Method of manufacturing semiconductor device
US7494876B1 (en) 2005-04-21 2009-02-24 Vishay Siliconix Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
US7868381B1 (en) 2002-03-22 2011-01-11 Vishay-Siliconix Structures of and methods of fabricating trench-gated MIS devices
US8598654B2 (en) 2011-03-16 2013-12-03 Fairchild Semiconductor Corporation MOSFET device with thick trench bottom oxide
JP2014045223A (en) * 2011-04-12 2014-03-13 Denso Corp Semiconductor device manufacturing method
US9136335B2 (en) 2011-04-12 2015-09-15 Denso Corporation Semiconductor device having a trench gate structure and manufacturing method of the same
US9419129B2 (en) 2009-10-21 2016-08-16 Vishay-Siliconix Split gate semiconductor device with curved gate oxide profile
US9425305B2 (en) 2009-10-20 2016-08-23 Vishay-Siliconix Structures of and methods of fabricating split gate MIS devices
US9577089B2 (en) 2010-03-02 2017-02-21 Vishay-Siliconix Structures and methods of fabricating dual gate devices
US10234486B2 (en) 2014-08-19 2019-03-19 Vishay/Siliconix Vertical sense devices in vertical trench MOSFET
US11114559B2 (en) 2011-05-18 2021-09-07 Vishay-Siliconix, LLC Semiconductor device having reduced gate charges and superior figure of merit
US11217541B2 (en) 2019-05-08 2022-01-04 Vishay-Siliconix, LLC Transistors with electrically active chip seal ring and methods of manufacture
US11218144B2 (en) 2019-09-12 2022-01-04 Vishay-Siliconix, LLC Semiconductor device with multiple independent gates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01192175A (en) * 1988-01-27 1989-08-02 Hitachi Ltd Semiconductor device
JPH02102579A (en) * 1988-10-12 1990-04-16 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01192175A (en) * 1988-01-27 1989-08-02 Hitachi Ltd Semiconductor device
JPH02102579A (en) * 1988-10-12 1990-04-16 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032335A (en) * 1996-04-10 1998-02-03 Harris Corp Improved type trench mos gate device
JP2004507092A (en) * 2000-08-16 2004-03-04 フェアチャイルド　セミコンダクター　コーポレイション Thick oxide layer at bottom of trench structure in silicon
US7416947B2 (en) 2001-07-03 2008-08-26 Siliconix Incorporated Method of fabricating trench MIS device with thick oxide layer in bottom of trench
US7326995B2 (en) 2001-07-03 2008-02-05 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7291884B2 (en) 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7435650B2 (en) 2001-07-03 2008-10-14 Siliconix Incorporated Process for manufacturing trench MIS device having implanted drain-drift region and thick bottom oxide
US7033876B2 (en) 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US7009247B2 (en) 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
US6903412B2 (en) 2001-08-10 2005-06-07 Siliconix Incorporated Trench MIS device with graduated gate oxide layer
US6875657B2 (en) 2001-08-10 2005-04-05 Siliconix Incorporated Method of fabricating trench MIS device with graduated gate oxide layer
WO2003015180A3 (en) * 2001-08-10 2003-11-06 Siliconix Inc Mis device having a trench gate electrode and method of making the same
US9324858B2 (en) 2002-03-22 2016-04-26 Vishay-Siliconix Trench-gated MIS devices
US7868381B1 (en) 2002-03-22 2011-01-11 Vishay-Siliconix Structures of and methods of fabricating trench-gated MIS devices
US7028139B1 (en) 2003-07-03 2006-04-11 Veritas Operating Corporation Application-assisted recovery from data corruption in parity RAID storage using successive re-reads
US7234024B1 (en) 2003-07-03 2007-06-19 Veritas Operating Corporation Application-assisted recovery from data corruption in parity RAID storage using successive re-reads
WO2005053032A3 (en) * 2003-11-29 2005-08-25 Koninkl Philips Electronics Nv Trench insulated gate field effect transistor
US7494876B1 (en) 2005-04-21 2009-02-24 Vishay Siliconix Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
JP2007242943A (en) * 2006-03-09 2007-09-20 Fuji Electric Device Technology Co Ltd Process for fabrication of mos semiconductor device
JP2008004686A (en) * 2006-06-21 2008-01-10 Denso Corp Method of manufacturing semiconductor device
US9425305B2 (en) 2009-10-20 2016-08-23 Vishay-Siliconix Structures of and methods of fabricating split gate MIS devices
US9893168B2 (en) 2009-10-21 2018-02-13 Vishay-Siliconix Split gate semiconductor device with curved gate oxide profile
US9419129B2 (en) 2009-10-21 2016-08-16 Vishay-Siliconix Split gate semiconductor device with curved gate oxide profile
US10453953B2 (en) 2010-03-02 2019-10-22 Vishay-Siliconix Structures and methods of fabricating dual gate devices
US9577089B2 (en) 2010-03-02 2017-02-21 Vishay-Siliconix Structures and methods of fabricating dual gate devices
US8598654B2 (en) 2011-03-16 2013-12-03 Fairchild Semiconductor Corporation MOSFET device with thick trench bottom oxide
US9171906B2 (en) 2011-04-12 2015-10-27 Denso Corporation Semiconductor device having a trench gate structure and manufacturing method of the same
US9136335B2 (en) 2011-04-12 2015-09-15 Denso Corporation Semiconductor device having a trench gate structure and manufacturing method of the same
JP2014045223A (en) * 2011-04-12 2014-03-13 Denso Corp Semiconductor device manufacturing method
US11114559B2 (en) 2011-05-18 2021-09-07 Vishay-Siliconix, LLC Semiconductor device having reduced gate charges and superior figure of merit
US10234486B2 (en) 2014-08-19 2019-03-19 Vishay/Siliconix Vertical sense devices in vertical trench MOSFET
US10444262B2 (en) 2014-08-19 2019-10-15 Vishay-Siliconix Vertical sense devices in vertical trench MOSFET
US10527654B2 (en) 2014-08-19 2020-01-07 Vishay SIliconix, LLC Vertical sense devices in vertical trench MOSFET
US11217541B2 (en) 2019-05-08 2022-01-04 Vishay-Siliconix, LLC Transistors with electrically active chip seal ring and methods of manufacture
US11218144B2 (en) 2019-09-12 2022-01-04 Vishay-Siliconix, LLC Semiconductor device with multiple independent gates

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