JPH02114673A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02114673A JPH02114673A JP26852488A JP26852488A JPH02114673A JP H02114673 A JPH02114673 A JP H02114673A JP 26852488 A JP26852488 A JP 26852488A JP 26852488 A JP26852488 A JP 26852488A JP H02114673 A JPH02114673 A JP H02114673A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- insulating film
- film
- trench
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012212 insulator Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 14
- 238000001312 dry etching Methods 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明はＳＯＩ （Ｓｉ ｌ ｉｏｎ Ｏｎ Ｉｎ
５ｕｌａｔｏｒ）と通称される絶縁体又は絶縁膜表面に
Ｓｉ膜を形成したウェー八基板を用いたＭＯＳ ＦＥ
Ｔの製造方法に関し、とりわけ、そのゲート構造の新し
い製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to SOI (Silion On In
MOS FE using a wafer substrate with a Si film formed on the surface of an insulator or insulating film, commonly known as 5ulator)
The present invention relates to a method for manufacturing T, and in particular to a new method for manufacturing its gate structure.
【従来の技術１
従来ＳＯＩ基板を用いたＭＯＳ ＦＥＴは第３図に示
す如き断面構造をしていた。すなわち、Ｓｔから成る基
板２１の表面には５ｉＯ−１１１から成る絶縁膜２２が
形成されるかあるいは基板２１と絶縁膜２２とは一体と
してサファイア基板から成る等して、その上に、０．３
ｕｍ厚のＳｉ膜２３が形成され、該Ｓｉ膜２３の表面で
プレーナ２４部に平坦にＳｉｎ、膜から成るゲート絶縁
１１２５と該ゲート絶縁膜２５上にゲート電極２６が形
成され、これらゲート領域を挟んで拡散層２７が形成さ
れて成るのが通例であった。[Prior art 1] Conventionally, a MOS FET using an SOI substrate had a cross-sectional structure as shown in FIG. That is, on the surface of the substrate 21 made of St, an insulating film 22 made of 5iO-111 is formed, or the substrate 21 and the insulating film 22 are made of a sapphire substrate as one body, and then a 0.3
A Si film 23 with a thickness of 0.0 m is formed on the surface of the Si film 23, and a gate insulator 1125 made of a Si film is formed flat on the planar 24 portion, and a gate electrode 26 is formed on the gate insulating film 25. It was customary to form a diffusion layer 27 on both sides.
［発明が解決しようとする課題］
しかし、上記従来技術によるとＳＯＩ ＭＯＳＦＥＴ
のゲート長が０，２５μｍ以下になると常温での高速動
作が困難になると云う課題があった。[Problem to be solved by the invention] However, according to the above-mentioned prior art, SOI MOSFET
There is a problem in that when the gate length becomes 0.25 μm or less, high-speed operation at room temperature becomes difficult.
本発明は、かかる従来技術の課題を解決し。The present invention solves the problems of the prior art.
０．２５μｍ以下のゲート長でも、常温でも高速動作が
可能なＳＯＩ ＭＯＳ ＦＥＴのゲート構造とその
製造方法を提供することを目的とする。It is an object of the present invention to provide a gate structure of an SOI MOS FET that can operate at high speed even at room temperature even with a gate length of 0.25 μm or less, and a method for manufacturing the same.
【課題を解決するための手段１
上記課題を解決するために、本発明は、半導体装置の製
造方法に関し、絶縁体又は絶縁膜表面に形成したＳｉ膜
にはドライ・エッチングにより溝を形成し、該溝の少な
くとも側壁を含む表面にゲート絶縁膜を形成し、該ゲー
ト絶ＩｔＩｌ１表面にゲート電極を形成する手段をとる
。[Means for Solving the Problems 1] In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device, in which a groove is formed by dry etching in a Si film formed on the surface of an insulator or an insulating film. A gate insulating film is formed on the surface including at least the side walls of the groove, and a gate electrode is formed on the surface of the gate-insulated ItIl1.
［実 施 例］ 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示す、いわゆるトレンチ・
ゲートＭＯＳ ＦＥＴをＳＯＩ基板に作成した場合の
断面図である。すなわち、Ｓｉから成る基板ｌの表面に
は５ｉＯａから成る絶縁膜２が形成され、該絶縁膜表面
にＳｉ膜３が形成され、該Ｓｉ膜３にドライ・エッチン
グによりトレンチ４を形成し、該トレンチ４の側壁を含
む表面に、ゲート絶縁１１ｉ５及びその上にゲート電極
６を形成してゲート領域と成し、該ゲート領域を挟んで
拡散層７を形成したものである。FIG. 1 shows an embodiment of the present invention, a so-called trench
It is a sectional view when a gate MOS FET is created on an SOI substrate. That is, an insulating film 2 made of 5iOa is formed on the surface of a substrate l made of Si, a Si film 3 is formed on the surface of the insulating film, a trench 4 is formed in the Si film 3 by dry etching, and a trench 4 is formed in the Si film 3 by dry etching. A gate insulator 11i5 and a gate electrode 6 are formed on the surface including the sidewalls of 4 to form a gate region, and a diffusion layer 7 is formed with the gate region sandwiched therebetween.
第２図は本発明の他の実施例を示す、いわゆるヒロック
（小さい丘）ゲートＭＯＳ ＦＥＴｆｔ５ＯＩ基板上
に作成した場合の断面図である。すなわち、Ｓｉから成
る基板１１の表面にはＳ ｉ Ｏｍから成る絶縁膜１２
を形成し、該絶縁１１ｉ１２上にはＳ１膜１３を形成し
、該Ｓｉ膜１３のゲート部をヒロック状に残す形でドラ
イ・エッチングを施し、ヒロック１４を形成し、すなわ
ちヒロック１４以外のＳｔ膜１３はトレンチ状にドライ
・エッチングされることとなり、前記ヒロック１４の側
面を含む表面には、ゲート絶縁膜１５及びゲート電極１
６を形成してゲート領域となし、該ゲート領域を挟んで
拡散層１７を形成して成る。FIG. 2 is a sectional view of a so-called hillock (small hill) gate MOS FET fabricated on a ft5OI substrate, showing another embodiment of the present invention. That is, an insulating film 12 made of SiOm is formed on the surface of a substrate 11 made of Si.
An S1 film 13 is formed on the insulator 11i12, and dry etching is performed to leave the gate portion of the Si film 13 in a hillock shape to form a hillock 14, that is, the St film other than the hillock 14 is 13 is dry etched into a trench shape, and the surface including the side surfaces of the hillock 14 is covered with a gate insulating film 15 and a gate electrode 1.
6 is formed to serve as a gate region, and a diffusion layer 17 is formed sandwiching the gate region.
尚、基板ｌ及び１１と絶縁膜２及び１２とはサファイア
基板として一体となったものであっても良いことは云う
までもない。It goes without saying that the substrates 1 and 11 and the insulating films 2 and 12 may be integrated as a sapphire substrate.
［発明の効果１
本発明によりＳＯＩ ＭＯＳ ＦＥＴのゲート長は
０．２５μｍ以下、０．１ｕｍ程度になっても実質的な
チャネル長は、０．２５μｍ以上とれることとなり、ゲ
ート長寸法減少による高速動作不能と云う現象をなくす
ることができる効果がある。[Effect of the invention 1] According to the present invention, the gate length of SOI MOS FET is 0.25 μm or less, and even if it is about 0.1 μm, the actual channel length can be 0.25 μm or more, and high-speed operation is achieved by reducing the gate length dimension. It has the effect of eliminating the phenomenon of inability.
第１図及び第２図は本発明の実施例を示すＳＯＩ Ｍ
ＯＳ ＦＥＴの断面図、第３図は従来技術によるＳＯ
Ｉ ＭＯＳ ＦＥＴの断面図である。
第１図
１１．２１ ・
ｌ ２、２２ ・
ｌ ３、２３ ・
ｌ ５、２５ ・
ｌ ６、２６ ・
１７．２７ ・
・基板
・絶１ｉ１１１
・Ｓｉ膜
・トレンチ
・ゲート絶縁膜
・ゲート電極
・拡散層
・ヒロック
・プレーナ
第２図
第３図FIGS. 1 and 2 show an SOI M illustrating an embodiment of the present invention.
A cross-sectional view of the OS FET, Figure 3 is an SO according to the conventional technology.
FIG. 2 is a cross-sectional view of an I MOS FET. Figure 1 11.21 ・ l 2, 22 ・ l 3, 23 ・ l 5, 25 ・ l 6, 26 ・ 17.27 ・ ・Substrate・Exclusion1i111 ・Si film・Trench・Gate insulating film・Gate electrode・Diffusion Layer/hillock/planar Figure 2 Figure 3
Claims (1)
エッチングにより溝が形成され、該溝の少なくとも側壁
を含む表面にはゲート絶縁膜が形成され、該ゲート絶縁
膜表面にはゲート電極が形成されて成る事を特徴とする
半導体装置の製造方法。The Si film formed on the surface of the insulator or insulating film is dry.
1. A method of manufacturing a semiconductor device, comprising: forming a groove by etching; forming a gate insulating film on a surface including at least a side wall of the groove; and forming a gate electrode on the surface of the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26852488A JPH02114673A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26852488A JPH02114673A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02114673A true JPH02114673A (en) | 1990-04-26 |
Family
ID=17459720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26852488A Pending JPH02114673A (en) | 1988-10-25 | 1988-10-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02114673A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100366965B1 (en) * | 1999-07-13 | 2003-01-09 | 인터내셔널 비지네스 머신즈 코포레이션 | Soi cmos body contact through gate, self-aligned to source-drain diffusions |
| US7338862B2 (en) | 2005-03-31 | 2008-03-04 | Samsung Electronics Co., Ltd. | Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure |
-
1988
- 1988-10-25 JP JP26852488A patent/JPH02114673A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100366965B1 (en) * | 1999-07-13 | 2003-01-09 | 인터내셔널 비지네스 머신즈 코포레이션 | Soi cmos body contact through gate, self-aligned to source-drain diffusions |
| US7338862B2 (en) | 2005-03-31 | 2008-03-04 | Samsung Electronics Co., Ltd. | Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure |
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